M61522FP

M61522FP RENESAS | Alldatasheet

Document overview

• Manufacturer or author: pROVIDED bY alldatasheet.com(free datasheet download site)
• PDF pages: 18

Technical content

Rev.1.0, Sep.19.2003, page 1 of 17 M61522FP 8ch ELECTRONIC VOLUME WITH 8 INPUT SELECTOR REJ03F0034-0100Z Rev.1.0 Sep.19.2003 Feature FUNCTION FEATURE Electronic Volume 8 channel Dependant Electronic Volume with High Voltage Transistor. (0~-99dB/ 1dBstep, -∞ dB) Input Selector (1) Front L/R channel 8 Input Selector.(Main/Sub) (2) 2 channel Selector Output. Multi Channel Input All channel 2 Input Selector. External Input 2 External Input.(C/SBLch) REC Output 4 Lines REC Output (Both L and R channels) Input ATT Input ATT (0/-3/-6/-9/-12dB) Output Gain Control Output Gain Control (0/+3/+6/+9/+10/+12dB) Balance Out Built-in Balance Output (for ADC) Application Receiver, AV Amp, Mini Stereo etc. Recommended Operating Condition Rated Supply Voltage …… AVCC=7.0V(typ), AVEE=-7.0V(typ), DVDD=3.3V(typ)

Rev.1.0, Sep.19.2003, page 2 of 17 System Block Diagram MCU I/FCLOCK DATA LATCH Rch FLout FRout Cout RECOUTL Output Ga in Con trol Lch AVCC AVEE DVDD DGND SBLout SLout SRout SWout SBRout GND InputATT Balance Output L chan nel Output Ga in Con trol Output Ga in Con trol Output Ga in Con trol Output Ga in Con trol Output Ga in Con trol Output Ga in Con trol Output Ga in Con trol InputATT Balance Output R cha nnel LOUT Multi FRin Multi FLinROUT RECOUTR Multi Cin /Externa l INA Multi SBLin /Externa l INB Multi SLin Multi SBRin Multi SRin Multi SWin SUB L MAIN L MAIN R SUB R

Rev.1.0, Sep.19.2003, page 3 of 17 Block Diagram and Pin Configuration (Top View) INRF INRE INRD INRC INRB INRA AVEE INLA FLVIN INLB INLC INLD INLE INLF INLG INLH SRIN2 GND CIN1 FRIN2 COUT AVCC CLOCK DATA LA TCH DVDD GND SBLOUT SBLIN2 BALANCE R/+ FLSE LOUT SWIN2 FLIN1 SLOUT FLOUT CIN2 GND BALANCE L/- GND GND FRIN1 SBRIN1 SRIN1 SWIN1 FLIN2 GND CIN3 (Exter nal INA) SBLIN3 (Exter nal INB) BALANCE L/+ RECL4 RECL3 RECL2 RECL1LOUT NC SLIN1 SWOUT SROUT SBRIN2 SBLIN1 GND SBROUT FROUT GND FRVIN FRSELOUT GND SLIN2 BALANCE R/- GND RECR4 RECR3 RECR2 RECR1 ROUT GND INRH INRG DGND InputATT Lch BalanceOut Rch InputATT MCU I/F Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control CLOCK DATA LATCH FRchVOL FLchVOL S RchVOLS WchVOL Cch VOL S BLchVOL S LchVOLFRch FLchS BRch VOL Output Ga in Control GND SUB R S UB L MAIN L MAIN R

Rev.1.0, Sep.19.2003, page 4 of 17 Pin Description PIN No. Name Function

1 NC Non-connection terminal

2,9,12,21,24,31, 40,43,52,53,56,63 GND Analog Ground 3,4,5,6, 57,58,59,60 REC L1,L2,L3,L4 /REC R1,R2,R3,R4 Output pin of REC (Lch and Rch) 7,8 BALANCE L/+,L/- Output pin of L channel Balance Output(+/-) 10,11 BALANCE R/+,R/- Output pin of R channel Balance Output(+/-) 13,51 FLIN1/FLIN2 Input pin of FL channel (2 Input Selector) 14,50 SLIN1/SLIN2 Input pin of SL channel (2 Input Selector) 15,49 SBLIN1/SBLIN2 Input pin of SBL channel (2 Input Selector) 16,48 CIN1/CIN2 Input pin of C channel (2 Input Selector) 17,47 SWIN1/SWIN2 Input pin of SW channel (2 Input Selector) 18,46 SRIN1/SRIN2 Input pin of SR channel (2 Input Selector) 19,45 SBRIN1/SBRIN2 Input pin of SBR channel (2 Input Selector) 20,44 FRIN1/FRIN2 Input pin of FR channel (2 Input Selector)

22 FLSELOUT Output pin of FL channel volume input selector

23 FLVIN Input pin of FL channel volume

25 DVDD Power supply to internal logic circuit

29 DGND Ground of internal logic circuit

26,27,28 LATCH,DATA,CLOCK Input pin of Control trigger/data/clock

30 AVCC Positive power supply to internal analog circuit

32 FLOUT Output pin of FL channel

33 SLOUT Output pin of SL channel

34 SBLOUT Output pin of SBL channel

35 COUT Output pin of C channel

36 SWOUT Output pin of SW channel

37 SBROUT Output pin of SBR channel

38 SROUT Output pin of SR channel

39 FROUT Output pin of FR channel

41 FRVIN Input pin of FR channel volume

42 FRSELOUT Output pin of FR channel volume input selector

54 CIN3 External input pinA(Input pin of C channel)

55 SBLIN3 External input pinB(Input pin of SBL channel)

61,62 ROUT/LOUT Output pin of Input selector 64,65,66,67,68,69, 70,71 INRA,B,C,D,E,F,G,H Input pin of R channel (8 Input Selector) 73,74,75,76,77,78, 79,80 INLA,B,C,D,E,F,G,H Input pin of L channel (8 Input Selector)

72 AVEE Negative power supply to internal analog circuit

Rev.1.0, Sep.19.2003, page 5 of 17 Absolute Maximum Ratings (Ta=25°C, unless otherwise noted) Symbol Parameter Condition Ratings Unit AVCC-AVEE ±7.8 Supply voltage Power supply DVDD-GND 6.0 V Pd Power dissipation Ta ≤25°C 1250 mW Kθ Thermal derating Ta>25 °C 12.5 mW/ °C Topr Operating temperature -20~+55 °C Tstg Storage temperature -40~+125 °C 0.5 1.0 1.5 0 25 50 75 100 125 150 THERMAL DERATINGS (MAXIMUM RATING) PO WER DISSIPATION Pd(W) AMBIENT TEMPERATURE Ta (˚C) Recommended Operating Conditions (Ta=25°C, unless otherwise noted) Parameter Symbol Condition MIN TYP MAX Unit Analog supply voltage (Positive) AVCC 4.5 7.0 7.3 V Analog supply voltage (Negative) AVEE -7.3 -7.0 -4.5 V Digital supply voltage DVDD 3.0 3.3 3.6 V Logic ìH î level input voltage VIH DGND reference 2.4 — DVDD V Logic ì Lî level input voltage VIL DGND reference DGND — 0.5 V Note1: VEE≤DGND<VDD ≤VCC Note2: After applying AVCC, then apply AVEE and DVDD.

Rev.1.0, Sep.19.2003, page 6 of 17 Relationship between Data and Clock D0 D1 D29 D30 D31 D0 LATCH SIGNALH L H L H L DATA CLOCK LATCH DATA signal is readat the rising edgeof the CLOCK. Serial data (D0 - D31) is loadedat the risingedgeof the LATCH signal. Clock and Data Timings CLOCK DATA 25% 75% tr tf tcr tWHC tWLC tSD tHD LATCH tSL tr tf 25% 75% 25% 75% tr tWHC tf tSC 25%

Rev.1.0, Sep.19.2003, page 7 of 17 Timing Definition of Digital Block Limits Symbol Parameter Min typ Max Unit tcr Clock cycle time 4 — — tWHC Clock pulse width (ìHî level) 1.6 — — tWLC Clock pulse width (ìLî level) 1.6 — — tr Rising time of clock, data and latch — — 0.4 tf Falling time of clock, data and latch — — 0.4 tSD Data setup time 0.8 — — tHD Data hold time 0.8 — — tSL Latch setup time 1 — — tWHL Latch pulse width 1.6 — — tSC Clock setup time 4 — — µsec

Rev.1.0, Sep.19.2003, page 8 of 17 Data Control Specification C/SBL VOL Input Sele- ctor D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13D14 D15 D16 D17D18 D19D20D21 D22 D23D24 D25D26 D27D28 D29D30 Input Selector (MAIN) Input ATT Output Gain Control FL/FR VOL Input Sele- ctor REC Output REC Output REC Output REC Output 4 00 0 All ch Output Mute FLch Volume FRch Volume Cch Volume SWch Volume SLch Volume SRch Volume SBLch Volume SBRchVolume 000 D31 Input Selector (SUB) SW SR SL SBR VOL Input Sele- ctor 0 0Slot 0 Slot 1 Slot 2 Three type s of input format can be selected by changing the D30/D31slot setting status. (Initialize alldata of the3 formats when Digital Powersupply (DVDD) turn on).

Rev.1.0, Sep.19.2003, page 9 of 17 Setting Code Setting A B C D E F G H D0 D1 D2 D3 (1)Input Selector(MAIN/SUB) (D30=0,D31=0) ALL OFF 00 (2) Input ATT (D30=0,D31=0) 0dB -3dB 0 -6dB 0 1 Se tting D8 D9 -9dB 0 1 (3)Output Gain Control (D30=0,D31=0) 0dB +3dB 0 +6dB 0 1 Set ting D11 D12 +9dB 0 1 (6)SW/SR/SL/SBR channel VolumeInput Selector (D30=0,D31=0) Multi IN1 Multi IN2 1 Setting D18 (4)FL/FR channel Volume InputSe lector (D30=0,D3 1=0) Bypa ss Multi IN1 0 Multi IN2 1 0 Set ting D14 D15 (8)REC Output (D30=0,D31=0) Setting OFF 0 D20 RECoutput REC1 REC2 REC3 REC4 D21 D22 D23 ON 1 (7)All channel Output Mute (D30=0,D31=0) Mute OFF Mute ON 1 Setting D19 D10 -12dB 1 0 0 D13 +10dB 1 0 0 (5)C/SBL channel Volume InputSelector (D30=0,D31=0) Exter nal IN Multi IN1 0 Multi IN2 1 0 Set ting D16 D17 MAI N SUB D4 D5 D6 D7 +12dB 1 0 1 It's initia Note : Please don't input except specification data. l setting when DVDD turn on.

Rev.1.0, Sep.19.2003, page 10 of 17 ATT FLch SLch FRch SRch Cch SBLch SWch SBRch D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -12dB -13dB -14dB -15dB -16dB -17dB -18dB -19dB -20dB -21dB -22dB -23dB -24dB -25dB -26dB -27dB 0000 000 0000 001 0000 010 0000 011 0000 100 0000 101 0000 110 0000 111 0001 000 0001 001 0001 010 0001 011 0001 100 0001 101 0001 110 0001 111 0010 000 0010 001 0010 010 0010 011 0010 100 0010 101 0010 110 0010 111 0011 000 0011 001 0011 010 0011 011 ATT -29dB -30dB -31dB -32dB -33dB -34dB -35dB -36dB -37dB -38dB -39dB -40dB -41dB -42dB -43dB -44dB -45dB -46dB -47dB -48dB -49dB -50dB -51dB -52dB -53dB -54dB -55dB 001 110 0 001 110 1 001 111 0 001 111 1 010 000 0 010 000 1 010 001 0 010 001 1 010 010 0 010 010 1 010 011 0 010 011 1 010 100 0 010 100 1 010 101 0 010 101 1 010 110 0 010 110 1 010 111 0 010 111 1 011 000 0 011 000 1 011 001 0 011 001 1 011 010 0 011 010 1 011 011 0 011 011 1 -11dB -28dB FLch SLch FRch SRch Cch SBLch SWch SBRch D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 (9)8 channel Volume(FLch,FRch,Cch,SWch:D30=0,D31=1 / SLch,SRch,SBLch,SBRch:D30=1,D31=0)

Rev.1.0, Sep.19.2003, page 11 of 17 -57dB -58dB -59dB -60dB -61dB -62dB -63dB -64dB -65dB -66dB -67dB -68dB -69dB -70dB -71dB -72dB -73dB -74dB -75dB -76dB -77dB -78dB -79dB -80dB -81dB -82dB 0111 000 0111 001 0111 010 0111 011 0111 100 0111 101 0111 110 0111 111 1000 000 1000 001 1000 010 1000 011 1000 100 1000 101 1000 110 1000 111 1001 000 1001 001 1001 010 1001 011 1001 100 1001 101 1001 110 1001 111 1010 000 1010 001 1010 010 -84dB -85dB -86dB -87dB -88dB -89dB -90dB -92dB 101 001 1 101 010 0 101 010 1 101 011 0 101 011 1 101 100 0 101 100 1 101 101 0 -56dB -83dB 101 110 0 ATT FLch SLch FRch SRch Cch SBLch SWch SBRch D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 ATT FLch SLch FRch SRch Cch SBLch SWch SBRch D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 - 9 3 d B 101 110 1 - 9 4 d B 101 111 0 - 9 1 d B 101 101 1 -95dB -96dB -97dB -99dB 101 111 1 110 000 0 110 000 1 110 001 1 -/KA5 d B 111 100 0 - 9 8 d B 110 001 0 Note : Please don't input except specification data.

Rev.1.0, Sep.19.2003, page 12 of 17

Electrical Characteristics

Unless otherwise noted, Ta=25°C, AVCC=7V, AVEE=-7V, DVDD=3.3V, f=1kHz, Volume=0dB, Input ATT=0dB, Output Gain Control=0dB setting (1) Power supply characteristics Limits Parameter Symbol Test condition min typ max Unit Analog positive power circuit current AIcc With AVCC=7V and AVEE=-7V Pin30 pin current, no signal. — 40 60 mA Analog negative power Circuit current AIee With AVCC=7V and AVEE=-7V Pin72 pin current, no signal. — 40 60 mA Digital power circuit current DIdd With DVDD=5V, Pin25 pin current, no signal. — 3 6 mA

Rev.1.0, Sep.19.2003, page 13 of 17 (2) Input/Output characteristics (OVER ALL) Limits Parameter Symbol Test condition min typ max Unit Input resistance Rin 14~19, 45~50pin When each selector chooses a terminal concerned. 25 50 100 k Ω Maximum output voltage VOM THD=1%, RL=10kohm Output Gain Contro=+10dB setting 3.6 4.2 — Vrms Pass gain Gv Vi=0.3Vrms, FLAT -2.0 0 2.0 dB THD1 BW: 400Hz~30kHz, f=1kHz, Vo=0.3Vrms, RL=10kΩ — 0.005 0.05 % Total harmonic distortion THD2 BW: 400Hz~30kHz, f=1kHz, Vo=2Vrms, RL=10kΩ — 0.03 0.1 % Channels balance CBAL Input Pin71,73/Output Pin39,32 Vi=0.3Vrms, JIS-A -0.5 0 0.5 dB Vono (VOL=-∞ dB) JIS-A, Rg=0ohm Volume=-∞ dB setting — 2 6 µVrms Vono (VOL=0dB) JIS-A, Rg=0ohm Volume=0dB setting — 4 12 µVrms Output noise voltage Vonobal (Balance out) Output Pin 7, 8, 10, 11 JIS-A, Rg=0 Ω — 5 10 µVrms CS1 (Input selector) Pin73~80, Pin71~64 Vo=0.5Vrms, Rg=0Ω , RL=10k Ω , JIS-A — -80 -65 dB Input selector channel separation CS2 (Multi channel/external input selector) Pin51~44, Pin13~20, Pin54,55 Vo=0.5Vrms, Rg=0Ω , RL=10k Ω , JIS-A — -80 -65 dB CT1 (Main line) Input Pin71,73/Output Pin32,39 Vo=0.5Vrms, Rg=0Ω , RL=10k Ω , JIS-A — -80 -65 dB Crosstalk of mutual channels CT2 (Sub line) Input Pin71,73/Output Pin62,61 Vo=0.5Vrms, Rg=0Ω , RL=10k Ω , JIS-A — -80 -65 dB

Rev.1.0, Sep.19.2003, page 14 of 17 (3) 8 channel Volume characteristics Unless otherwise noted, Output Gain Control=0dB setting Limits Parameter Symbol Test condition min typ max Unit Maximum attenuation ATTmax Vi=1Vrms, JIS-A, VOL=- ∞ — -100 -95 dB Volume gain gang error of mutual channels Dvol Pin32,33,34,35,36,37,38,39 Output, Volume=0dB setting -0.5 0 +0.5 dB Cross talk of mutual channels CTvol Vo=0.5Vrms, RL=10k Ω, JIS-A, Rg=0 Ω — -80 -65 dB

Rev.1.0, Sep.19.2003, page 15 of 17 Internal Block Diagram 3 4 5 6 7 8 INLA INLB INLC INLD INLE INLF INLG INLH FRIN1 FRIN2 FLIN1 FLIN2 MCU I/F LA TCH DATA CLOCK 25 30 DVDD +3.3V AVCC +7V DGND 11 10 60 59 58 57 71INRA INRB INRC INRD INRE INRF INRG INRH CIN1 CIN2 SBLIN1 SBLIN2 SWIN1 SWIN2 50SLIN2 46SRIN2 AVEE -7V GND LOUT ROUT RECR1 RECR2 RECR3 RECR4 REC L1 REC L2 REC L3 REC L4 L+ L- R+ R- FLOUT COUT SBLOUT SWOUT SL OUT SROUT FROUT SLIN1 SRIN1 2322 0/-3/-6/-9/-12d B 0/-3/-6/-9/-12d B 0~-99d B 0~-99d B 0~-99d B 0~-99d B 0~-99d B 0~-99d B 0~-99d B Output Ga in Control 4142 CIN3 (External INA) SBLIN3 (External INB) BALANCE OUTPUT 45SBRIN2 SBRIN1 0~-99d B Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control SBROUT Input ATT Input ATT FLch VolumeInputSe lector FRc h VolumeInputSe lector Cch Volume InputSe lect or SBLch Volume InputSe lect or SWch Volume InputSe lect or SLch Volume InputSe lect or SR ch Volume InputSe lect or SBR ch Volume InputSe lect or SUB L MAI N L SUB R MAI N R NC

Rev.1.0, Sep.19.2003, page 16 of 17 Application Example ADC + - - 47k AVEE -7V 47k47k47k47k47k47k47k 47k47k47k47k47k47k47k 47k REC L4 REC L3 REC L2 REC L1 SBLIN3 (Exter nal INB) RECR4 RECR3 RECR2 RECR1 CIN3 (Exter nal INA) ROUT SBRSR SW C SBL SL L MCU AVCC DVDD 3.3V SBRIN2 SRIN2 SWIN2 CIN2 SBLIN2 SLIN2 LIN2 DGND 47k 47k R RIN2 47k SBRIN1 SRIN1 SWIN1 CIN1 SBLIN1 SLIN1 LIN1 47k RIN1 47k INRG INRF INRE INRD INRC INRB INRA INLA INLB INLC INLD INLE INLF INLG INRH INLH LOUT InputATT Lch BalanceOut Rch InputATT MCU I/F Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control Output Ga in Control CLOCK DATA LATCH FRchVOL FLchVOL S RchVOLS WchVOL Cch VOL S BLchVOL S LchVOLFRch FLchS BRch VOL Output Ga in Control S U BR S U BL MAIN L MAIN R NC

Rev.1.0, Sep.19.2003, page 17 of 17 Package Dimensions QFP80-P-1420-0.80 1.58 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 80P6N-A Plastic 80pin 14✕ 20mm body QFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.5 ——I2 1.3 ——M D 14.6 ——M E 20.6 10˚0˚ 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.8 20.220.019.8 14.214.013.8 0.20.150.13 0.450.350.3 2.8 3.05 ee e E c HE 80 65 H D D M D ME A F A1A2 L y Recommended Mount Pa d Detail F x —— 0.2 b x M MMP

© 2003. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 1.0 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem ent of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Tech nology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. An y diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 RENESAS SALES OFFICES