M61520FP RENESAS | Alldatasheet
Document overview
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Technical content
Features
Volume Six independent high-performance independent volumes on-chip (0 to 87 dB in 1 dB steps, -∞ ) Input selector L/R ch: 6 inputs with muting and attenuation REC output Two-channel record output (one channel includes a mute switch) Gain control Input gain control for FL, FR, C, SL, SR, and SW channels (0/3.6 dB) Record-input gain control (+1/+3/+4.6/+6.6 dB) Output gain control for SL, SR and C channels (0/+6 dB) Output gain control for the SW channel (+6/+10 dB) Output gain control for FL and FR channels (0/+2/+6.5/+10.5 dB) *1 Microphone-mix gain control (0/-2/+6.5/+10.5 dB) *1 Bass boost On-chip bass-boost circuits for the FL and FR channels Balanced output Internal balanced outputs for the ADC Note: 1 The microphone mix gain is coupled with output gain control for the FL and FR channels. Application Mini-component systems, TVs, etc. Recommended Operating Conditions Analog power-supply voltage range: 8.0 V to 10.0 V Digital power-supply voltage range: 3.0 V to 5.5 V
Rev.1.0, Sep.19.2003, page 2 of 15 System Block Diagram -4.4/-9.4/ -8/-13/ -11.6/ -16.6dB -4.4/-9.4/ -8/-13/ -11.6/ -16.6dB MCU I/F ATT ATT + + + + - ADC DSP DAC + + + + Gain 0/+2/+6.5/ +10.5dB Gain 0/+2/+6.5/ +10.5dB Gain 0/+6dB Gain 0/+6dB Gain 0/+6dB Gain +6/+10dB Master VOL. Master VOL. Master VOL. Master VOL. Master VOL. Master VOL. ref ref ref ref ref Bass Boost Bass Boost ATT +1/+3/ +4.6/+6.6dB Gain +1/+3/ +4.6/+6.6d B Gain Gain 0/+3.6dB Gain 0/+3.6dB Gain 0/+3.6dB Gain 0/+3.6dB Gain 0/+3.6dB Gain 0/+3.6dB PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 TCH CLOCK DATA LA REC OUT MIC IN REC OUT FL FR SL SR C SW ref Coupled
Rev.1.0, Sep.19.2003, page 3 of 15 Block Diagram with Pin Connections NC RIN6 RIN5 RIN4 RIN3 RIN2 RIN1 AVC 0/+2 /+6.5/ +10.5dB 0/+2 /+6.5/ +10.5dB Coupled 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 65666768697071727374757677787980 60k 60k 60k 60k SR SL C SW 0/+3.6dB 0/+3.6dB 0/+3.6dB 0/+3.6dB MCU I/F ATT FR FL 0/+3.6dB 0/+3.6dB ATT 0/-2/-6.5/-10.5dB L/R/FL/FR block REF SL/SR block REF C/SW block REF ATT 60k 60k 60k +1/+3/ +4.6/+6.6dB +1/+3/ +4.6/+6.6dB 60k 60k 60k 60k 60k 60k 60k 60k 60k 60k 60k 60k -4.4/-9.4/ -8/-13/ -11.6/-16.6dB -4.4/-9.4/ -8/-13/ -11.6/-16.6dB REF . +6/+10dB 0/+6dB 0/+6dB 0/+6dB Bass Boost Bass Boost FR FL SRSLCSW 60k 60k C LIN LIN LIN LIN LIN LIN NC NC LRECOU T1MICIN 1 Input selector Input selector LRECOU T2LRECIN 2 RRECIN 3 RRECOUT1 RRECOUT2ADR+OUT 4 REFOUTEX2ADR-OUT 5 REFOUTEX1ADL+OUT 6 REFINADL-OUT 7 REFOUTFRIN 8 IVSSFLIN 9 IVDDSRIN 10 AGNDSLIN 11 FROUTCIN 12 FRBB2SWIN 13 FRBB1DGND 14 FRVOLINDATA 15 FRBUFCLOCK 16 FRREFLATCH 17 BBREFOUTPORT1 18 FLOUTPORT2 19 FLBB2PORT3 20 FLBB1PORT4 21 FLVOLINPORT5 22 FLBUFPORT6 23 FLREFDVDD 24 SWREF SWBUF SWVOLIN SWOU T CREF CBUF CVOLIN COUT SLREF SLBUF SLVOLIN SLOUT RREF RBUF SRVOLIN SROUT S S Internal power supply
Rev.1.0, Sep.19.2003, page 4 of 15 Absolute Maximum Ratings Parameter Symbol Ratings Unit Conditions Max. power-supply voltage AVCC 10.5 V DVDD 6.5 V Internal power dissipation Pd 1.4 W Ambient operating temperature Topr -20 to +75 °C Storage temperature Tstg -40 to +125 °C Thermal derating curve Internal power dissipation pd [W] Ambient temperature Ta [°C] 02 5 0.5 0.7 1.0 1.4 1.5 2.0 50 75 100 125 150 Recommended Operating Condition Limits Item Symbol Min. Typ. Max. Unit Condition Power-supply voltage AVCC 8.0 9.0 10.0 V DVDD 3.0 5.0 5.5 V Input voltage (L level) VIL 0.0 0.8 V Pins 15, 16, and 17 Input voltage (H level) VIH 2.0 VDD V Pins 15, 16, and 17
Electrical characteristics
Unless otherwise noted, Ta = 25°C, AVCC = 9.0 V, DVDD = 5.0 V, f = 1 kHz, and bass boosting is switched off. (1) Power-supply characteristics Limits Item Symbol Min. Typ. Max. Unit Condition Analog power-supply circuit current AICC 20 40 mA Current on pin 73 when AVCC = 5 V, with no signal Digital power-supply circuit current Dldd 0.8 1.5 mA Current on pin 24 when DVDD = 5 V, with no signal
Rev.1.0, Sep.19.2003, page 5 of 15 (2) Input/output characteristics Limits Item Symbol Min. Typ. Max. Unit Condition Input impedance Rin 30 60 90 K Ω 66pin, 74pin Input-selector max. input voltage Vin 1.8 2.2 Vrms 66pin, 74pin FL, FR OUT max. output voltage Vom 1.8 2.2 Vrms Input on pins 8 and 9, output on pins 46 and 53, RL = 10 kΩ , THD = 1%, bass boost = on, fin = 80 Hz REC OUT max. output voltage Vomrec 1.8 2.2 Vrms Input on pins 2 and 3, output on pins 62 and 64, RL = 10 kΩ , THD = 1%, fin = 1 kHz C, SL, SR, SW max. output voltage Vomvol 1.8 2.2 Vrms Input on pins 10 and 11, output on pins 36 and 40. RL = 10 kΩ , THD = 1%, fin = 1 kHz, gain = 6 dB Bypass gain 1 Gv1 -8.0 dB Gain from pins 4 to 74 and pins 6 to 66. Bypass gain 2 Gv2 0 dB Gain from pins 8 to 53 and pins 9 to 46. Max. attenuation ATT -87 -92 dB Vo = 1 Vrms, on pins 40 and 36, JIS-A filter ADOUT output noise voltage Vadno 4.0 12.0 µVrms JIS-A filter, when no signal is present, RG = 10 kΩ , on pins 4 and 6, “normal function” settings RECOUT output noise voltage Vrecno 7.0 15.0 µVrms JIS-A filter, when no signal is present, RG = 10 kΩ , on pins 62 and 64, “normal function” settings FL, FROUT output noise voltage Vono1 7.0 15.0 µVrms 46, 53pin C, SL, SRVOLOUT output noise voltage Vvolno1 6.0 12.0 µVrms 40, 36pin SW VOLOUT output noise voltage Vvolwno1 12.0 24.0 µVrms JIS-A filter, when no signal is present, Rg = 10 kΩ , volume setting: 0 dB, “normal function” settings 28pin FL, FROUT output noise voltage Vono2 5.0 10.0 µVrms 46, 53pin C, SL, SRVOLOUT output noise voltage Vvolno2 4.0 8.0 µVrms 40, 36pin SW VOLOUT output noise voltage Vvolwno2 8.0 16.0 µVrms JIS-A filter, when no signal is present, Rg = 10 kΩ , volume setting: -∞ dB, “normal function” setting 28pin Distortion on FL, FROUT THD 0.01 0.05 % On pins 46 and 53, BW = 400 to 30 kHz, Vo = 300 mVrms, RL = 30 kΩ Distortion on REC OUT THDrec 0.01 0.05 % On pins 62 and 64, BW = 400 to 30 kHz, Vo = 300 mVrms, RL = 51 kΩ Distortion on C, SL, SR, SWVOLOUT THDvol 0.01 0.05 % On pins 40 and 36, BW = 400 to 30 kHz, Vo = 300 mVrms, RL = 30 kΩ Crosstalk between channels CT -70 -55 dB Vo = 0.5 Vrms, RL = 10 k Ω , JIS-A, Rg = 10 kΩ , between pins 46 and 53 CTrec -70 -55 dB Vo = 0.5 Vrms, RL = 30 k Ω , JIS-A, Rg = 10 kΩ , between pins 62 and 64 Normal function settings:
- Input attenuator: -8 dB
- REC input gain amp: +1 dB
- FL, FR, C, SL, SR, SW input gain amp: 0 dB
- SL, SR, C output gain amp: 0 dB
- SW output gain amp: +6 dB
Rev.1.0, Sep.19.2003, page 6 of 15 Specification of Control Data Data is fetched on rising edges of SCK; after 16 bits have been fetched, they are internally latched on the rising edge of REQ. DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SCK REQ (All data for the ten formats must be initialized each time the power is turned on.) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A 0 0 0 0 (1) Input selector (2) Input ATT (3) REC inGain (4) FL/FR inGain (5) SL/SR/C/SW inGain B 0 0 0 1 (6) MIC MIX/FL/FR Gain (7) SL/SR/C Gain (8) SW Gain (9) PORT1 (10) PORT2 (11) PORT3 (12) PORT4 (13) PORT5 (14) PORT6 C 1 0 0 0 (15) ALL MUTE (16) MIC MUTE (17) REC2 MUTE (19) Lch volume D 1 0 0 1 0 0 (18) Bass Boost (19) Rch volume E 1 0 1 0 0 0 0 (19) Cch volume F 1 0 1 1 0 0 0 (19) SLch volume G 1 1 0 0 0 0 0 (19) SRch volume H 1 1 0 1 0 0 0 (19) SWch volume Chip address 1 1 Initial internal state of the IC (state just after power is turned on): (1) Input selector : MUTE (9) OUTPUTPORT1 : PORT1OFF (18) Bass boost: No boost (2) Input ATT : -8dB (10) OUTPUTPORT2 : PORT2OFF (19) LchVOL : - ∞ dB (3) Record-input gain amp : +1dB (11) OUTPUTPORT3 : PORT3OFF (20) RchVOL : - ∞ dB (4) FL/FRch input gain amp : 0dB (12) OUTPUTPORT4 : PORT4OFF (21) CchVOL : - ∞ dB (5) SL/SR/C/SWch input gain amp : 0dB (13) OUTPUTPORT5 : PORT5OFF (22) SLchVOL : - ∞ dB (6) MIC mixing gain, (14) OUTPUTPORT6 : PORT6OFF (23) SRchVOL : - ∞ dB FL/FR output gain amp : 0dB (15) Mute all : No muting (24) SWchVOL : - ∞ dB (7) SL/SR/Cch output gain amp : 0dB (16) MIC MUTE : MUTE (8) SWch output gain amp : +6dB (17) REC2 MUTE : THRU Note: Do not input values other than those specified above. Operation is not guaranteed with other values.
Rev.1.0, Sep.19.2003, page 7 of 15 ♦ Setting just after power is turned on (1) Input selector setting (7) SL/SR/C ch output gain amp setting (15) Mute-all setting INPUT SEL. D4A D5A D6A SL/SR/C GAIN AMP D6B ALL MUTE 1 0 0 0 ♦ 0 0 ♦ No MUTE 2 0 0 1 +6dB 1 ALL MUTE 3 0 1 0 4 0 1 1 (8) SW ch output gain amp setting (16) Microphone mute setting 5 1 0 0 SW GAIN AMP D7B MIC MUTE 6 1 0 1 ♦ +6dB 0 THRU ♦ MUTE 1 1 1 +10dB 1 ♦ MUTE (2) Input ATT setting (9) Output port 1 setting (17) RECOUT2 mute setting INPUT ATT D7A D8A D9A PORT1 D8B REC2 MUTE ♦ -8dB 0 0 0 ♦ PORT1 OFF 0 ♦ THRU -13 dB 0 0 1 PORT1 ON 1 MUTE -4.4 dB 0 1 0 -9.4 dB 0 1 1 (10) Output port 2 setting (18) Bass-boost setting -11.6 dB 1 0 0 PORT2 D9B BASS BOOST -16.6 dB 1 0 1 ♦ PORT2 OFF 0 ♦ No Boost PORT2 ON 1 Boost ON (3) REC input gain amp setting REC IN GAIN D10A D11A (11) Output port 3 setting ♦ +1 dB 0 0 PORT3 D10B +3 dB 0 1 ♦ PORT3 OFF 0 +4.6 dB 1 0 PORT3 ON 1 +6.6 dB 1 1 (12) Output port 4 setting (4) FL/FR ch input gain amp setting PORT4 D11B FL/FR IN GAIN D12A ♦ PORT4 OFF 0 ♦ 0 dB 0 PORT4 ON 1 +3.6 dB 1 (13) Output port 5 setting (5) SL/SR/C/SW ch input gain amp setting PORT5 D12B SL/SR/C/SW IN GAIN D13A ♦ PORT5 OFF 0 ♦ 0 dB 0 PORT5 ON 1 +3.6 dB 1 (14) Output port 6 setting PORT6 D13B ♦ PORT6 OFF 0 PORT6 ON 1 (6) MIC mixing gain, FL/FR ch output gain setting MIC MIX GAIN FL/FR GAIN AMP D4B D5B ♦ 0 dB 0 dB 0 0 -2 dB +2 dB 0 1 -6.5 dB +6.5 dB 1 0 -10.5 dB +10.5 dB 1 1
Rev.1.0, Sep.19.2003, page 8 of 15 (19) Volume setting (FLch, FRch, SLch, SRch, SWch) Setting just after power is turned on ATT D7C~H D8C~H D9C~H D10C~H D11C~H D12C~H D13C~H ATT D7C~H D8C~H D9C~H D10C~H D11C~H D12C~H D13C~H ±0dB 0 0 0 0 0 0 0 -45.0dB 1 0 1 1 0 1 0 -1.0dB 1 0 0 0 0 0 0 -46.0dB 0 1 1 1 0 1 0 -2.0dB 0 1 0 0 0 0 0 -47.0dB 1 1 1 1 0 1 0 -3.0dB 1 1 0 0 0 0 0 -48.0dB 0 0 0 0 1 1 0 -4.0dB 0 0 1 0 0 0 0 -49.0dB 1 0 0 0 1 1 0 -5.0dB 1 0 1 0 0 0 0 -50.0dB 0 1 0 0 1 1 0 -6.0dB 0 1 1 0 0 0 0 -51.0dB 1 1 0 0 1 1 0 -7.0dB 1 1 1 0 0 0 0 -52.0dB 0 0 1 0 1 1 0 -8.0dB 0 0 0 1 0 0 0 -53.0dB 1 0 1 0 1 1 0 -9.0dB 1 0 0 1 0 0 0 -54.0dB 0 1 1 0 1 1 0 -10.0dB 0 1 0 1 0 0 0 -55.0dB 1 1 1 0 1 1 0 -11.0dB 1 1 0 1 0 0 0 -56.0dB 0 0 0 1 1 1 0 -12.0dB 0 0 1 1 0 0 0 -57.0dB 1 0 0 1 1 1 0 -13.0dB 1 0 1 1 0 0 0 -58.0dB 0 1 0 1 1 1 0 -14.0dB 0 1 1 1 0 0 0 -59.0dB 1 1 0 1 1 1 0 -15.0dB 1 1 1 1 0 0 0 -60.0dB 0 0 1 1 1 1 0 -16.0dB 0 0 0 0 1 0 0 -61.0dB 1 0 1 1 1 1 0 -17.0dB 1 0 0 0 1 0 0 -62.0dB 0 1 1 1 1 1 0 -18.0dB 0 1 0 0 1 0 0 -63.0dB 1 1 1 1 1 1 0 -19.0dB 1 1 0 0 1 0 0 -64.0dB 0 0 0 0 0 0 1 -20.0dB 0 0 1 0 1 0 0 -65.0dB 1 0 0 0 0 0 1 -21.0dB 1 0 1 0 1 0 0 -66.0dB 0 1 0 0 0 0 1 -22.0dB 0 1 1 0 1 0 0 -67.0dB 1 1 0 0 0 0 1 -23.0dB 1 1 1 0 1 0 0 -68.0dB 0 0 1 0 0 0 1 -24.0dB 0 0 0 1 1 0 0 -69.0dB 1 0 1 0 0 0 1 -25.0dB 1 0 0 1 1 0 0 -70.0dB 0 1 1 0 0 0 1 -26.0dB 0 1 0 1 1 0 0 -71.0dB 1 1 1 0 0 0 1 -27.0dB 1 1 0 1 1 0 0 -72.0dB 0 0 0 1 0 0 1 -28.0dB 0 0 1 1 1 0 0 -73.0dB 1 0 0 1 0 0 1 -29.0dB 1 0 1 1 1 0 0 -74.0dB 0 1 0 1 0 0 1 -30.0dB 0 1 1 1 1 0 0 -75.0dB 1 1 0 1 0 0 1 -31.0dB 1 1 1 1 1 0 0 -76.0dB 0 0 1 1 0 0 1 -32.0dB 0 0 0 0 0 1 0 -77.0dB 1 0 1 1 0 0 1 -33.0dB 1 0 0 0 0 1 0 -78.0dB 0 1 1 1 0 0 1 -34.0dB 0 1 0 0 0 1 0 -79.0dB 1 1 1 1 0 0 1 -35.0dB 1 1 0 0 0 1 0 -80.0dB 0 0 0 0 1 0 1 -36.0dB 0 0 1 0 0 1 0 -81.0dB 1 0 0 0 1 0 1 -37.0dB 1 0 1 0 0 1 0 -82.0dB 0 1 0 0 1 0 1 -38.0dB 0 1 1 0 0 1 0 -83.0dB 1 1 0 0 1 0 1 -39.0dB 1 1 1 0 0 1 0 -84.0dB 0 0 1 0 1 0 1 -40.0dB 0 0 0 1 0 1 0 -85.0dB 1 0 1 0 1 0 1 -41.0dB 1 0 0 1 0 1 0 -86.0dB 0 1 1 0 1 0 1 -42.0dB 0 1 0 1 0 1 0 -87.0dB 1 1 1 0 1 0 1 -43.0dB 1 1 0 1 0 1 0 ♦ -∞ dB 1 1 1 1 1 1 1 -44.0dB 0 0 1 1 0 1 0 Note: Do not input values other than those specified above. Operation is not guaranteed with other values.
Rev.1.0, Sep.19.2003, page 9 of 15 Control-Data Timing DATA t1, t2 t6 t7 t1 t4 t2 VDD=5V 2.2V 0.8V 2.2V 0.8V 2.2V 0.8V t1 t2 t10 t9t3 SCK REQ Name Symbol Min. Typ. Max. Unit Time for signal to rise t1 0.3 µs Time for signal to fall t2 0.3 µs SCK clock width t3 1 µs SCK high pulse width t4 0.4 µs SCK low pulse width t5 0.4 µs DATA setup time t6 0.4 µs DATA hold time t7 0.4 µs REQ rise hold time t8 0.8 µs REQ high pulse width t9 0.4 µs SCK setup time t10 0.4 µs
Rev.1.0, Sep.19.2003, page 10 of 15 Functional description (1) Input selector, input attenuator The IC incorporates a selector for either of two six-input channels and a mute switch. An input level for the selected ATT Balanced output for the ADC (positive phase) Balanced output for the ADC (inverse phase) 60k 60k 60k 60k 60k 60k -4.4/-9.4/ -8/-13/ -11.6/-16.6dB (2) REC block The REC signal is mixed with the MIC signal and then output. The gain of the signal for mixing with the MIC signal is selected from among +1 dB, +3, +4.6, +6.6 dB. The REC OUT2 side includes a mute switch. Fr REC input om MIC +1/+3/+4.6/+6.6dB 60k 0dB REC OUT1 MUTE SW REC OUT2 - +
Rev.1.0, Sep.19.2003, page 11 of 15 (3) Microphone mixing In the microphone-input circuit, the input signal is passed through an op-amp buffer to prevent crosstalk between FL and FR and then mixed with FL and FR. The level of the mixed signal changes in accordance with the variable gain of the output gain amplifier (see the table below). A mute switch is incorporated to improve noise characteristics when microphone mixing is not in use. Microphone input + - + Main signals FL,FR 60k MUTE SW to REC OUT Lch/Rch OUT ATT 0/-2/-6.5/-10.5dB The relation between the output gain and mixing gain FL/FR output gain Mixing gain 0 0 +2dB -2dB +6.5dB -6.5dB +10.5dB -10.5dB (4) Master volume (FL ch, FR ch, C ch, SL ch, SR ch, SW ch) This IC incorporates six independently controlled electronic volumes, each of which has low-distortion and low- noise characteristics. Volume: attenuation of 0 dB to –87 dB, settable in 1-dB steps. VOL IN VOL IN VOL IN 0/+2/+6.5/+10.5dB 0/+6dB +6/+10dBVolume: 0 dB to -87 dB in 1-dB steps, - Volume: 0 dB to -87 dB in 1-dB steps, - Volume: 0 dB to -87 dB in 1-dB steps, - VOL OUT VOL OUTVOL OUT FL/FRch SWchSL/SR/Cch
Rev.1.0, Sep.19.2003, page 12 of 15 (5) Equivalent Circuit for the Bass-Boost Circuit Input Output+ Switching-noise reduction circuit SEL 0dB Q=4 (G=10dB) Positive-feedback second-order high-pass filter circuit for the bass-boost module VIN VOUT C1 C2 Amplitude characteristics of the second-order high-pass filter Q G0 1 0 to 1dB 2 6dB 4 10dB 5 13dB 10 20dB The transfer function is described by the following expressions: VOUT Ks2 ω o2 = Q =s2 + s VIN 1 R2C1 R1C1 R1C2 R2C2 R2C2 R2C1 R1C1 R1C1R2C2 + (1-K) + (1-K)+ R1R2C1C2 R1R2C1C2 The bass-boost module includes the above positive-feedback second-order high-pass filter. In the above figure, when R1 = 1.2 kΩ , R2 = 470 kΩ , and C1 = C2 = 0.1 µF (K = +1), Fo = 70 Hz (f0 = ω o/2π), Q = 10.
Rev.1.0, Sep.19.2003, page 13 of 15 Gain Level Diagram Input D range Input D range Output D range Input D range Output D range Input D range Output D range Input D range Output D range Input D range Output D range Input D range Output D range NPUT SELECTOR> ATTSELECTOR INPUT -4.4/-9.4/ -8/-13/ -11.6/-16.6dB 2.2Vrms(9V Vcc) <REC BLOCK> MIC INPUT MIC MIXING (0dB) REC OUT 2.2Vrms(9V Vcc)2.2Vrms (9V Vcc) REC INPUT REC MIXING MIC BUF <FL,FR BUF> FL,FR IN MIC MIXI NG FL,FR BUF OUT 1.8Vrms (9V Vcc) MIC BUF 1.8Vrms (9V Vcc) INPUT GAIN (0/+3.6dB) FL,FR OU T 1.8Vrms (9V Vcc) OUTPUT GAIN Bass Boost 2.2Vrms (9V Vcc) Coupled TOTAL GAIN AD OUT TOTAL GAIN +1/+3/+4.6/+6.6dB (Mixed) <FL,FR Vol> FL,FR VOL IN <C to SW BUF> 1.8Vrms (9VVcc) INPUT GAIN (0/+3.6dB) C to SW IN TOTAL GAIN 0dB or 3.6dB C to SW BUFOUT 1.8Vrms (9VVcc) <C,SL,SR Vol> C,SL,SR VOL IN OUTPUT GAIN (0/+6dB) 1.8Vrms (9VVcc) 2.2Vrms (9VVcc) TOTAL GAIN 0dB or 6dB C,SL,SR OUT <SW Vol> SW VOL IN OUTPUT GAIN (+6/+10dB) 1.8Vrms (9VVcc) 2.2Vrms (9VVcc) TOTAL GAIN 6dB or 10dB SW OUT Caution: Do not input a signal which exceeds the power-supply voltage level.
Rev.1.0, Sep.19.2003, page 14 of 15 Application Example 9.0V 0/+2 / +6.5/+10.5dB 0/+2 / +6.5/+10.5dB Coupled 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 65666768697071727374757677787980 60k 60k 60k 60k SR SL C SW 0/+3.6dB 0/+3.6dB 0/+3.6dB 0/+3.6dB MCU I/F ATT FR FL 0/+3.6dB 0/+3.6dB ATT 0/-2/-6.5/-10.5dB 60k k 60k +1/+3 +4.6/+6.6dB +1/+3 +4.6/+6.6dB Input selector Input selector k 60k 60k 60k 60k 60k 60k 60k 60k 60k 60k 60k -4.4/-9.4 -8/-13 -11.6/-16.6dB REF . SWVOLREF SWOUT 10µ 10µ 10µ 10µ 10µ CVOLREF COUT SLVOLREF SLOUT SRVOLREF T SW C SL SR +6/ +10dB 0/ +6dB +6dB 0/ +6dB FL FR Ba ss Boost Bass Boost 0.1µ 470k FRVOLREF 0.1µ 470k Analog GND LREC OUT1 LRECOUT2 RRECOUT1 RRECOUT2 + 0.01µ 47µ REFOUTEX2 47µ 0.01µ REFOUTEX1 + 0.01µ 220µ 47µ 0.01µ REFOUTEX1 100µ 100µ ATT -4.4/-9.4/ -8/-13/ -11.6/-16.6dB L/R/FL/FR block REF SL/SR block REF C/SW block REF 60k 60k MCU SROU AnalogVCC LIN1 LIN2 LIN3 LIN4 LIN5 LIN6 RIN1 RIN2 RIN3 RIN4 RIN5 RIN6 MICIN LRECIN RRECIN ADR+OUT ADR-OUT ADL+OUT ADL-OUT FRIN FLIN SRIN SLIN CIN Rch OU T SWIN Digital GND 1.2k0.1µ PORT1 BBREFOUT Lch OUTPORT2 PORT3 PORT4 1.2k0.1µ PORT5 PORT6 FLVOLREF Digital VDD Internal power supply
Rev.1.0, Sep.19.2003, page 15 of 15 Package Dimensions QFP80-P-1420-0.80 1.58 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 80P6N-A Plastic 80pin 14✕ 20mm body QFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.5 ——I2 1.3 ——M D 14.6 ——M E 20.6 10˚0˚ 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.8 20.220.019.8 14.214.013.8 0.20.150.13 0.450.350.3 2.8 3.05 ee e E c HE 80 65 H D D M D ME A F A1A2 L y Recommended Mount Pad Detail F x —— 0.2 b x M MMP
© 2003. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 1.0 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem ent of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Tech nology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. An y diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 RENESAS SALES OFFICES