M61506FP | DigiCamel IC Datasheet

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M61506FP RENESAS | Alldatasheet

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Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 14

Technical content

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 7tENESAS Renesas Technology Corp.

MITSUBISHI SOUND PROCESSORS. M61506FP Peak hold IC for 5 band spectrum analyzer displays

DESCRIPTION

The M61506FP is a 5 band peak hold ICs that use microprocessor time division to produce serial output for spectrum analyzer displays.

FEATURES

IB 5 band peak hold elements for spectrum analyzer displays. BB Discharge time constant circuit for each band is on the chip. Hisingle 5V power supply. RECOMMENDED OPERATING CONDITIONS Supply voltage range ——— 4.5 to 6.5V Rated supply voltage ——— 5 9y SYSTEM BLOCK DIAGRAM . —_ Peak oa CO o> PFS |} Peak c> c> O Hold signal o A seal output z interface a a O O 0 90 SELA SELC SELB ENB 2tENESAS (ets }

Vecl2 Vec/2 Gen. GND2 (VccX0.3) HOLD as BPF IN. DIFOUT ENB /\\ fil[pee+] [HOLD Amp- (| er ea) couT ; 112 sELC /\\ pies] [PHOLD Lh. A feed Bacio] || ¢ ONF = SELB reese] EHO] SPEAK HOLD>_ AOUT ut 110 | seta /\\ Amp-A HOLD C RESET ae [a | O79 | vec (Notes)f1=105Hz,f2=340Hz,f3=1KHz,f4=3.4KHz,f5=10.5KHz (The value is the design value) Units Resistance :Q Capacitance: F 7tENESAS (2 1% )

(1)The audio signal amplified by Amp-A and Amp-D into BPF/peak hold circuit for spectrum analyzer display. Because the last output signal inputs into A/D of microprocessor. The Vcc,GND had better be common with Vcc,GND of A/D of maicroprocessor. It untilizes effect of common-mode rejection of Amp-D.Amp-C is the input amplifier to reject common-mode signal(noise).To get to good ground isolation. (2)BPF/peak hold circuit is fit for 5 band spectrum analyzer display. <center frequency> #1=105Hz f2=340Hz f3=1KHz 14=3.4KHz f5=10.5KHz (The value is the design value) Center frequency and Q of BPF is @0=gm/C gm:matual condactance of inside amplifier circuit (It depends on outside resistor value of Pin.No.3) C:inside capacitor Q=(R1+R2)/R1:it is fixed by inside resistor ratio. (The design value of Q is 3.5) (3)The hold capacitor of peak hold circuit is included. The reset(discharge) signal is made automatically after ending the output of hold value(Discharge pulse effect:-3dB(typ).fall refer to output value) (4)The internal output voltage of peak hold circuit is refered to Vec/2. (Pin.No.1) When it is selected by the output select circuit it appear at PHout (Pin.No.15) refered to GND. ztENESAS (3/18)

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a 180K 350K: GND2 fa | cor | o | [elo [| : [7 [ on | o | AOUT col? re K pare | ee ee ee fol [| 11 SELB Vecx0.3 20K

12 SELC 10K

Vecx0.3

13 ENB

a

15 PHOUT

fief am [1 [owe 7tENESAS (5/8 )

Thermal derating(maximum rating) ea TT IN 2 "CINE TTT =e 04 zo ei | A] I YT E < 3 loa [TN po tts | o Eo T ett | TIN o NX 0 25 50 ri) 100 125 150 AMBIENT TEMPERATURE Ta ( °C) 7ENESAS (6 4B)

Recommended operating conditions (Ta=25 °C unless otherwise noted) Vec=5V level voltage Vid ve = voc Vv (Note 1) The center frequency characteristics of BPF are determined by the resistor connected between 3pin terminal and GND.If it is necess- ary,adjust the resistor value(note:all bands will be shifted together). The Q of BPF is fixed in 3.5 by inside circuit. (Note 2) The internal output resistor of peak hold output(PIN 15)is 10k typ. The input resistance of the microprocessor must be much larger than 10k . (Note 3) The control voltage from the microprocessor must be from GND -0.3V to Vec+0.3V. If the control voltage is out of the above range. It's necessary to modify the control voltage in the above range by using resistors or diodes. 7tENESAS (7 18 )

OUTPUT CONTROL SPECIFICATION <Output select logic table> | Gio) | en | seal sero] serc| noe | Fewoiunisen| © | x | x | x [roncn | | ow [1 fo folol} | we [+ fe |e f+] 4 Peas [1 fo]+1ifo| | Poo fa fo tats] ee ee [wane [a [+ ])sfe] | Peo [+ f+t+t +] <Note 1> '‘H'=low level,'1'=high level,'X'='O'or'1' <Note 2> The output setting time is more than 10 usec. (When the output setting time is short,the output value and reset signal become unstable) PHut — = sd oe Ts(10pSec.MAX) fn SEIPET <SELECT state> (intemal signal) <Automatic Generation by inside time constant> fn RESET (intemal signal Tr(25ySec. TYP) zRENESAS (87)

12 RESET tot | l l Lil

(340Hzy & l l l l | lL 1 ot

7 Lot | l L iol

ELECTRICAL CHARACTERISTICS

(Ta=25 °C ,Vec=5.0V,PHout(Pin.No.15)RL=1MQ. unless otherwise noted. VAIN=-30dBV, f= 1KHz,ENB(Pin.No.13)=1) Parameter Symbol Condition |_min | typ | Max | Unit [ crataren | ioe | emer [-[e fe] (ENB,SELA,SELB,SELC=0) P Vo fi to f5 Measured at each output Vv Maximum output level (VAIN=-14dBV) 40 | 47 Output offset voltage Vos f1 to f5 Measured at each output mV (No signal,EN B=0/1) “genpanes wf fas fen fis | GND vesie mpatt ie eee ee f1 output level f1(fin=80 to 130Hz) f2 output level f2(fin=270 to 410Hz) £8 output level fn-0 8 to 1:2KK) f4 output level f4(fin=2.7 to 4.1KHz) 15 output level f(9N=8.0 to 19.0KH) The time from the rise of output Output response time Ts selection until the rise of PHout 5 1o | HSeC (90% of peak) <Reference> Discharge level Inside reset signal 3 Tr=25usecTYP. 2tENESAS (10/18)

wee Vec/2 Gen.

0.1 T GND2

L V REF Gen. SELECTOR 0.1 L (Vecx0.3) 1M 400K = i HOLD a8 CONTROL OUTPUT CIRCUIT. BPE IN. DIFOUT Px4 f cou Dita Px3 \\ 8 PHOLD 100K & 647 fA PHOLD |}]} 3 i = IN OF Le | Pe 30K 5 P.HOLD AOU PEAK HOLD> SPEAKHOLD: Px Amp-A SELA, 100k /\\ P HOLD C RESET

0.47 Vee

AINO4 Le | o. | 390K oot J [ro Units resistance: capacitance:F 2tENESAS (17)

= Vec/2 Gen. O.1u y GND2 VREF PHOUT It 2 V REF Gen. SELECTOR 01H | (VecX0.3) IREF 100K HOLD 5a BPF IN 7: “ DIFOUT [4 | Px4 ft PHOLD cou D {2 P.HOLD. Px /\\\\ 3 100K E= ; COM 947, {4 3 OF Le | Pe noKD . <Common-mode Noise Rejection> ground isolation AU) | PEAK HOLD>. Mao] 7 oy 10 Px1 A A SELA mp- 100K /\\ 7 HOLD C RESET 0.047. Vor CHI O4 Le | 0 | 0.047u 270K CH2 of 270K oot | 10 <Input Audio Signal> Units resistance: Q capacitance: F 7tENESAS (12 718 )

— be ae a 6 en, HHHaegag| | s| # f= O Recommended Mount Pad F TOMER HE ) Smo Nem Mae HoobouoHboOe - es a © ® 5 Caco [ot [02 | rs

6 D Ib} 035 [04 | 05 |

| et eset 92 | 028 | ys [ob }i09 [tot | 02 ° gt = [127 [= [Hers _[78 [er P Ce ee [mq | - | os! - |

3 St, a= = aa

_jbe Pepe =e g [be |= [076 [=] zu Detail G Detail Cer [= —|~762 | — | be piat = t-_] 2tENESAS (B71 )

Product Information

M61506FP specifications and overview.

Summary

Peak hold IC for 5 band spectrum analyzer displays

Description

Peak hold IC for 5 band spectrum analyzer displays

Source title M61506FP Datasheet(PDF) - Renesas Technology Corp

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