M5M29GB640C3TXAI-12

M5M29GB640VP ETC | Alldatasheet

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Technical content

67,108,864-BIT(8,388,608 - WORD BY 8-BIT / 4,194,304 - WORD BY 16-BIT) 3.3V ONLY FLASH MEMORY

• Automatic Suspend Enhance - Word/byte write suspend to read - Sector erase suspend to word/byte write - Sector erase suspend to read register report
• Automatic sector erase, full chip erase, word write and sector lock/unlock configuration
• Status Reply - Detection of program and erase operation comple- tion. - Command User Interface (CUI) - Status Register (SR)
• Data Protection Performance - Include boot sectors and parameter and main sectors to be block/unblock
• 100,000 minimum erase/program cycles
• Common Flash Interface (CFI)
• Package type: - 48-pin TSOP (12mm x 20mm)

FEATURES

• Single power supply operation - 3.0V only operation for read, erase and program operation - VCC=VPP=2.7~3.6V - VCC=12 fast production programming - 1.65V~2.5V or 2.7V~3.6V I/O Option (VCCQ) - Operating temperature:-40°C~85 °C
• Fast access time : 90/120ns
• Low power consumption - 9mA maximum active read current, f=5MHz (CMOS input) - 21mA program erase current maximum (VPP=1.65~3.6V) - 7uA typical standby current under power saving mode
• Sector architecture - Sector Erase (Sector structure : 4Kword x 2 (boot sectors), 4Kword x 6 (parameter sectors), 32Kword x
• Auto Erase (chip & sector) and Auto Program - Automatically program and verify data at specified address A15 A14 A13 A12 A11 A10 A21 A20 WE RP NC WP A19 A18 A17 A16 VCCQ GND Q15 Q14 Q13 Q12 VCC Q11 Q10 OE GND CE M5M29GB640VP M5M29GB640VP 67,108,864-BIT(8,388,608 - WORD BY 8-BIT / 4,194,304 - WORD BY 16-BIT) 3.3V ONLY FLASH MEMORY
• Automatic Suspend Enhance - Word/byte write suspend to read - Sector erase suspend to word/byte write - Sector erase suspend to read register report
• Automatic sector erase, full chip erase, word write and sector lock/unlock configuration
• Status Reply - Detection of program and erase operation comple- tion. - Command User Interface (CUI) - Status Register (SR)
• Data Protection Performance - Include boot sectors and parameter and main sectors to be block/unblock
• 100,000 minimum erase/program cycles
• Common Flash Interface (CFI)
• 64-bit Protection Register Latch-up protected to 100mA from -1V to VCC+1V
• Package type: - 48-pin TSOP (12mm x 20mm)
• Single power supply operation - 3.0V only operation for read, erase and program operation - VCC=VPP=2.7~3.6V - VCC=12 fast production programming - 1.65V~2.5V or 2.7V~3.6V I/O Option (VCCQ) - Operating temperature:-40°C~85 °C
• Fast access time : 90/120ns
• Low power consumption - 9mA maximum active read current, f=5MHz (CMOS input) - 21mA program erase current maximum (VPP=1.65~3.6V) - 7uA typical standby current under power saving mode
• Sector architecture - Sector Erase (Sector structure : 4Kword x 2 (boot sectors), 4Kword x 6 (parameter sectors), 32Kword x 7 (parameter sectors) - Top Boot
• Auto Erase (chip & sector) and Auto Program - Automatically program and verify data at specified address

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy- cling. The M5M29GB640VP uses a 2.7V~3.6V VCC sup- ply to perform the High Reliability Erase and auto Pro- gram/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V. A Command User Interface (CUI) serves as the inter- face between the system processor and internal opera- tion of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algo- rithms and timings necessary for erase, full chip erase, word/byte write and sector lock/unlock configuration op- erations. A sector erase operation erases one of the device's 32K- word sectors typically within 1.0s, 4K-word sectors typi- cally within 0.5s independent of other sectors. Each sec- tor can be independently erased minimum 100,000 times. Sector erase suspend mode allows system software to suspend sector erase to read or write data from any other sector. Writing memory data is performed in word increments of the device's 32K-word sectors typically within 0.8s and 4K-word sectors typically within 0.1s. Word program sus- pend mode enables the system to read data or execute code from any other memory array location. M5M29GB640VP features with individual sectors lock- ing by using a combination of bits thirty-nine sector lock- bits and WP , to lock and unlock sectors. The status register indicates when the WSM's sector erase, full chip erase, word program or lock configura- tion operation is done. The access time is 90/120ns (tELQV) over the operat- ing temperature range (-40°C to +80°C) and VCC supply voltage range of 2.7V~3.6V. M5M29GB640VP's power saving mode feature substan- tially reduces active current when the device is in static mode (addresses not switching). In this mode, the typi- cal ICCS current is 7uA (CMOS) at 3.0V VCC. As CE and RP are at VCC, ICC CMOS standby mode is enabled. When RP is at GND, the reset mode is enabled which minimize power consumption and provide data write protection. A reset time (tPHQV) is required from RP switching high until outputs are valid. Similarly, the device has a wake time (tPHEL) from RP-high until writes to the CUI are recognized. With RP at GND, the WSM is reset and the status register is cleared.

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 BLOCK DIAGRAM Output Buffer Output Multiplexer Data Register DQ0~DQ7 Identifier Register Command User Interface Input Buffer Status Register Data Comparator Y -Gating 32K-Word Main Sector x96 Boot Sector 0 Boot Sector 1 Parameter Sector 0 Parameter Sector 1 Parameter Sector 2 Parameter Sector 3 Parameter Sector 4 Parameter Sector 5 Main Sector 0 Main Sector 1 Main Sector 29 Main Sector 30 Write State Machine Program/Erase Voltage Switch Y DecoderInput BufferA0~A21 Address Latch Address Counter X Decoder I/O Logic VCC CS WE OE RP WP VPP VCC GND

Table 1. Pin Description data pin float to tri-state when the chip is de-selected. which drives the outputs to High Z, resets the WSM and minimizes current level. data and address is latched WE on the rising edge of the second WE pulse. OE input Output enable: gates the device's outputs during a real cycle. VCC supply Device power supply: (2.7V~3.6V). GND supply Ground voltage: all the GND pin shall not be connected.

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 SECTOR STRUCTURE (TOP) Sector Sector Size Address Range (h) Boot Sector 0 4K Word 3FF000-3FFFFF Boot Sector 1 4K Word 3FE000-3FEFFF Parameter Sector 0 4K Word 3FD000-3FDFFF Parameter Sector 1 4K Word 3FC000-3FCFFF Parameter Sector 2 4K Word 3FB000-3FBFFF Parameter Sector 3 4K Word 3F A000-3FAFFF Parameter Sector 4 4K Word 3F9000-3F9FFF Parameter Sector 5 4K Word 3F8000-3F8FFF Main Sector 0 32K Word 3F0000-3F7FFF Main Sector 1 32K Word 3E8000-3EFFFF Main Sector 2 32K Word 3E0000-3E7FFF Main Sector 3 32K Word 3D8000-3DFFFF Main Sector 4 32K Word 3D0000-3D7FFF Main Sector 5 32K Word 3C8000-3CFFFF Main Sector 6 32K Word 3C0000-3C7FFF Main Sector 7 32K Word 3B8000-3BFFFF Main Sector 8 32K Word 3B0000-3B7FFF Main Sector 9 32K Word 3A8000-3AFFFF Main Sector 10 32K Word 3A0000-3A7FFF Main Sector 11 32K Word 398000-39FFFF Main Sector 12 32K Word 390000-397FFF Main Sector 13 32K Word 388000-38FFFF Main Sector 14 32K Word 380000-387FFF Main Sector 15 32K Word 378000-37FFFF Main Sector 16 32K Word 370000-377FFF Main Sector 17 32K Word 368000-36FFFF Main Sector 18 32K Word 360000-367FFF Main Sector 19 32K Word 358000-35FFFF Main Sector 20 32K Word 350000-357FFF Main Sector 21 32K Word 348000-34FFFF Main Sector 22 32K Word 340000-347FFF Main Sector 23 32K Word 338000-33FFFF Main Sector 24 32K Word 330000-337FFF Main Sector 25 32K Word 328000-32FFFF Main Sector 26 32K Word 320000-327FFF Main Sector 27 32K Word 318000-31FFFF Main Sector 28 32K Word 310000-317FFF Main Sector 29 32K Word 308000-30FFFF Main Sector 30 32K Word 300000-307FFF

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 Sector Sector Size Address Range (h) Main Sector 31 32K Word 2F8000-2FFFFF Main Sector 32 32K Word 2F0000-2F7FFF Main Sector 33 32K Word 2E8000-2EFFFF Main Sector 34 32K Word 2E0000-2E7FFF Main Sector 35 32K Word 2D8000-2DFFFF Main Sector 36 32K Word 2D0000-2D7FFF Main Sector 37 32K Word 2C8000-2CFFFF Main Sector 38 32K Word 2C0000-2C7FFF Main Sector 39 32K Word 2B8000-2BFFFF Main Sector 40 32K Word 2B0000-2B7FFF Main Sector 41 32K Word 2A8000-2AFFFF Main Sector 42 32K Word 2A0000-2A7FFF Main Sector 43 32K Word 298000-29FFFF Main Sector 44 32K Word 290000-297FFF Main Sector 45 32K Word 288000-28FFFF Main Sector 46 32K Word 280000-287FFF Main Sector 47 32K Word 278000-27FFFF Main Sector 48 32K Word 270000-277FFF Main Sector 49 32K Word 268000-26FFFF Main Sector 50 32K Word 260000-267FFF Main Sector 51 32K Word 258000-25FFFF Main Sector 52 32K Word 250000-257FFF Main Sector 53 32K Word 248000-24FFFF Main Sector 54 32K Word 240000-247FFF Main Sector 55 32K Word 238000-23FFFF Main Sector 56 32K Word 230000-237FFF Main Sector 57 32K Word 228000-22FFFF Main Sector 58 32K Word 220000-227FFF Main Sector 59 32K Word 218000-21FFFF Main Sector 60 32K Word 210000-217FFF Main Sector 61 32K Word 208000-20FFFF Main Sector 62 32K Word 200000-207FFF Main Sector 63 32K Word 1F8000-1FFFFF Main Sector 64 32K Word 1F0000-1F7FFF Main Sector 65 32K Word 1E8000-1EFFFF Main Sector 66 32K Word 1E0000-1E7FFF Main Sector 67 32K Word 1D8000-1DFFFF Main Sector 68 32K Word 1D0000-1D7FFF Main Sector 69 32K Word 1C8000-1CFFFF Main Sector 70 32K Word 1C0000-1C7FFF

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 Sector Sector Size Address Range (h) Main Sector 71 32K Word 1B8000-1BFFFF Main Sector 72 32K Word 1B0000-1B7FFF Main Sector 73 32K Word 1A8000-1AFFFF Main Sector 74 32K Word 1A0000-1A7FFF Main Sector 75 32K Word 198000-19FFFF Main Sector 76 32K Word 190000-197FFF Main Sector 77 32K Word 188000-18FFFF Main Sector 78 32K Word 180000-187FFF Main Sector 79 32K Word 178000-17FFFF Main Sector 80 32K Word 170000-177FFF Main Sector 81 32K Word 168000-16FFFF Main Sector 82 32K Word 160000-167FFF Main Sector 83 32K Word 158000-15FFFF Main Sector 84 32K Word 150000-157FFF Main Sector 85 32K Word 148000-14FFFF Main Sector 86 32K Word 140000-147FFF Main Sector 87 32K Word 138000-13FFFF Main Sector 88 32K Word 130000-137FFF Main Sector 89 32K Word 128000-12FFFF Main Sector 90 32K Word 120000-127FFF Main Sector 91 32K Word 118000-11FFFF Main Sector 92 32K Word 110000-117FFF Main Sector 93 32K Word 108000-10FFFF Main Sector 94 32K Word 100000-107FFF Main Sector 95 32K Word 0F0000-0FFFFF

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 SECTOR STRUCTURE (BOTTOM) Sector Sector Size Address Range (h) Boot Sector 0 4K Word 00000-00FFF Boot Sector 1 4K Word 01000-01FFF Parameter Sector 0 4K Word 02000-02FFF Parameter Sector 1 4K Word 03000-03FFF Parameter Sector 2 4K Word 04000-04FFF Parameter Sector 3 4K Word 05000-05FFF Parameter Sector 4 4K Word 06000-06FFF Parameter Sector 5 4K Word 07000-07FFF Main Sector 0

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 Sector Sector Size Address Range (h) Main Sector 31 32K Word 100000-107FFF Main Sector 32 32K Word 108000-10FFFF Main Sector 33 32K Word 110000-117FFF Main Sector 34 32K Word 118000-11FFFF Main Sector 35 32K Word 120000-127FFF Main Sector 36 32K Word 128000-12FFFF Main Sector 37 32K Word 130000-137FFF Main Sector 38 32K Word 138000-13FFFF Main Sector 39 32K Word 140000-147FFF Main Sector 40 32K Word 148000-14FFFF Main Sector 41 32K Word 150000-157FFF Main Sector 42 32K Word 158000-15FFFF Main Sector 43 32K Word 160000-167FFF Main Sector 44 32K Word 168000-16FFFF Main Sector 45 32K Word 170000-177FFF Main Sector 46 32K Word 178000-17FFFF Main Sector 47 32K Word 180000-187FFF Main Sector 48 32K Word 188000-18FFFF Main Sector 49 32K Word 190000-197FFF Main Sector 50 32K Word 198000-19FFFF Main Sector 51 32K Word 1A0000-1A7FFF Main Sector 52 32K Word 1A8000-1AFFFF Main Sector 53 32K Word 1B0000-1B7FFF Main Sector 54 32K Word 1B8000-1BFFFF Main Sector 55 32K Word 1C0000-1C7FFF Main Sector 56 32K Word 1C8000-1CFFFF Main Sector 57 32K Word 1D0000-1D7FFF Main Sector 58 32K Word 1D8000-1DFFFF Main Sector 59 32K Word 1E0000-1E7FFF Main Sector 60 32K Word 1E8000-1EFFFF Main Sector 61 32K Word 1F0000-1F7FFF Main Sector 62 32K Word 1F8000-1FFFFF Main Sector 63 32K Word 200000-207FFF Main Sector 64 32K Word 208000-20FFFF Main Sector 65 32K Word 210000-217FFF Main Sector 66 32K Word 218000-21FFFF Main Sector 67 32K Word 220000-227FFF Main Sector 68 32K Word 228000-22FFFF Main Sector 69 32K Word 230000-237FFF Main Sector 70 32K Word 238000-23FFFF

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 Sector Sector Size Address Range (h) Main Sector 71 32K Word 240000-247FFF Main Sector 72 32K Word 248000-24FFFF Main Sector 73 32K Word 250000-257FFF Main Sector 74 32K Word 258000-25FFFF Main Sector 75 32K Word 260000-267FFF Main Sector 76 32K Word 268000-26FFFF Main Sector 77 32K Word 270000-277FFF Main Sector 78 32K Word 278000-27FFFF Main Sector 79 32K Word 280000-287FFF Main Sector 80 32K Word 288000-28FFFF Main Sector 81 32K Word 290000-297FFF Main Sector 82 32K Word 298000-29FFFF Main Sector 83 32K Word 2A0000-2A7FFF Main Sector 84 32K Word 2A8000-2AFFFF Main Sector 85 32K Word 2B0000-2B7FFF Main Sector 86 32K Word 2B8000-2BFFFF Main Sector 87 32K Word 2C0000-2C7FFF Main Sector 88 32K Word 2C8000-2CFFFF Main Sector 89 32K Word 2D0000-2D7FFF Main Sector 90 32K Word 2D8000-2DFFFF Main Sector 91 32K Word 2E0000-2E7FFF Main Sector 92 32K Word 2E8000-2EFFFF Main Sector 93 32K Word 2F0000-2F7FFF Main Sector 94 32K Word 2F8000-2FFFFF Main Sector 95 32K Word 300000-307FFF Main Sector 96 32K Word 308000-30FFFF Main Sector 97 32K Word 310000-317FFF Main Sector 98 32K Word 318000-31FFFF Main Sector 99 32K Word 320000-327FFF Main Sector 100 32K Word 328000-32FFFF Main Sector 101 32K Word 330000-337FFF Main Sector 102 32K Word 338000-33FFFF Main Sector 103 32K Word 340000-347FFF Main Sector 104 32K Word 348000-34FFFF Main Sector 105 32K Word 350000-357FFF Main Sector 106 32K Word 358000-35FFFF Main Sector 107 32K Word 360000-367FFF Main Sector 108 32K Word 368000-36FFFF Main Sector 109 32K Word 370000-377FFF Main Sector 110 32K Word 378000-37FFFF

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 Sector Sector Size Address Range (h) Main Sector 111 32K Word 380000-387FFF Main Sector 112 32K Word 388000-38FFFF Main Sector 113 32K Word 390000-397FFF Main Sector 114 32K Word 398000-39FFFF Main Sector 115 32K Word 3A0000-3A7FFF Main Sector 116 32K Word 3A8000-3AFFFF Main Sector 117 32K Word 3B0000-3B7FFF Main Sector 118 32K Word 3B8000-3BFFFF Main Sector 119 32K Word 3C0000-3C7FFF Main Sector 120 32K Word 3C8000-3CFFFF Main Sector 121 32K Word 3D0000-3D7FFF Main Sector 122 32K Word 3D8000-3DFFFF Main Sector 123 32K Word 3E0000-3E7FFF Main Sector 124 32K Word 3E8000-3EFFFF Main Sector 125 32K Word 3F0000-3F7FFF Main Sector 126 32K Word 3F8000-3FFFFF

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002

2 PRINCIPLES OF OPERATION

The product includes an on-chip WSM to manage sec- tor erase, word/byte write and lock-bit configuration func- tions. After initial device power-up or return from reset mode (see section on Bus Operations), the device defaults to read array mode. Manipulation of external memory con- trol pins allow array read, standby and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. All functions associated with altering memory contents-sec- tor erase, word/byte write, sector lock/unlock, status and identifier codes - are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the sector erase, word/byte write and sector lock/unlock. The internal algorithms are regu- lated by the WSM, including pulse repetition, internal verification and margining of data. Addresses and data are internally latched during write cycles. Address is latched at falling edge of CE and data latched at rising edge of WE. Writing the appropriate command outputs array data, accesses the identifier codes or outputs sta- tus register data. Interface software that initiates and polls progress of sector erase, full chip erase, word/byte write and sector lock/unlock can be stored in any sector. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Sector erase suspend allows system software to suspend a sector erase to read/write data from/to sectors other than that which is suspend. Word/byte write suspend allows system software to suspend a word/byte write to read data from any other flash memory array location. With the mechanism of sector lock, memory contents cannot be altered due to noise or unwanted operation. When RP=VIH and VCC<VLKO (lockout voltage), any data write alteration can be failure. During read opera- tion, if write VPP voltage is below VPPLK, then hard- ware level data protection is achieved. With CUI's two- step command sequence sector erase, word/byte write or sector lock/unlock, software level data protection is achieved also.

3 BUS OPERATION

The local CPU reads and writes flash memory in-sys- tem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any sector, configuration codes or status register independent of the VPP volt- age. RP can be at VIH. The first task is to write the appropriate read mode com- mand (Read Array, Read Configuration, Read Query or Read Status Register) to the CUI. Upon initial device power-up or after exit from reset mode, the device auto- matically resets to read array mode. In order to read data, control pins set for CE, OE, WE, RP and WP must be driven to active. CE and OE must be active to obtain data at the outputs. CE is the device selection control. OE is the data output (DQ0-DQ15) control and active drives the selected memory data onto the I/O bus, WE must be VIH, RP must be VIH, WP must be at VIL or VIH.

3.2 Output Disable

With OE at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0-DQ15) are placed in a high-impedance state.

3.3 Standby

CE at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0~DQ15 outputs are placed in a high- impedance state independent of OE. If deselected dur- ing sector erase, word/byte write or sector lock/unlock, the device continues functioning, and consuming active power until the operation completes.

3.4 Reset

As RP=VIL, it initiates the reset mode. The device en- ters reset/deep power down mode. However, the data stored in the memory has to be sustained at least 100ns in the read mode before the device becomes deselected

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 and output high impedance state. In read modes, RP-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP must be held low for a minimum of 100ns. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. Af- ter this wake-up interval tPHEL or tPHWL, normal op- eration is restored. The CUI is reset to read array mode and status register is set to 80H. Sector lock bit is set at lock status. During sector erase, word/byte write or sector lock/un- lock modes, RP-low will abort the operation. Memory contents being altered are no longer valid; the data may be partially erased or written. In addition, CUI will go into either array read mode or erase/write interrupted mode. When power is up and the device reset subsequently, it is necessary to read sta- tus register in order to assure the status of the device. Recognizing status register (SR.7~0) will assure if the device goes back to normal reset and enters array read mode.

3.5 Read Configuration Codes

The read configuration codes operation outputs the manu- facturer code, device code, sector lock configuration codes, and the protection register Using the manufac- turer and device codes, the system CPU can automati- cally match the device with its proper algorithms. The sector lock codes identify locked and unlocked sectors.

3.6 Write

Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VCC=2.7V-3.6V and VPP=VPPH1/2, the CUI additionally controls sec- tor erase, full chip erase, word/byte write and sector lock/ unlock. The Sector Erase command requires appropriate com- mand data and an address within the sector to be erased. The Full Chip Erase command requires appropriate com- mand data and an address within the device. The Word/ Byte Write command requires the command and address of the location to be written. Set Sector lock/unlock com- mands require the command and address within the de- vice or sector within the device (Sector Lock) to be locked. The Clear Sector Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory loca- tion. It is written when WE and CE are active (whichever goes high first). The address and data needed to ex- ecute a command are latched on the rising edge of WE or CE. Standard microprocessor write timings are used.

4 COMMAND DEFINITIONS

mands into the CUI. Table 3 defines these commands. Table 2. Bus Operation 1,2

1. Refer to DC Characteristics for VPPLK, VPP1, VPP2, VPP3 voltage.
2. X can be VIL or VIH for pin and addresses.
3. RP at GND±0.2 to ensure the lowest power consumption.
4. Refer to Table 3 for valid DIN during a write operation.
5. To program or erase the lockable sectors holds WP at VIH.

Table 3. Command Definition (1)

1. Bus operation are defined in Table 2 and referred to AC Timing Waveform.
2. X=Any address within device
3. Data is latched from the rising edge of WE or CE (whichever goes high first)

SRD=Data read from status register, see Table 6 for description of the status register bits.

1. Following the Read configuration codes command, read operation access manufacturer, device codes, sector

lock/unlock codes, see chapter 4.2.

1. Either 40H or 10H are recognized by the WSM as word/byte write setup.
2. The sector unlock operation simultaneously clear all sector lock.
3. Read Query Command is read for CFI query information.

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002

4.1 Read Array Command

Upon initial device power-up and after exit from reset mode, the device defaults to read array mode. This op- eration is also initiated by writing the Read Array com- mand. The device remains enabled for reads until an- other command is written. Once the internal WSM has started a sector erase, word/byte write or sector lock configuration the device will not recognize the Read Ar- ray command until the WSM completes its operation unless the WSM is suspended via a Sector Erase Sus- pend or Word Write Suspend command. If RP=VIL de- vice is in read Read Array command mode, this read operation no longer requires VPP . The Read Array com- mand functions independently of the VPP voltage and RP can be VIH.

4.2 Read Configuration Codes Command

The configuration code operation is initiated by writing the Read Configuration Codes command (90H). To re- turn to read array mode, write the Read Array Command (FFH). Following the command write, read cycles from addresses shown in Table 4 retrieve the manufacturer, device, sector lock configuration codes (see Table 4 for configuration code values). To terminate the operation, write another valid command. Like the Read Array com- mand, the Read Configuration Codes command func- tions independently of the VPP voltage and RP can be VIH. Following the Read Configuration Codes command, the information is shown: Code Address Data (A19-A0) (DQ15-DQ0) Manufacturer Code 00000H 00C2H Device Code 00001H 88CC/88CDH Sector Lock ConfigurationXX002H LocK - Sector is unlocked DQ0=0 - Sector is locked DQ0=1 - Sector is locked-down DQ1=1 Protection Register Lock 80 PR-LK Protection Register 81-88 PR Table 4: ID Code

4.3 Read Status Register Command

CUI writes read status command (70H). The status reg- ister may be read to determine when a sector erase, word/byte write or lock-bit configuration is complete and whether the operation completed successfully. (refer to table 6) It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the sta- tus register until another valid command is written. The status register contents are latched on the falling edge of CE or OE, whichever occurs. CE or OE must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions in- dependently of the VPP voltage. RP can be VIH.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command (50H). These bits indicate various failure conditions (see Table 6). By allowing sys- tem software to reset these bits, several operations (such as cumulatively erasing multiple sectors or writing sev- eral words/bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written on CUI. It functions indepen- dently of the applied VPP Voltage. RP can be VIH. This command is not functional during sector erase or word write suspend modes.

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002

4.5 Sector Erase Command

Erase is executed one sector at a time and initiated by a two-cycle command. A sector erase setup is first writ- ten (20H), followed by a sector erase confirm (D0H). This command sequence requires appropriate sequencing and an address within the sector to be erased. Sector pre- conditioning, erase, and verify are handled internally by the WSM. After the two-cycle sector erase sequence is written, the device automatically outputs status register data when read (see Figure 8). The CPU can detect sec- tor erase completion by analyzing the output data of the status register bit SR.7. When the sector erase is complete, status register bit SR.5 should be checked. If a sector erase error is de- tected, the status register should be cleared before sys- tem software attempts corrective actions. The CUI re- mains in read status register mode until a new com- mand is issued. This two-step command sequence of set-up followed by execution ensures that sector contents are not acciden- tally erased. An invalid sector Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable sector erasure can only occur when 2.7V~3.6V and VPP=VPPH1/2. In the ab- sence of this high voltage, sector contents are protected against erasure. If sector erase is attempted while VPP<VPPLK SR.3 and SR.5 will be set to "1". To suc- cessfully erase the boot sector, the corresponding sec- tor lock-bit must be clear first. In parameter and sectors case, it must be cleared the corresponding sector lock- bit. If sector erase is attempted when the excepting above sector being locked conditions, SR.1 and SR.5 will be set to "1". Sector erase is not functional.

4.6 Word Write Command

Word write is executed by a two-cycle command se- quence. Word write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data. The WSM then takes over, controlling the word write and write verify algorithms internally. Af- ter the word write sequence is written, the device auto- matically outputs status register data when read (see Figure 6). The CPU can detect the completion of the word write event by analyzing the status register bit SR.7. When word write is complete, status register bit SR.4 should be checked. If word write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable word writes can only occur when VCC=2.7V~3.6V and VPP=VPPH1/2. In the absence of this high voltage, memory contents are protected against word writes. If word write is attempted while VPP<VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word write requires for boot sector that WP is VIH the corresponding sector lock-bit be cleared. In parameter and main sectors case, it must be cleared the corresponding sector lock-bit. If word write is attempted when the excepting above sector being clocked conditions, SR.1 and SR.4 will be set to "1". Word write is not functional.

4.7 Sector Erase Suspend Command

The Sector Erase Suspend command (50H) allows sec- tor-erase interruption to read or word write data in an- other sector of memory. Once the sector erase process starts, writing the Sector Erase Suspend command re- quests that the WSM suspend the sector erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Sector Erase Suspend command is written. Polling status reg- ister bits SR.7 and SR.6 can determine when the sector erase operation has been suspended (both will be set to "1"). Specification tWHR12 defines the sector erase sus- pend latency. When Sector Erase Suspend command write to the CUI, if sector erase was finished, the device places read ar- ray mode. Therefore, after Sector Erase Suspend com- mand write to the CUI, Read Status Register command (70H) has to write to CUI, then status register bit SR.6 should be checked for placing the device in suspend mode. At this point, a Read Array command can be written to read data from sectors other than that which is sus- pended. A Word Write commands sequence can also be issued during erase suspend to program data in other sectors. Using the Word Write Suspend command (see Section 4.9), a word write operation can also be sus- pended. During a word write operation with sector erase suspended, status register bit SR.7 will return to "0".

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 However, SR.6 will remain "1" to indicate sector erase suspend status. The only other valid commands while sector erase is suspended are Read Status Register and sector erase Resume. After a Sector Erase Resume command is writ- ten to the flash memory, the WSM will continue the sec- tor erase process. Status register bits SR.6 and SR.7 will automatically clear. After the Erase Resume com- mand is written, the device automatically outputs status register data when read (see Figure 4). VPP must re- main at VPPH1/2 while sector erase is suspended. RP must also remain at VIL or VHH (the same RP level used for sector erase). WP must also remain at VIL or VIH (the same WP level used for sector erase). Sector cannot resume until word write operations initiated dur- ing sector erase suspend has completed. If the time between writing the Sector Erase Resume command and writing the Sector Erase Suspend com- mand is shorter than 15ms and both commands are writ- ten repeatedly, a longer time is required than standard sector erase until the completion of the operation.

4.8 Word Write Suspend Command

The Word Write Suspend command allows word write interruption to read data in other flash memory locations. Once the word write process starts, writing the Word Write Suspend command requests that the WSM sus- pend the Word write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word write operation has been suspended (both will be set to "1"). Specification tWHR11 defines the word write suspend latency. When Word Write Suspend command write to the CUI, if word write was finished, the device places read array mode. Therefore, after Word Write Suspend command write to the CUI, Read Status Register command (70H) has to write to CUI, then status register bit SR.2 should be checked for placing the device in suspend mode. At this point, a Read Array command can be written to read data from locations other than that which is sus- pended. The only other valid commands while word write is suspended are Read Status Register and Word Write Resume. After Word Write Resume command is written to the flash memory, the WSM will continue the Word write process. Status register bits SR.2 and SR.7 will automatically clear. After the Word Write Resume com- mand is written, the device automatically outputs status register data when read (see Figure 4). VPP must re- main at VPPH1/2 while in word write suspend mode. RP must also remain at VIL or VHH (the same RP level used for word write). If the time between writing the Word Write Resume com- mand and writing the Word Write Suspend command is short and both commands are written repeatedly, a longer time is required than standard word write until the comple- tion of the operation.

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002

4.9 Sector Lock/Unlock /Lock-down Command

4.9.1 Sector Locked State

The default status of all sectors when power-up or reset is locked. Any attempt on program or erase operations will result in an error on bit SR.1 of a locked sector. The status of a locked sector can be changed to unlocked or lock-down using software commands. An unlocked sec- tor can be locked by locked by writing the sector lock command sequence, 60H followed by 01H.

4.9.2 Sector Unlocked State

An unlocked sector can be programmed or erased. All unlocked sector return to the locked state when the de- vice is either reset or powered down. The status of an unlocked sector can be changed to locked or locked- down using software commands. A locked sector can be unlocked by writing unlock command sequence, 60H followed by D0H.

4.9.3 Sector Locked-Down State

Sectors which are locked-down are protected from pro- gram and erase operation; however, the protection sta- tus of three sectors cannot be changed using software commands alone. Any sector locked or unlocked can be locked-down by writing the lock-down command se- quence, 60H followed by 2FH. When the device is reset or powered down, the locked-down sectors will revert to the locked state. The status of WP will determine the function of sector lock-down and is summarized is followed: WP Sector Lock-down Description WP=0 - sectors are protected from program, erase, and lock status changes WP=1 - the sector lock-down function is disabled - an individual lock-down sector can be un locked and relocked via software command. Once WP goes low, sectors that previously locked-down returns to lock-down state regardless of any changes when WP was high.

4.9.4 Read Sector Lock Status

The lock status of every sector can be read through Read Configuration mode. To enter this mode first com- mand write 90H to the device. The next sector reads at address +00002 will output the lock status of this sec- tor. The lock status can be read from the lowest two output pins DQ0 and DQ1. DQ0, DQ0 indicates the sec- tor lock/unlock status and set by the lock command and cleared by the unlock command. When entering lock- down, the lock status is automatically set. DQ1 indi- cates lock-down status and is set by the lock-down com- mand. It cannot be further cleared by software, only by device reset or power-down. Sector Lock Configuration Table Lock Status Data Sector is unlocked DQ0=0 Sector is locked DQ0=1 Sector is locked-down DQ1=1 In addition, sector lock-down is cleared only when the device is reset or powered down.

4.9.5 Sector Locking while Erase Suspend

to unlock, lock, or lock-down a sector.

4.9.6 Status Register Error Checking

Table 5. Sector Locking State Transitions is resumed, the erase operation will complete.

Table 6. Status Register Definition unable to verify successful sector erasure. out when polling the status register.

1. 128-Bit Protection Register

5.1 Protection Register Read & Programming

mode, write the Read Array Command (FFH). address and data and program the specified location.

0 Factory 1 0 0 0 0 0 0 1

1 Factory 1 0 0 0 0 0 1 0

2 Factory 1 0 0 0 0 0 1 1

3 Factory 1 0 0 0 0 1 0 0

4 Customer 1 0 0 0 0 1 0 1

5 Customer 1 0 0 0 0 1 1 0

6 Customer 1 0 0 0 0 1 1 1

7 Customer 1 0 0 0 1 0 0 0

Table 7. Word-Wide Protection Register Addressing

5.2 Protection Register Locking

Table 8. Protection Register Memory Map

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002

6 ELECTRICAL SPECIFICATIONS

6.1 ABSOLUTE MAXIMUM RATINGS

During Read, Sector Erase, Word/Byte Voltage on Any Pin (except VCC and VPP Supply Voltage (for sector erase and VCC and VCCQ Supply Voltage WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and ex- tended exposure beyond the "Operation Conditions" may affect device reliability.

6.2.1 Capacitance (1) (TA=+25oC, f=1MHz)

Symbol Parameter Min. Max. Unit Notes T A Operating Temperature -40 +85 oC VCC1 VCC Supply Voltage 2.7 3.6 V 1 VCCQ1 I/O Supply Voltage 2.7 3.6 V 1 VCCQ2 I/O Supply Voltage 1.65 2.5 V 1 VCCQ3 I/O Supply Voltage 1.8 2.5 V 1 VPP1 Supply Voltage 1.65 3.6 V 1 VPP2 Supply Voltage 11.4 12.6 V 1 Cycling Sector Erase Cycling 2

6.2 Operating Conditions (Temperature and VCC Operating Conditions)

Symbol Parameter Typ. Max. Unit T est Condition CIN Input Capacitance 6 8 pF VIN=0.0V COUT Output Capacitance 10 12 pF VOUT=0.0V NOTE: 1.Sampled, not 100% tested. 1. Minimum DC voltage is -0.5V on input pins. During transitions, this level may undershoot to -2.0V for pe- riods <20ns. Maximum DC voltage on input/output pins to VCC+0.5V which during transition; may overshoot to VCC+2.0V for periods <20ns. 2. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. 4. VPP voltage is normally 1.65V~3.6V. Connection to supply of 11.4~12.6V can only be done for 1000 cycles on the main sectors and 25000 cycles on the parameter sectors during program/erase. VPP may be connected to 12V for a total of 80 hours maximum. NOTE: 1.VCC and VCCQ must share the same supply when they are in the VCC1 range. 2. Applying VPP=11.4~12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main sectors and 2500 cycles on the parameter sectors. VPP may be connected to 12V for a total of 80 hours maximum.

6.2.2 AC Input/Output Test Conditions

Figure 1. Transient Input/Output Reference Waveform Note:AC test inputs are driven at VCCQ/2 for a Logic "1" and 0.0V for a Logic "0". Figure 2. SWITCHING TEST CIRCUITS TEST SPECIFICATIONS

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002

6.2.3 AC Characteristic -- Read Only Operation (1)

-90 -110 tAVAV Read Cycle Time 90 110 ns tAVQV Address to Output Delay 90 110 ns tELQV CE to Output Delay 2 90 110 ns tGLQV OE to Output Delay 2 30 30 ns tPHQV RP to Output Delay 150 150 ns tELQX CE to Output in Low Z 3 0 0 ns tGLQX OE to Output in Low Z 3 0 0 ns tEHQZ CE to Output in High Z 3 20 20 ns tGHQZ OE to Output in High Z 3 20 20 ns tOH Output Hold from Address, 3 0 0 ns CE, or OE Change, Whichever Occurs First Notes: 1. See AC Waveform: Read Operations. 2. OE may be delayed up to tELQV-tGLQV after the falling edge of CE without impact on tELQV. 3. Sampled, but not 100% tested. 4. See test Configuration.

Figure 3. READ-ONLY OPERATION AC WAVEFORM

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002

6.2.5 AC Characteristic -- Write Operation

Notes: 1. Write timing characteristics during erase suspend are the same as during write-only operations. 2. Refer to Table 5 for valid AIN or DIN. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from CE or WE going low (whichever goes low last) to CE or WE going high (whichever goes high first). Hence, tWP=tWLWH=tELEH=tELWH. Similarly, Write pulse width high (tWPH) is defined from CE or WE going high (whichever goes high first) to CE or WE going low (whichever goes low first). Hence, tWPH=tWHWL=tEHEL=tEHWL. 5. See Test Configuration. -90 -110 Sym. Parameter Note Min. Min. Unit tPHWL/tPHEL RP High Recovery to WE(CE) Going Low 150 150 ns tELWL/tWLEL CE(WE) Setup to WE(CE) Going Low 0 0 ns tELEH/tWLWH WE(CE) Pulse Width 4 50 70 ns tDVWH/tDVEH Data Setup to WE(CE) Going High 2 50 60 ns tAVWH/tAVEH Address Setup to WE(CE) Going High 2 50 70 ns tWHEH/tEHWH CE(WE) Hold Time from WE(CE) High 0 0 ns tWHDX/tEHDX Data Hold Time from WE(CE) High 2 0 0 ns tWHAX/tEHAX Address Hold Time from WE(CE) High 2 0 0 ns tWHWL/tEHEL WE(CE) Pulse Width High 4 30 30 ns tVPWH/tVPEH VPP Setup to WE(CE) Going High 3 200 200 ns tQVVL VPP Hold from Valid SRD 3 0 0 ns tBHWH/tBHEH WP Setup to WE(CE) Going High 3 0 0 ns tQVBL WP Hold from Valid SRD 3 0 0 ns tWHGL WE High to OE Going Low 3 30 30 ns

Figure 4. WRITE AND ERASE OPERATION AC WAVEFORM

1. CE must be toggled low when reading Status Register Data. WE must be inactive (high) when reading Status

B.Write Program or Erase Setup Command. C.Write Valid Address and Data (for Program) or Erase Confirm Command. D.Automated Program or Erase Delay. E.Read Status Register Data (SRD): reflects completed program/erase operation. F .Write Read Array Command.

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002

6.2.5 Erase and Program Timing (1)

Vpp 1.65V-3.6V 11.4V-12.6V Symbol Parameter Note Typ(1) Max Typ(1) Max Unit tBWPB 4-KW Parameter Sector 2,3 0.10 0.30 0.03 0.12 s Word Program Time(Word) tBWMB 32-KW Main Sector 2,3 0.8 2.4 0.24 1 s Word Program Time tWHQV1/ Word Program Time 2,3 12 200 8 185 us tEHQV1 tWHQV2/ 4-KW Parameter Sector 2,3 0.5 4 0.4 4.0 s tEHQV2 Er ase Time (Byte) tWHQV3/ 32-KW Main Sector 2,3 1 5 0.6 5 s tEHQV3 Er ase Time (Byte) tWHRH1/ Program Suspend Latency 3 15 20 15 20 us tEHRH1 tWHRH2/ Erase Suspend Latency 3 15 20 15 20 us tEHRH2 Notes: 1. Typical values measured at TA=+25°C and nominal voltage. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested.

1. See Section 3.4 for a full description of these conditions.
2. If tPLPH is < 100ns the device may still reset but this is not guaranteed.
3. If RP is asserted while a sector erase or word program operation is not executing, the reset will complete within
4. Sampled, but not 100% tested.

Figure 5. RESET WAVEFORM

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002

6.2.6 DC Characteristics

ILI Input Load Current 1,2 ± 1 ± 1 ± 1 uA VCC=VCC Max. VCCQ=VCCQ Max. VIN=VCCQ or GND ILO Output Leakage 1,2 0.2 ± 10 0.2 ± 10 0.2 ± 10 uA VCC=VCC Max. Current VCCQ=VCCQ Max. VIN=VCCQ or GND ICCS VCC Standby Current 1 7 15 20 50 150 250 uA VCC=VCC Max. CE=RP=VCCQ or during Program/ Erase Suspend WP=VCCQ or GND ICCD VCC Power-Down 1,2 7 15 7 20 7 20 uA VC C=VCC Max Current VCCQ=VCCQ Max VIN=VCCQ or GND RP=GND ±0.2V ICCR VCC Read Current 1,2,3 9 18 8 15 9 15 mA VCC=VCC Max VCCQ=VCCQ Max OE=VIH, CE=VIL f=5MHz, IOUT=0mA Inputs=VIL or VIH IPPD VPP Deep Power- 1 0.2 5 0.2 5 0.2 5 uA RP=GND ±0.2V Down Current VPP < VCC IPPR VPP Read Current 1,4 2 ±15 2 ±15 2 ±15 uA VPP < VCC 50 200 50 200 50 200 uA 1,4 0.05 0.1 18 55 18 55 mA V PP=VPP1, ICCW+ VCC+VPP Program Program in Progress IPPW Current 8 22 10 30 10 30 mA VPP=VPP2(12V) Program in Progress 1,4 0.05 0.1 21 45 21 45 mA VPP=VPP1 ICCE+ VCC+VPP Erase Erase in Progress IPPE Current 8 22 16 45 16 45 mA VPP=VPP2(12V) Erase in Progress 1,4 0.05 0.1 21 45 21 45 mA VPP=VPP1 IPPES VCC+VPP Program Program or Erase + or Erase Suspend Suspend in Progress IPPWS Current 50 200 50 200 50 200 mA VPP=VPP2(12V) Program or Erase Suspend in Progress

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 Notes: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA=+25°C. 2. The test conditions VCC Max, VCCQ Max, VCC Min, and VCCQ Min refer to the maximum or minimum VCC or VCCQ voltage listed at the top of each column. VCC Max=3.3V for 0.25um 32-Mbit devices. 3. Power Savings (Mode) reduces ICCR to approximately standby levels in static operation (CMOS inputs). 4. Sampled, but not 100% tested. 5. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR. 0.22V VIH Input High Voltage 2.0 VCCQ VCCQ VCCQ VCCQ VCCQ V VCC=VCCQ Min IOL=100uA VOH Output High Voltage VCCQ VCCQ VCCQ V VCC=VCC Min -0.1V -0.1V -0.1V VCC=VCCQ Min IOH=-100uA VPPLK VPP Lock-Out Voltage 6 1.0 1.0 1.0 V Complete Write Protection VPP1 VPP during Program/ 6 1.65 3.6 V VPP2 Erase Operations 6,7 11.4 12.6 V VLKO VCC Prog/Erase 1.5 1.5 1.5 V Lock Voltage VLKO2 VCCQ Prog/Erase 1.2 1.2 1.2 V Lock Voltage

Figure 6. Automated Word Programming Flowchart Repeat for subsequent programming operations. or after a sequence of program operations. programmed before full status is checked. attempting retry or other error recovery.

Figure 7. Program Suspend/Resume Flowchart

Figure 8. Automated Sector Erase Flowchart Repeat for subsequent block erasures. or after a sequence of sector erasures. erased before full status is checked. attempting retry or other error recovery.

Figure 9. Erase Suspend/Resume Flowchart

Figure 10. Locking Operations Flowchart

Figure 11. Protection Register Programming Flowchart outside the defined space will return an error. Repeat for subsequent programming operations. or after a sequence of program operations. program operations before full status is checked. attempting retry or other error recovery.

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 8. QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX28F640C3T/B is capable of operating in the CFI mode. This mode all the host system to determine the manu- facturer of the device such as operating parameters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in Table X. The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Program Suspend, Standby mode, and Read ID mode; however, it is ignored otherwise. The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, Program Suspend or read ID mode. The command is valid only when the device is in the CFI mode. Table 9-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Address h Data h Query-unique ASCII string "QRY" 10 0051 11 0052 12 0059 Primary vendor command set and control interface ID code 13 0003 14 0000 Address for primary algorithm extended query table 15 0035 16 0000 Alternate vendor command set and control interface ID code (none) 17 0000 18 0000 Address for secondary algorithm extended query table (none) 19 0000 1A 0000 Table 9-2. CFI Mode: System Interface Data Values Description Address h Data h VCC supply, minimum (2.7V) 1B 0027 VCC supply, maximum (3.6V) 1C 0036 VPP supply, minimum (none) 1D 00B4 VPP supply, maximum (none) 1E 00C6 Typical timeout for single word/byte write (2N us) 1F 0005 Typical timeout for maximum size buffer write (2N us) 20 0000 Typical timeout for individual block erase (2N ms) 21 000A Typical timeout for full chip erase (2N ms) 22 0004 Maximum timeout for single word/byte write times (2N X Typ) 23 0004 Maximum timeout for maximum size buffer write times (2N X Typ) 24 0000 Maximum timeout for individual block erase times (2N X Typ) 25 0003 Maximum timeout for full chip erase times (not supported) 26 0000

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 Table 9-3. CFI Mode: Device Geometry Data Values Description Address h Data h Device size (2N bytes) 27 0001 Flash device interface code (02=asynchronous x8/x16) 28 0002 29 0000 Maximum number of bytes in multi-byte write (not supported) 2A 0000 2B 0000 Number of erase block regions 2C 0001 Erase block region 1 information 2D 0004 [2E,2D] = # of blocks in region -1 2E 0000 [30, 2F] = size in multiples of 256-bytes 2F 0000 30 0002 Table 9-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values Description Address h Data h Query-unique ASCII string "PRI" 35 0050 36 0052 37 0049 Major version number, ASCII 38 0031 Minor version number, ASCII 39 0030 Optional Feature & Command Support 3A 66 bit 0 Chip Erase Supported (1=yes, 0=no) 3B 00 bit 1 Suspend Erase Supported (1=yes, 0=no) 3C 00 bit 2 Suspend Program Supported (1=yes, 0=no) 3D 00 bit 3 Lock/Unlock Supported (1=yes, 0=no) bit 4 Queued Erase Supported (1=yes, 0=no) bits 5-31 revered for future use; undefined bits are "0" Sector Lock Status 3F 03 Define which bits in the sector status Register section of the Query are 40 00 implemented. bit 0 sector Lock Status Register Lock/Unlock bit (bit 0) active; (1=yes, 0=no) bit 1 sector Lock Status Register Lock/Unlock bit (bit 1) active; (1=yes, 0=no) Bits 2-15 reserved for future use. Undefined bits are 0. VCC Logic Supply Optimum Program/Erase Voltage (highest performance) 41 33 bits 7-4 BCD value in volts bits 3-0 BCD value in 100mV VPP (Programming) Supply Optimum Program/Erase Voltage 42 C0 bits 7-4 HEX value in volts bits 3-0 BCD value in 100mV

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002 ORDER INFORMATION PART NO. ACCESS TIME OPERATING STANDBY PACKAGE (ns) Current MAX.(mA) Current MAX.(uA) MX28F640C3TTC-90 90 30 5 48 Pin TSOP MX28F640C3BTC-90 90 30 5 48 Pin TSOP MX28F640C3TTC-12 120 30 5 48 Pin TSOP MX28F640C3BTC-12 120 30 5 48 Pin TSOP MX28F640C3TTI-90 90 30 5 48 Pin TSOP MX28F640C3BTI-90 90 30 5 48 Pin TSOP MX28F640C3TTI-12 120 30 5 48 Pin TSOP MX28F640C3BTI-12 120 30 5 48 Pin TSOP MX28F640C3TXAC-90 90 30 5 48 Ball CSP MX28F640C3BXAC-90 90 30 5 48 Ball CSP MX28F640C3TXAC-12 120 30 5 48 Ball CSP MX28F640C3BXAC-12 120 30 5 48 Ball CSP MX28F640C3TXAI-90 90 30 5 48 Ball CSP MX28F640C3BXAI-90 90 30 5 48 Ball CSP MX28F640C3TXAI-12 120 30 5 48 Ball CSP MX28F640C3BXAI-12 120 30 5 48 Ball CSP

P/N:PM0900 M5M29GB640VP REV. 0.3, NOV. 21, 2002

PACKAGE INFORMATION