M59MR032D120GC6T

M59MR032C STMICROELECTRONICS | Alldatasheet

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Technical content

32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst)

Figure 1. Logic Diagram

Figure 2. LFBGA Connections (Top view through package)

Figure 3. µBGA Connections (Top view through package)

M59MR032C, M59MR032D Table 1. Signal Names

DESCRIPTION

The M59MR032 is a 32 Mbit non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by- Word basis using a 1.65V to 2.0V V DD supply for the circuitry. For Program and Erase operations the necessary high voltages are generated inter- nally. The device supports synchronous burst read and asynchronous page mode read from all the blocks of the memory array; at power-up the de- vice is configured for page mode read. In synchro- nous burst mode, a new data is output at each clock cycle for frequencies up to 54MHz. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against pro- gramming and erase at Power-up. Blocks can be unprotected to make changes in the application and then reprotected. Instructions for Read/Reset, Auto Select, Write Configuration Register, Programming, Block Erase, Bank Erase, Erase Suspend, Erase Re- sume, Block Protect, Block Unprotect, Block Lock- ing, CFI Query, are written to the memory through a Command Interface (C.I.) using standard micro- processor write timings. The memory is offered in LFBGA54 and µBGA46, 0.5 mm ball pitch packages and it is supplied with all the bits erased (set to ’1’). Table 2. Absolute Maximum Ratings

1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

The M59MR032 is organized as 2Mbit by 16 bits. address lines A16-A20 are the MSB addresses. put Enable G and Write Enable W inputs. microprocessor during burst read. shown in Tables 4, 5, 6 and 7. tected and unlocked at Power-up. Table 3. Bank Size and Sectorization

Table 4. Bank A, Top Boot Block Addresses Table 5. Bank B, Top Boot Block Addresses

Table 6. Bank B, Bottom Boot Block Addresses Table 7. Bank A, Bottom Boot Block Addresses

M59MR032C, M59MR032D SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs or Data Input/Output (ADQ0- ADQ15). When Chip Enable E is at VIL and Out- put Enable G is at VIH the multiplexed address/ data bus is used to input addresses for the memo- ry array, data to be programmed in the memory ar- ray or commands to be written to the C.I. The address inputs for the memory array are latched on the rising edge of Latch Enable L . The address latch is transparent when L is at VIL. Both input data and commands are latched on the rising edge of Write Enable W. When Chip Enable E and Out- put Enable G are at VIL the address/data bus out- puts data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection status the Configuration Register status or the Status Register Data Polling bit ADQ7, the Toggle Bits ADQ6 and ADQ2, the Error bit ADQ5. The address/data bus is high imped- ance when the chip is deselected, Output Enable G is at VIH, or RP is at VIL. Address Inputs (A16-A20).The five MSB ad- dresses of the memory array are latched on the rising edge of Latch Enable L. Chip Enable (E).The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memo- ry array, while W remains at VIL. Output Enable (G).The Output Enable gates the outputs through the data buffers during a read op- eration. When G is at VIH the outputs are High im- pedance. Write Enable (W).This input controls writing to the Command Register and Data latches. Data are latched on the rising edge of W. Write Protect (WP).This input gives an addition- al hardware protection level against program or erase when pulled at V IL, as described in the Block Lock instruction description. Reset/Power-down Input (RP).The RP input provides hardware reset of the memory, and/or Power-down functions, depending on the Configu- ration Register status. Reset/Power-down of the memory is achieved by pulling RP to VIL for at least tPLPH . When the reset pulse is given, if the memory is in Read, Erase Suspend Read or Standby, it will output new valid data in tPHQ7V1 af- ter the rising edge of RP. If the memory is in Erase or Program modes, the operation will be aborted and the reset recovery will take a maximum of t PLQ7V . The memory will recover from Power- down (when enabled) in tPHQ7V2 after the rising edge of RP. Exit from Reset/Power-down changes the contents of the configuration register bits 14 and 15, setting the memory in asynchronous page mode read and power save function disabled. All blocks are protected and unlocked after a Reset/ Power-down. See Tables 29, 31 and Figure 14. Latch Enable (L ).L latches the address bits ADQ0-ADQ15 and A16-A20 on its rising edge. The address latch is transparent when L is at VIL and it is inhibited when L is at VIH. Clock (K).The clock input synchronizes the memory to the microcontroller during burst mode read operation; the address is latched on a K edge (rising or falling, according to the configuration set- tings) when L is at VIL. K is don’t care during asyn- chronous page mode read and in write operations. Wait (WAIT).WAIT is an output signal used dur- ing burst mode read, indicating whether the data on the output bus are valid or a wait state must be inserted. This output is high impedance when E or G are high or RP is at VIL, and can be configured to be active during the wait cycle or one clock cy- cle in advance.

M59MR032C, M59MR032D Bus Invert (BINV).BINV is an input/output signal used to reduce the amount of power needed to switch the external address/data bus. The power saving is achieved by inverting the data output on ADQ0-ADQ15 every time this gives an advantage in terms of number of toggling bits. In burst mode read, each new data output from the memory is compared with the previous data. If the number of transitions required on the data bus is in excess of 8, the data is inverted and the BINV signal will be driven by the memory at V OH to inform the receiv- ing system that data must be inverted before any further processing. By doing so, the actual transi- tions on the data bus will be less than 8. In a simi- lar way, when a command is given, BINV may be driven by the system at V IH to inform the memory that the data must be inverted.Like the other input/ output pins, BINV is high impedance when the chip is deselected, output enable G is at VIH or RP is at VIL; when used as an input, BINV must follow the same setup and hold timings of the data in- puts. VDD and VDDQ Supply Voltage (1.65V to 2.0V). The main power supply for all operations (Read, Program and Erase). VDD and VDDQ must be at the same voltage. V PP Program Supply Voltage (12V).VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin; if V PP is kept in a low voltage range (0 to 2V) VPP is seen as a control input, and the current absorption is limited to 5µA (0.2µA typ- ical). In this case with V PP = VIL we obtain an ab- solute protection against program or erase; with VPP = VPP1 these functions are enabled. VPP val- ue is only sampled during program or erase write cycles; a change in its value after the operation has been started does not have any effect and program or erase are carried on regularly. If V PP is used in the 11.4V to 12.6V range (VPP2 ) then the pin acts as a power supply. This supply voltage must remain stable as long as program or erase are finished. In read mode the current sunk is less then 0.5mA, while during program and erase oper- ations the current may increase up to 10mA. V SS Ground. VSS is the reference for all the volt- age measurements.

Table 8. User Bus Operations (1) Table 9. Read Electronic Signature (AS and Read CFI instructions) (1) Note: 1. Addresses are latched on the rising edge of L input. Table 10. Read Block Protection (AS and Read CFI instructions) (1) Note: 1. Addresses are latched on the rising edge of L input.

1. A locked block can be unprotected only with WP at VIH.

down and Block Locking. See Table 8. ing on the clock configuration. data is internally read and stored in a page buffer. by ADQ0 and ADQ1 address inputs. order to read the output of the memory.

Figure 4. Read Operation Sequence when CR15 = 0 (excluding Read Memory Array) system that an output delay will occur. and clock is ignored during write. dress within the bank being modified. of the Output Enable G or Write Enable W inputs. , Output Enable G or Write Enable W inputs. to VIL (see Block Lock instruction).

55h at the address 2AAh during the second cycle. blocks of the same memory bank can be erased. gram data in another block, and then resumed. Command sequencing must be followed exactly. command set and some electrical specifications. to return to Read Array mode. Table 11. Commands

of ADQ0 and ADQ1 (see Tables 9, 10 and 11). when ADQ0 is at VIH with ADQ1 at VIL. Table 12. Read Configuration Register (AS and Read CFI instructions) 0 = Address latched and data output on the falling clock edge. 1 = Address latched and data output on the rising clock edge.

Table 13. X-Latency Configuration Note: 1.Configuration codes 5 and 6 may be used only in conjunction with configuration bit CR9 set at “1” (one data every 2 clock cycles). Figure 5. X-Latency Configuration Sequence pends on the configuration register settings. (CR14 = 1) in Read Array burst mode (CR15 = 0). dresses must not be inverted). Table 14. BINV Configuration Bits

is given in Table 13 and Figure 5. after a RP pulse is significantly longer (50µs vs. 150ns) when power-down is enabled. bus are valid or a wait state must be inserted. during the wait state (see Figure 10). 15 for burst order and length. on the rising or falling edge of the clock. Table 15. Burst Order and Length Configuration

4 Words 8 Words

and ADQ5 allows verification of any possible error. erased is also possible during erase suspend. Table 16. Protection States Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status.

1. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by

ADQ1 (= 1 for a locked block) and ADQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = VIH and A0 = VIL.

1. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed
2. A WP transition to VIH on a locked block will restore the previous ADQ0 value, giving a 111 or 110.

M59MR032C, M59MR032D – the lock status is cleared for all blocks at power- up or pulling RP at VIL for at least tPLPH . The protection and lock status can be monitored for each block using the Autoselect (AS) instruc- tion. Protected blocks will output a ‘1’ on ADQ0 and locked blocks will output a ‘1’ on ADQ1. After a pulse of RP of at least tPLPH all blocks are protected and unlocked. Refer to Table 16 for a list of the protection states. Block Erase (BE) Instruction.This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles and an address within the block to be erased is given and latched into the memory. Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Cod- ed cycles. All blocks must belong to the same bank of memory; if a new block belonging to the other bank is given, the operation is aborted. The erase will start after an erase timeout period of 100µs. Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the inter- nal timer can be monitored through the level of ADQ3, if ADQ3 is '0' the Block Erase Command has been given and the timeout is running, if ADQ3 is '1', the timeout has expired and the P/ E.C. is erasing the Block(s). If the second com- mand given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before erasing to FFh. Read op- erations within the same bank, after the sixth rising edge of W or E, output the status register bits. During the execution of the erase by the P/E.C., the memory accepts only the Erase Suspend ES instruction; the Read/Reset RD instruction is ac- cepted during the 100µs time-out period. Data Polling bit ADQ7 returns '0' while the erasure is in progress and '1' when it has completed. The Tog- gle bit ADQ6 toggles during the erase operation, and stops when erase is completed. After completion the Status Register bit ADQ5 re- turns '1' if there has been an erase failure. In such a situation, the Toggle bit ADQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD in- struction is necessary in order to reset the P/E.C. Bank Erase (BKE) Instruction.This instruction uses six write cycles and is used to erase all the blocks belonging to the selected bank. The Erase Set-up command 80h is written to address 555h on the third cycle after the two Coded cycles. The Bank Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles at an address within the selected bank. If the second command given is not an erase con- firm or if the Coded cycles are wrong, the instruc- tion aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations within the same bank after the sixth rising edge of W or E output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit ADQ7 re- turns '0', then '1' on completion. The Toggle bit ADQ6 toggles during erase operation and stops when erase is completed. After completion the Status Register bit ADQ5 returns '1' if there has been an Erase Failure. Erase Suspend (ES) Instruction.In a dual bank memory the Erase Suspend instruction is used to read data within the bank where erase is in progress. It is also possible to program data in blocks not being erased. The Erase Suspend instruction consists of writing the command B0h without any specific address. No Coded Cycles are required. Erase suspend is accepted only during the Block Erase instruction execution. The Toggle bit ADQ6 stops toggling when the P/E.C. is suspended within 15µs after the Erase Suspend (ES) command has been writ- ten. The device will then automatically be set to Read Memory Array mode. When erase is sus- pended, a Read from blocks being erased will out- put ADQ2 toggling and ADQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume ER and the Program PG instruc- tions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in ADQ6 toggling when the data is being programmed. Erase Resume (ER) Instruction.If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at an address within the bank be- ing erased and without any Coded Cycle.

Table 17. Instructions (1,2) Read Memory Array until a new write cycle is initiated. Read CFI data until a new write cycle is initiated.

M59MR032C, M59MR032D Note: 1. Commands not interpreted in this table will default to read array mode. 2. For Coded cycles address inputs A11-A20 are don't care. 3. X = Don't Care. 4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com- mand cycles. 5. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. 6. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0. 7. High voltage on V PP (11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction. BL Block Lock 4 Addr. 555h 2AAh 555h Block Address Data AAh 55h 60h 2Fh BE Block Erase 6+ Addr. 555h 2AAh 555h 555h 2AAh Block Address Data AAh 55h 80h AAh 55h 30h BKE Bank Erase 6 Addr. 555h 2AAh 555h 555h 2AAh Bank Address Data AAh 55h 80h AAh 55h 10h ES Erase Suspend 1 Addr. (3) X Read until Toggle stops, then read all the data needed from any Blocks not being erased then Resume Erase.Data B0h ER Erase Resume 1 Addr. Bank Address Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time Data 30h

M59MR032C, M59MR032D STATUS REGISTER BITS P/E.C. status is indicated during execution by Data Polling on ADQ7, detection of Toggle on ADQ6 and ADQ2, or Error on ADQ5 bits. Any read at- tempt within the Bank being modified and during Program or Erase command execution will auto- matically output these five Status Register bits. The P/E.C. automatically sets bits ADQ2, ADQ5, ADQ6 and ADQ7. Other bits (ADQ0, ADQ1 and ADQ4) are reserved for future use and should be masked (see Table 18). Read attempts within the bank not being modified will output array data. Toggle bits ADQ6 and ADQ2 are affected by G and/or E cycles regardless of the bank in which these cycles refer to. This means that toggle bits are in a state that depends on the amount of ac- cesses to both banks and not only to the bank where erasing or programming is on going. Status Register Bits must be accessed according to the device configuration (see Figure 4). Data Polling Bit (ADQ7).When Programming operations are in progress, this bit outputs the complement of the bit being programmed on ADQ7. In case of a double word program opera- tion, the complement is done on ADQ7 of the last word written to the command interface, i.e. the data written in the fifth cycle. During Erase opera- tion, it outputs a '0'. After completion of the opera- tion, ADQ7 will output the bit last programmed or a '1' after erasing. Data Polling is valid and only ef- fective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for erase. It must be performed at the ad- dress being programmed or at an address within the block being erased. See Figure 17 for the Data Polling flowchart and Figure 15 for the Data Polling waveforms. ADQ7 will also flag the Erase Sus- pend mode by switching from '0' to '1' at the start of the Erase Suspend. In order to monitor ADQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Suspend mode, ADQ7 will output '1' if the read is attempted on a block being erased and the data value on other blocks. During Pro- gram operation in Erase Suspend Mode, ADQ7 will have the same behavior as in the normal pro- gram execution outside of the suspend mode. Toggle Bit (ADQ6).When Programming or Eras- ing operations are in progress, successive at- tempts to read ADQ6 will output complementary data. ADQ6 will toggle following toggling of either G , or E when G is at VIL. The operation is complet- ed when two successive reads yield the same out- put data. The next read will output the bit last programmed or a '1' after erasing. The toggle bit ADQ6 is valid only during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. ADQ6 will be set to '1' if a Read operation is attempted on an Erase Sus- pend block. When erase is suspended ADQ6 will toggle during programming operations in a block different from the block in Erase Suspend. Either E or G toggling will cause ADQ6 to toggle. See Figure 18 for Toggle Bit flowchart and Figure 16 for Toggle Bit waveforms. Toggle Bit (ADQ2).This toggle bit, together with ADQ6, can be used to determine the device status during the Erase operations. During Erase Sus- pend a read from a block being erased will cause ADQ2 to toggle. A read from a block not being erased will output data. ADQ2 will be set to '1' dur- ing program operation. After erase completion and if the error bit ADQ5 is set to '1', ADQ2 will toggle if the faulty block is addressed. Error Bit (ADQ5).This bit is set to '1' by the P/ E.C. when there is a failure of programming or block erase, that results in invalid data in the mem- ory block. In case of an error in block erase or pro- gram, the block in which the error occurred or to which the programmed data belongs, must be dis- carded. Other Blocks may still be used. The error bit resets after a Read/Reset (RD) instruction. In case of success of Program or Erase, the error bit will be set to '0'. Erase Timer Bit (ADQ3).This bit is set to ‘0’ by the P/E.C. when the last block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the erase time- out period is finished, ADQ3 returns to ‘1’, in the range of 80µs to 120µs.

Table 18. Status Register Bits (1) Note: 1. Status Register bits do not consider BINV.

1. DQ7 and DQ2 require a valid address when reading status information.

and all blocks are protected and unlocked. quired VDD program and erase currents.

Table 19. Query Structure Overview detailed in Tables 20, 21 and 22. Query data are always presented on the lowest order data outputs. Table 20. CFI Query Identification String Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15 are ‘0’. that can be read from the Flash memory device. software to configure itself when necessary.

Table 21. CFI Query System Interface Information

Table 22. Device Geometry Definition

1. x specifies the number of regions within the device containing one or more
2. By definition, symmetrically block devices have only one blocking region.

size. The value z = 0 is used for 128 byte block size.

Table 23. Primary Algorithm-Specific Extended Query Table field of optional features follows at the end of the bit-30 field.

Table 24. Burst Read Information Table 25. Security Code Area mode data output width. 00h indicates no read page buffer. the burst data output width.

Table 28. DC Characteristics Note: 1. Sampled only, not 100% tested.

1. VPP may be connected to 12V power supply for a total of less than 100 hrs.

Table 29. Asynchronous Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV .

Figure 8. Asynchronous Read AC Waveforms Note: Write Enable (W) = High.

Figure 9. Page Read AC Waveforms

Table 30. Synchronous Burst Read AC Characteristics

Figure 10. Synchronous Burst Read VALID ADDRESS VALID D. VALID D. Note: 1. The number of clock cycles to be inserted depends upon the x-latency set in the read configuration register.

1. WAIT signal can be configured to be active during wait state or one cycle below wait state.
2. WAIT signal is asserted only when burst length is configured as continuous (see Burst Read section for further information).

Figure 11. Synchronous Burst Read (with Data Hold Configuration bit CR9 = 1) Note: 1. WAIT signal can be configured to be active during wait state or one cycle below wait state.

1. WAIT signal is asserted only when burst length is configured as continuous (see Burst Read section for further information).

Table 31. Write AC Characteristics, Write Enable Controlled

Figure 12. Write AC Waveforms, W Controlled

Table 32. Write AC Characteristics, Chip Enable Controlled

Figure 13. Write AC Waveforms, E Controlled

Figure 14. Read and Write AC Waveforms, RP Related Table 33. Read and Write AC Characteristic, RP Related

Table 34. Program, Erase Times and Program, Erase Endurance Cycles erase should perform significantly better.

1. Excludes the time needed to execute the sequence for program instruction.
2. Same timing value if VPP = 12V.

Table 35. Data Polling and Toggle Bits AC Characteristics (1) Note: 1. All other timings are defined in Read AC Characteristics table.

Figure 15. Data Polling ADQ7 AC Waveforms (when Configuration Register bit CR15 = 1) Note: Latch Enable (L) = High.

Figure 16. Data Toggle DQ6, DQ2 AC Waveforms (when Configuration Register bit CR15 = 1)

Table 36. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. Table 37. Daisy Chain Ordering Scheme vice, please contact the STMicroelectronics Sales Office nearest to you.

Table 38. Revision History

Table 39. LFBGA54 - 10 x 4 ball array, 0.5 mm pitch, Package Mechanical Data Figure 19. LFBGA54 - 10 x 4 ball array, 0.5 mm pitch, Bottom View Package Outline

Table 40. µBGA46 - 10 x 4 ball array, 0.5 mm pitch, Package Mechanical Data Figure 20. µBGA46 - 10 x 4 ball array, 0.5 mm pitch, Bottom View Package Outline

M59MR032C, M59MR032D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. © 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.