M59DR032EB

M59DR032EA STMICROELECTRONICS | Alldatasheet

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32 Mbit (2Mb x 16, Dual Bank, Page )

Figure 1. Packages

and at the bottom for the M59DR032EB. program in any other block, and then resumed. ings necessary for program and erase operations. Protection Register Memory Map. supplied with all the bits erased (set to ‘1’). Figure 2. Logic Diagram Table 1. Signal Names

Figure 3. TFBGA Connections (Top view through package) Table 2. Bank Organization

Figure 4. Security Block and Protection Register Memory Map

M59DR032EA, M59DR032EB SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A20).The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine. During a write operation the address inputs are latched on the falling edge of Chip Enable E or Write Enable W, whichever occurs last. Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address dur- ing a Bus Read operation or input a command or the data to be programmed during a Write Bus op- eration. Both input data and commands are latched on the rising edge of Write Enable W . The data output is the Memory Array, the Common Flash Interface, the Electronic Signature Manufacturer or Device codes, the Block Protection status, the Configura- tion Register status or the Status Register Data depending on the address. The data bus is high impedance when the chip is deselected, Output Enable G is at VIH, or RP is at VIL. Chip Enable (E). The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. When Chip Enable is at V IH the device is deselected and the power con- sumption is reduced to the standby level. Output Enable (G).The Output Enable gates the outputs through the data buffers during a read op- eration. When Output Enable is at VIH the outputs are high impedance. Write Enable (W).The Write Enable controls the Bus Write operation of the memory’s Command Interface. Write Protect (WP). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V IL, the locked-down blocks cannot be locked or unlocked. When Write Protect is at VIH, the Lock-Down is disabled and the locked-down blocks can be locked or unlocked. (refer to Table 10, Lock Sta- tus). Reset/Power-Down Input (RP ).The Reset/Pow- er-Down input provides hardware reset of the memory, and/or Power-Down functions, depend- ing on the Configuration Register status. A Reset or Power-Down of the memory is achieved by pull- ing RP to VIL for at least tPLPH . The Reset/Power-Down function is set in the Con- figuration Register (see Set Configuration Regis- ter command). If it is set to ‘0’ the Reset function is enabled, if it is set to ‘1’ the Power-Down function is enabled. After a Reset or Power-Up the power save function is disabled and all blocks are locked. The memory Command Interface is reset on Pow- er Up to Read Array. Either Chip Enable or Write Enable must be tied to V IH during Power Up to al- low maximum security and the possibility to write a command on the first rising edge of Write Enable. After a Reset, when the device is in Read, Erase Suspend Read or Standby, valid data will be out- put t PHQ7V1 after the rising edge of RP. If the de- vice is in Erase or Program, the operation will be aborted and the reset recovery will take a maxi- mum of t PLQ7V . The memory will recover from Power-Down tPHQ7V2 after the rising edge of RP. See Tables 17, 18 and Figure 11. VDD and VDDQ Supply Voltage (1.65V to 2.2V). VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase). V DDQ provides the power supply to the I/O pins. VDD and VDDQ must be at the same voltage. VPP Programming Voltage (11.4V to 12.6V).VPP provides a high voltage power supply for fast fac- tory programming. VPP is required to use the Dou- ble Word and Quadruple Word Program commands. VSS Ground. VSS ground is the reference for the core supply. It must be connected to the system ground. Note: Each device in a system should have VDD , VDDQ and VPP decoupled with a 0.1µF ca- pacitor close to the pin. See Figure 6, AC Mea- surement Load Circuit. The PCB trace widths should be sufficient to carry the required VPP program and erase currents.

and Reset/Power-Down, see Table 3. the falling edge of W or E whichever occurs last. nals do not start a write cycle. , Output Enable G or Write Enable W inputs. an address within the bank being modified. Table 3. Bus Operations

M59DR032EA, M59DR032EB COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings and verifies the correct execution of the Program and Erase commands. Two bus write cycles are required to unlock the Command Interface. They are followed by a setup or confirm cycle. The increased number of write cycles is to ensure maximum data security. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface is reset to Read mode when power is first applied or exiting from Reset. Command sequences must be followed exactly. Any invalid combination of commands will reset the device to Read mode Read/Reset Command. The Read/Reset com- mand returns the device to Read mode. One Bus Write cycle is required to issue the Read/Reset command and return the device to Read mode. Subsequent Read operations will read the ad- dressed location and output the data. The write cy- cle can be preceded by the unlock cycles but it is not mandatory. Read CFI Query Command. The Read CFI Query command is used to read data from the Common Flash Interface (CFI) and the Electronic Signature (Manufacturer or the Device Code, see Table 5). The Read CFI Query Command consists of one Bus Write cycle. Once the command is is- sued the device enters Read CFI mode. Subse- quent Bus Read operations read the Common Flash Interface or Electronic Signature. Once the device has entered Read CFI mode, only the Read/Reset command should be used and no oth- er. Issuing the Read/Reset command returns the device to Read mode. See Appendix B, Common Flash Interface, Tables 31, 32, and 33 for details on the information con- tained in the Common Flash Interface memory ar- ea. Auto Select Command. The Auto Select com- mand uses the two unlock cycles followed by one write cycle to any bank address to setup the com- mand. Subsequent reads at any address will out- put the Block Protection status, Protection Register and Protection Register Lock or the Con- figuration Register status depending on the levels of A0 and A1 (see Tables 6, 7 and 8). Once the Auto Select command has been issued only the Read/Reset command should be used and no oth- er. Issuing the Read/Reset command returns the device to Read mode. Set Configuration Register Command.The M59DR032E contains a Configuration Register, see Table 7, Configuration Register. It is used to define the status of the Reset/Power- Down functions. The value for the Configuration Register is always presented on A0-A15, the other address bits are ignored. Address input A10 de- fines the status of the Reset/Power-Down func- tions. If it is set to ‘0’ the Reset function is enabled, if it is set to ‘1’ the Power-Down function is en- abled. At Power Up the Configuration Register bit is set to ‘0’. The Set Configuration Register command is used to write a new value to the Configuration Register. The command uses the two unlock cycles followed by one write cycle to setup the command and a further write cycle to write the data and confirm the command. Program Command. The Program command uses the two unlock cycles followed by a write cy- cle to set up the command and a further write cycle to latch the Address and Data and start the Pro- gram Erase Controller. Read operations within the same bank output the Status Register after pro- gramming has started. Note that the Program command cannot change a bit set to ’0’ back to ’1’. One of the Erase Com- mands must be used to set all the bits in a block or in the whole bank from ’0’ to ’1’. If the Program command is used to try to set a bit from ‘0’ to ‘1’ Status Register Error bit DQ5 will be set to ‘1’, only if V PP is in the range of 11.4V to 12.6V. Double Word Program Command. This feature is offered to improve the programming throughput by writing a page of two adjacent Words in parallel. The V PP supply voltage is required to be from 11.4V to 12.6V for the Double Word Program com- mand. The command uses the two unlock cycles followed by a write cycle to set up the command. A further two cycles are required to latch the address and data of the two Words and start the Program Erase Controller. The addresses must be the same except for the A0. The Double Word Program command can be executed in Bypass mode to skip the two unlock cycles. Note that the Double Word Program command cannot change a bit set to ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole bank from ’0’ to ’1’. If the Double Word Program command is used to try to set a bit from ‘0’ to ‘1’ Status Register Error bit DQ5 will be set to ‘1’. Quadruple Word Program Command. The Quadruple Word Program command improves the

M59DR032EA, M59DR032EB programming throughput by writing a page of four adjacent Words in parallel. The four Words must differ only for the addresses A0 and A1. The V PP supply voltage is required to be from 11.4V to 12.6V for the Quadruple Word Program com- mand. The command uses the two unlock cycles followed by a write cycle to set up the command. A further four cycles are required to latch the address and data of the four Words and start the Program Erase Controller. The Quadruple Word Program command can be executed in Bypass mode to skip the two unlock cycles. Note that the Quadruple Word Program command cannot change a bit set to ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole bank from ’0’ to ’1’. If the Quadruple Word Program command is used to try to set a bit from ‘0’ to ‘1’ Status Register Error bit DQ5 will be set to ‘1’. Enter Bypass Mode Command. The Bypass mode is used to reduce the overall programming time when large memory arrays need to be pro- grammed. The Enter Bypass Mode command uses the two unlock cycles followed by one write cycle to set up the command. Once in Bypass mode, it is impera- tive that only the following commands be issued: Exit Bypass, Program, Double Word Program or Quadruple Word Program. Exit Bypass Mode Command. The Exit Bypass Mode command uses two write cycles to be set up and confirmed. The unlock cycles are not required. After the Exit Bypass Mode command, the device resets to Read mode. Program in Bypass Mode Command. The Program in Bypass Mode command can be is- sued when the device is in Bypass mode (issue an Enter Bypass Mode command). It uses the same sequence of cycles as the Program command with the exception of the unlock cycles. Double Word Program in Bypass Mode Com- mand. The Double Word Program in Bypass Mode command can be issued when the device is in Bypass mode (issue an Enter Bypass Mode command). It uses the same sequence of cycles as the Double Word Program command with the exception of the unlock cycles. Quadruple Word Program in Bypass Mode Command. The Quadruple Word Program in By- pass Mode command can be issued when the de- vice is in Bypass mode (issue an Enter Bypass Mode command). It uses the same sequence of cycles as the Quadruple Word Program command with the exception of the unlock cycles. Block Lock Command. The Block Lock com- mand is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at Power-Up or Reset. Three Bus Write cycles are required to issue the Block Lock command. ■ The first two bus cycles unlock the Command Interface. ■ The third bus cycle sets up the Block Lock command and latches the block address. The lock status can be monitored for each block using the Auto Select command. Table 10 shows the Lock Status after issuing a Block Lock com- mand. The Block Lock bits are volatile, once set they re- main set until a hardware Reset or Power-Down/ Power-Up. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. Block Unlock Command. The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Three Bus Write cycles are required to issue the Block Unlock command. ■ The first two bus cycles unlock the Command Interface. ■ The third bus cycle sets up the Block UnLock command and latches the block address. The lock status can be monitored for each block using the Auto Select command. Table 10 shows the lock status after issuing a Block Unlock com- mand. Refer to the section, Block Locking, for a detailed explanation. Block Lock-Down Command. A locked or un- locked block can be locked-down by issuing the Block Lock-Down command. A locked-down block cannot be programmed or erased, or have its pro- tection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is dis- abled and the locked blocks can be individually un- locked by the Block Unlock command. Three Bus Write cycles are required to issue the Block Lock-Down command. ■ The first two bus cycles unlock the Command Interface. ■ The third bus cycle sets up the Block Lock- Down command and latches the block address. The lock status can be monitored for each block using the Auto Select command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Ta- ble 10 shows the Lock Status after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation.

M59DR032EA, M59DR032EB Block Erase Command. The Block Erase com- mand can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the device will return to Read Array mode. It is not necessary to pre-pro- gram the block as the Program/Erase Controller does it automatically before erasing. Six Bus Write cycles are required to issue the command. ■ The first two write cycles unlock the Command Interface. ■ The third write cycles sets up the command ■ the fourth and fifth write cycles repeat the unlock sequence ■ the sixth write cycle latches the block address and confirms the command. Additional Block Erase confirm cycles can be is- sued to erase other blocks without further unlock cycles. All blocks must belong to the same bank; if a new block belonging to the other bank is given, the operation is aborted. The additional Block Erase confirm cycles must be given within the DQ3 erase timeout period. Each time a new confirm cycle is issued the timeout pe- riod restarts. The status of the internal timer can be monitored through the level of DQ3, see Status Register section for more details. Once the command is issued the device outputs the Status Register data when any address within the bank is read. After the command has been issued the Read/Re- set command will be accepted during the DQ3 tim- eout period, after that only the Erase Suspend command will be accepted. On successful completion of the Block Erase com- mand, the device returns to Read Array mode. Bank Erase Command. The Bank Erase com- mand can be used to erase a bank. It sets all the bits within the selected bank to ’1’. All previous data in the bank is lost. The Bank Erase command will ignore any protected blocks within the bank. If all blocks in the bank are protected then the Bank Erase operation will abort and the data in the bank will not be changed. It is not necessary to pre-pro- gram the bank as the Program/Erase Controller does it automatically before erasing. As for the Block Erase command six Bus Write cy- cles are required to issue the command. ■ The first two write cycles unlock the Command Interface. ■ The third write cycles sets up the command ■ the fourth and fifth write cycles repeat the unlock sequence ■ the sixth write cycle latches the block address and confirms the command. Once the command is issued the device outputs the Status Register data when any address within the bank is read. For optimum performance, Bank Erase com- mands should be limited to a maximum of 100 Pro- gram/Erase cycles per Block. After 100 Program/ Erase cycles the internal algorithm will still operate properly but some degradation in performance may occur. Dual operations are not supported during Bank Erase operations and the command cannot be suspended. On successful completion of the Bank Erase com- mand, the device returns to Read Array mode. Erase Suspend Command. The Erase Suspend command is used to pause a Block Erase opera- tion. In a Dual Bank memory it can be used to read data within the bank where an Erase operation is in progress. It is also possible to program data in blocks not being erased. One bus write cycle is required to issue the Erase Suspend command. The Program/Erase Control- ler suspends the Erase operation within 20µs of the Erase Suspend command being issued and bits 7, 6 and/ or 2 of the Status Register are set to ‘1’. The device is then automatically set to Read mode. The command can be addressed to any bank. During Erase Suspend the memory will accept the Erase Resume, Program, Read CFI Query, Auto Select, Block Lock, Block Unlock and Block Lock- Down commands. Erase Resume Command. The Erase Resume command can be used to restart the Program/ Erase Controller after an Erase Suspend com- mand has paused it. One Bus Write cycle is re- quired to issue the command. The command must be issued to an address within the bank being erased. The unlock cycles are not required. Protection Register Program Command.The Protection Register Program command is used to Program the Protection Register (One-Time-Pro- grammable (OTP) segment and Protection Regis- ter Lock). The OTP segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Four write cycles are required to issue the Protec- tion Register Program command. ■ The first two bus cycles unlock the Command Interface. ■ The third bus cycle sets up the Protection Register Program command.

the Program/Erase Controller. tent after the programming has started. Table 4. Commands cycles address inputs A12-A20 are don't care. 1+ X F0h Read Memory Array until a new write cycle is initiated. CFI Query 1+ 55h 98h Read CFI and Electronic Signature until a Read/Reset command is issued. Mode 2 X A0h PA PD Read Data Polling or Toggle Bit until Program completes.

3 X 50h PA1 PD1 PA2 PD2 PA3 PD3 PA4 PD4

being erased then Resume Erase.

Table 5. Read Electronic Signature Table 6. Read Block Protection Table 7. Configuration Register

Table 8. Read Protection Register Table 9. Program, Erase Times and Program, Erase Endurance Cycles Note: 1. Excludes the time needed to execute the sequence for program command.

1. Same timing value if VPP = 12V

M59DR032EA, M59DR032EB BLOCK LOCKING The M59DR032E features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has two levels of protection. ■ Lock/Unlock - this first level allows software- only control of block locking. ■ Lock-Down - this second level requires hardware interaction before locking can be changed. The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 10, de- fines all of the possible protection states (WP DQ1, DQ0). Reading a Block’s Lock Status The lock status of every block can be read in the Auto Select mode of the device. Subsequent reads at the address specified in Table 6, will out- put the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indi- cates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when enter- ing Lock-Down. DQ1 indicates the Lock-Down sta- tus and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or af- ter a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase oper- ations attempted on a locked block will reset the device to Read Array mode. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software com- mands. An Unlocked block can be Locked by issu- ing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be un- locked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status can- not be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. Locked- Down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from pro- gram, erase and protection status changes. When WP =1 (VIH) the Lock-Down function is disabled (1,1,1) and Locked-Down blocks can be individu- ally unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains High. When WP is low, blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was High. Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase opera- tion, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After complet- ing any desired lock, read, or program operations, resume the erase operation with the Erase Re- sume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete.

Table 10. Lock Status in the Auto Select command with A1 = VIH and A0 = VIL.

1. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
2. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

current or previous Program or Erase operations. tus and any errors of the operation. last programmed or a '1' after erasing. programming or after the sixth W pulse for erase. gramming or after the sixth W pulse for Erase. 13 for Toggle Bit waveforms. gram or erase operation was successful. The Error Bit is reset by a Read/Reset command. ished, DQ3 returns to ‘1’, (80µs to 120µs). Table 11. Polling and Toggle Bits

Table 12. Status Register Bits Note: 1. Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations.

1. In case of double word program DQ7 refers to the last word input.

7 Data

for Program or Erase success.

6 Toggle Bit

5 Error Bit

4 Reserved

3 Erase Time

P/E.C. Erase operation has started.

2 Toggle Bit

to identify the erased block.

1 Program in progress or Erase

1 Reserved

0 Reserved

Table 13. Absolute Maximum Ratings

1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

ing on the quoted parameters. Table 14. Operating and AC Measurement Conditions Figure 5. Testing Input/Output Waveforms Figure 6. AC Testing Load Circuit Table 15. Capacitance Note: Sampled only, not 100% tested.

Table 16. DC Characteristics Note: 1. Sampled only, not 100% tested.

1. VPP may be connected to 12V power supply for a total of less than 100 hrs.
2. For standard program/erase operation VPP is don’t care.

Figure 7. Random Read AC Waveforms Note: Write Enable (W) = High.

Figure 8. Page Read AC Waveforms

Table 17. Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV .

Figure 9. Write AC Waveforms, Write Enable Controlled Table 18. Write AC Characteristics, Write Enable Controlled

Figure 10. Write AC Waveforms, Chip Enable Controlled Note: Addresses are latched on the falling edge of E, Data is latched on the rising edge of E. Table 19. Write AC Characteristics, Chip Enable Controlled

Figure 11. Reset/Power-Down AC Waveform Table 20. Reset/Power-Down AC Characteristics

Figure 12. Data Polling DQ7 AC Waveforms

Figure 13. Data Toggle DQ6, DQ2 AC Waveforms Note: All other timings are as a normal Read cycle.

Table 21. Data Polling and Toggle Bits AC Characteristics Figure 14. Data Polling Flowchart Figure 15. Data Toggle Flowchart

Figure 16. TFBGA48 7x12mm - 8x6 ball array, 0.75 mm pitch, Package Outline Note: Drawing is not to scale. Table 22. TFBGA48 7x12mm - 8x6 ball array, 0.75 mm pitch, Package Mechanical Data

Figure 17. TFBGA48 7x7mm - 8x6 ball array, 0.75 mm pitch, Package Outline Note: Drawing is not to scale. Table 23. TFBGA48 7x7mm - 8x6 ball array, 0.75 mm pitch, Package Mechanical Data

Table 24. Ordering Information Scheme

Table 25. Daisy Chain Ordering Scheme Sales Office nearest to you.

Table 26. Bank A, Top Boot Block Addresses Table 27. Bank B, Top Boot Block Addresses

Table 28. Bank B, Bottom Boot Block Table 29. Bank A, Bottom Boot Block

outputs (DQ8-DQ15) are set to 0. Read command to return to Read mode. Table 30. Query Structure Overview Table 31. CFI Query Identification String

Table 32. CFI Query System Interface Information

Table 33. Device Geometry Definition

1. x specifies the number of regions within the device containing one or more

separate Erase Block Regions.

1. By definition, symmetrically block devices have only one blocking region.

in size. The value z = 0 is used for 128 byte block size.

M59DR032EA, M59DR032EB

REVISION HISTORY

Table 34. Document Revision History Polling and Toggle Bits AC Characteristics modified. (revision version 02 equals 2.0). through package), respectively). Document promoted from Preliminary Data to full Datasheet status. TFBGA48, 7 x 7mm, 0.75mm pitch package added. 85ns Speed Class characterized. Performance of Bank Erase Command specified.

M59DR032EA, M59DR032EB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada- China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.