M59DR016C STMICROELECTRONICS | Alldatasheet
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Technical content
This is preliminary information on a new product now in development. Details are subject to change without notice.
16 Mbit (1Mb x16, Dual Bank, Page)
Figure 1. Logic Diagram
M59DR016C, M59DR016D Figure 2. TFBGA Connections (Top view through package) Table 1. Signal Names
DESCRIPTION
The M59DR016 is a 16 Mbit non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by- Word basis using a 1.65V to 2.2V V DD supply for the circuitry. For Program and Erase operations the necessary high voltages are generated inter- nally. The device supports asynchronous page mode from all the blocks of the memory array. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against pro- gramming and erase at Power Up. Blocks can be unprotected to make changes in the application and then reprotected. Instructions for Read/Reset, Auto Select, Write Configuration Register, Programming, Block Erase, Bank Erase, Erase Suspend, Erase Re- sume, Block Protect, Block Unprotect, Block Lock- ing, CFI Query, are written to the memory through a Command Interface using standard micropro- cessor write timings. The device is offered in TFBGA48 (0.75 mm pitch) packages and it is supplied with all the bits erased (set to ‘1’).
to indicate the state of the P/E.C operations. shown in Tables 3, 4, 5 and 6. and the Configuration Register status. Table 2. Absolute Maximum Ratings (1)
- Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
Table 3. Bank A, Top Boot Block Addresses Table 4. Bank B, Top Boot Block Addresses Table 5. Bank B, Bottom Boot Block Addresses Table 6. Bank A, Bottom Boot Block Addresses
Write Enable W, whichever occurs last. ry array, while W remains at VIL. Lock instruction description. edge of RP. See Tables 25, 26 and Figure 9. VDD and VDDQ Supply Voltage (1.65V to 2.2V). or E whichever occurs first. G signals do not start a write cycle. Table 7. Bank Size and Sectorization
Table 8. User Bus Operations (1) Table 9. Read Electronic Signature (AS and Read CFI instructions) Table 10. Read Block Protection (AS and Read CFI instructions) Table 11. Read Configuration Register (AS and Read CFI instructions) , Output Enable G or Write Enable W inputs. to VIL (see Block Lock instruction). dress within the bank being modified.
55h at the address 2AAh during the second cycle. blocks of the same memory bank can be erased. gram data in another block, and then resumed. Command sequencing must be followed exactly. command set and some electrical specifications. Table 12. Commands
M59DR016C, M59DR016D Auto Select (AS) Instruction.This instruction uses two Coded Cycles followed by one write cy- cle giving the command 90h to address 555h for command set-up. A subsequent read will output the Manufacturer or the Device Code (Electronic Signature), the Block Protection status or the Con- figuration Register status depending on the levels of A0 and A1 (see Tables 9, 10 and 11). A7-A2 must be at V IL, while other address input are ig- nored. The bank address is don’t care for this in- struction. The Electronic Signature can be read from the memory allowing programming equip- ment or applications to automatically match their interface to the characteristics of M59DR016. The Manufacturer Code is output when the address lines A0 and A1 are at V IL, the Device Code is out- put when A0 is at VIH with A1 at VIL. The codes are output on DQ0-DQ7 with DQ8- DQ15 at 00h. The AS instruction also allows the access to the Block Protection Status. After giving the AS instruction, A0 is set to VIL with A1 at VIH, while A12-A19 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. The AS Instruction finally allows the access to the Configuration Register status if both A0 and A1 are set to V IH. If DQ10 is '0' only the Reset function is active as RP is set to VIL (default at power-up). If DQ10 is '1' both the Reset and the Power Down functions will be achieved by pulling RP to VIL. The other bits of the Configuration Register are re- served and must be ignored. A reset command puts the device in read array mode. Write Configuration Register (CR) Instruc- tion.This instruction uses two Coded Cycles fol- lowed by one write cycle giving the command 60h to address 555h. A further write cycle giving the command 03h writes the contents of address bits A0-A15 to the 16 bits configuration register. Bits written by inputs A0-A9 and A11-A15 are reserved for future use. Address input A10 defines the sta- tus of the Reset/Power Down functions. It must be set to V IL to enable only the Reset function and to VIH to enable also the Power Down function. At Power Up all the Configuration Register bits are reset to '0'. Enter Bypass Mode (EBY) Instruction.This in- struction uses the two Coded cycles followed by one write cycle giving the command 20h to ad- dress 555h for mode set-up. Once in Bypass mode, the device will accept the Exit Bypass (XBY) and Program or Double Word Program in Bypass mode (PGBY, DPGBY) commands. The Bypass mode allows to reduce the overall pro- gramming time when large memory arrays need to be programmed. Exit Bypass Mode (XBY) Instruction.This in- struction uses two write cycles. The first inputs to the memory the command 90h and the second in- puts the Exit Bypass mode confirm (00h). After the XBY instruction, the device resets to Read Memo- ry Array mode. Program in Bypass Mode (PGBY) Instruc- tion.This instruction uses two write cycles. The Program command A0h is written to any Address on the first cycle and the second write cycle latch- es the Address on the falling edge of W or E and the Data to be written on the rising edge and starts the P/E.C. Read operations within the same bank output the Status Register bits after the program- ming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Program (PG) Instruction.This instruction uses four write cycles. The Program command A0h is written to address 555h on the third cycle after two Coded Cycles. A fourth write operation latches the Address and the Data to be written and starts the P/E.C. Read operations within the same bank out- put the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Pro- gramming at an address not in blocks being erased is also possible during erase suspend. Double Word Program (DPG) Instruction.This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel. High voltage (11.4V to 12.6V) on V PP pin is required. This instruction uses five write cy- cles. The double word program command 40h is written to address 555h on the third cycle after two Coded Cycles. A fourth write cycle latches the ad- dress and data to be written to the first location. A fifth write cycle latches the new data to be written to the second location and starts the P/E.C.. Note that the two locations must have the same address except for the address bit A0. The Double Word Program can be executed in Bypass mode (DPG- BY) to skip the two coded cycles at the beginning of each command.
blocks will output a ‘1’ on DQ1. Refer to Table 13 for a list of the protection states. erased is given and latched into the memory. Table 13. Protection States Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status.
- Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by
DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = VIH and A0 = VIL.
- Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed
- A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
for other blocks must be given within this delay. or E, output the status register bits. and stops when erase is completed. is necessary in order to reset the P/E.C.
M59DR016C, M59DR016D Bank Erase (BKE) Instruction.This instruction uses six write cycles and is used to erase all the blocks belonging to the selected bank. The Erase Set-up command 80h is written to address 555h on the third cycle after the two Coded cycles. The Bank Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded cycles at an address within the selected bank. If the second command given is not an erase con- firm or if the Coded cycles are wrong, the instruc- tion aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations within the same bank after the sixth rising edge of W or E output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit DQ7 re- turns '0', then '1' on completion. The Toggle bit DQ6 toggles during erase operation and stops when erase is completed. After completion the Status Register bit DQ5 returns '1' if there has been an Erase Failure. Erase Suspend (ES) Instruction.In a dual bank memory the Erase Suspend instruction is used to read data within the bank where erase is in progress. It is also possible to program data in blocks not being erased. The Erase Suspend instruction consists of writing the command B0h without any specific address. No Coded Cycles are required. Erase suspend is accepted only during the Block Erase instruction execution. The Toggle bit DQ6 stops toggling when the P/E.C. is suspended within 15µs after the Erase Suspend (ES) command has been writ- ten. The device will then automatically be set to Read Memory Array mode. When erase is sus- pended, a Read from blocks being erased will out- put DQ2 toggling and DQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume ER and the Program PG instruc- tions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in DQ6 toggling when the data is being programmed. Erase Resume (ER) Instruction.If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at an address within the bank be- ing erased and without any Coded Cycle.
Table 14. Instructions (1,2) Read Memory Array until a new write cycle is initiated. Read CFI data until a new write cycle is initiated.
M59DR016C, M59DR016D Note: 1. Commands not interpreted in this table will default to read array mode. 2. For Coded cycles address inputs A11-A19 are don't care. 3. X = Don't Care. 4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com- mand cycles. 5. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. 6. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0. 7. High voltage on V PP (11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction. BL Block Lock 4 Addr. 555h 2AAh 555h Block Address Data AAh 55h 60h 2Fh BE Block Erase 6+ Addr. 555h 2AAh 555h 555h 2AAh Block Address Data AAh 55h 80h AAh 55h 30h BKE Bank Erase 6 Addr. 555h 2AAh 555h 555h 2AAh Bank Address Data AAh 55h 80h AAh 55h 10h ES Erase Suspend 1 Addr. (3) X Read until Toggle stops, then read all the data needed from any Blocks not being erased then Resume Erase.Data B0h ER Erase Resume 1 Addr. Bank Address Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time Data 30h
Table 15. Status Register Bits (1) Note: 1. Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
- In case of double word program DQ7 refers to the last word input.
7 Data
for Program or Erase Success.
6 Toggle Bit
5 Error Bit
4 Reserved
3 Erase Time
P/E.C. Erase operation has started.
2 Toggle Bit
to identify the erased block.
1 Program on-going or Erase
1 Reserved
0 Reserved
tomatically sets bits DQ2, DQ5, DQ6 and DQ7. modified will output array data. Table 16. Polling and Toggle Bits program operation and to ‘0’ in Erase operation. Error Bit (DQ5).This bit is set to '1' by the P/E.C.
Table 17. Program, Erase Times and Program, Erase Endurance Cycles erase should perform significantly better.
- Excludes the time needed to execute the sequence for program instruction.
- Same timing value if VPP = 12V.
DD program and erase currents.
Table 18. Query Structure Overview detailled in Tables 19, 20 and 21. Query data are always presented on the lowest order data outputs. Table 19. CFI Query Identification String Note:Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. that can be read from the Flash memory device. software to configure itself when necessary.
Table 20. CFI Query System Interface Information
Table 21. Device Geometry Definition
- x specifies the number of regions within the device containing one or more con-
- By definition, symmetrically block devices have only one blocking region.
size. The value z = 0 is used for 128 byte block size.
Table 24. DC Characteristics Note: 1. Sampled only, not 100% tested.
- VPP may be connected to 12V power supply for a total of less than 100 hrs.
- For standard program/erase operation VPP is don’t care.
Table 25. Read AC Characteristics Note: 1. Sampled only, not 100% tested.
- G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV .
Figure 5. Random Read AC Waveforms Note: Write Enable (W) = High.
Figure 6. Page Read AC Waveforms
Table 26. Write AC Characteristics, Write Enable Controlled
Table 27. Write AC Characteristics, Chip Enable Controlled
Figure 7. Write AC Waveforms, W Controlled Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
Figure 8. Write AC Waveforms, E Controlled Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.
Table 28. Data Polling and Toggle Bits AC Characteristics (1) Note: 1. All other timings are defined in Read AC Characteristics table.
Figure 9. Read and Write AC Characteristics, RP Related
Figure 10. Data Polling DQ7 AC Waveforms
Figure 11. Data Toggle DQ6, DQ2 AC Waveforms Note: All other timings are as a normal Read cycle.
Table 29. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. Table 30. Daisy Chain Ordering Scheme vice, please contact the STMicroelectronics Sales Office nearest to you.
Table 31. Revision History
Table 32. TFBGA48 - 8 x 6 balls array, 0.75 mm pitch, Package Mechanical Data Figure 14. TFBGA48 - 8 x 6 balls array, 0.75 mm pitch, Package Outline
M59DR016C, M59DR016D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.