M59BW102 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 24
Technical content
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M59BW102
1 Mbit (64Kb x16, Burst) Low Voltage Flash Memory
■ 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ■ SEQUENTIAL CYCLE TIME: 25ns ■ RANDOM ACCESS TIME ■ PROGRAMMING TIME: 10µs typical ■ INTERLEAVED ACCESS TIME: 16ns ■ CONTINUOUS MEMORY INTERLEAVING – Unlimited Linear Access Data Output ■ PROGRAM/ERASE CONTROLLER (P/E.C.) – Program Word-by-Word – Status Register bits ■ LOW POWER CONSUMPTION – Stand-by and Automatic Stand-by ■ 100,000 PROGRAM/ERASE CYCLES ■ 20 YEARS DATA RETENTION – Defectivity below 1ppm/year ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: C1h
DESCRIPTION
The M59BW102 is a non-volatile memory that may be erased electrically at the chip level and pro- grammed in-system on a Word-by-Word basis us- ing only a single 3V V CC supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be pro- grammed in standard programmers. The device can be programmed and erased over 100,000 cycles. Instructions for Read/Reset, Auto Select for read- ing the Electronic Signature, Programming and Chip Erase are written to the device in cycles of commands to a Command Interface using stan- dard microprocessor write timings. The M59BW102 features an interleaved access mo- dality which allows extremely fast access time. The device is offered in TSOP40 (10 x 14mm) package. Figure 1. Logic Diagram
Figure 2. TSOP Connections quence will reset the device to Read Array mode. itor the progress of the operation. mand confirmation on the sixth cycle. Table 1. Signal Names an internal Program/Erase Controller (P/E.C.). Standby. See Tables 3 and 4.
is deselected or the outputs are disabled. ry array, while W remains at a low level. Table 2. Absolute Maximum Ratings (1)
- Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
Table 3. User Bus Operations (1)) Table 4. Read Electronic Signature (following AS instruction or with A9 = VID)
block diagram is shown in Figure 4. rising edge of W or E whichever occurs first. (ALE) or the Write Enable W inputs. STMicroelectronics is 20h, the device code is C1h. operations (Read, Program and Erase). two memory banks (named Even and Odd bank). array under selection and the odd bank is masked. der selection and even bank is masked. is asserted low again and ALE is low. Table 5. Commands Table 6. Polling and Toggle Bits
Figure 3. Non Linear and Linear Access Cycle Timing Diagram
Figure 4. Block Diagram DQ2, or Error on DQ5 and Erase Timer DQ3 bits. plement of the bit being programmed on DQ7.
gram operation and when erase is complete. Error Bit (DQ5).This bit is set to '1' by the P/E.C. finished, after 50µs to 120µs, DQ3 returns to '1'. write or on the fourth and fifth cycles. Table 7. Instructions Note: 1. Commands not interpreted in this table will default to read array mode.
- A wait of 10µs is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new
- The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-
- Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Device
- For Coded cycles address inputs A11-A16 are don't care.
- Read Data Polling, Toggle bits until Erase completes.
Read Memory Array until a new write cycle is initiated. Bit until Program completes.
Table 8. Status Register Bits Note: Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
7 Data
6 Toggle Bit
5 Error Bit
4 Reserved
3 Erase
'1' Erase Timeout Period Expired P/E.C. Erase operation has started.
2 Toggle Bit
1 Reserved
0 Reserved
in Program/Erase operation unless a fail occurred. output when A0 is High with A1 Low.
Table 11. DC Characteristics Note: 1. Sampled only, not 100% tested. Table 12. Sequential Read Mode AC Characteristics Note: 1. This timing refers to a Load Capacitance (CL) of 30pF. If CL is higher, add 1 ns for each extra 10pF.
Table 13. Random Read Mode AC Characteristics Note: 1. This timing refers to a Load Capacitance (CL) of 30pF. If CL is higher, add 1ns for each extra 10pF.
Table 14. Write AC Characteristics, Write Enable Controlled Figure 9. Write AC Waveforms, W Controlled Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W; ALE must be High.
Table 15. Write AC Characteristics, Chip Enable Controlled Figure 10. Write AC Waveforms, E Controlled Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E; ALE must be High.
Figure 11. Write AC Waveforms, W Controlled and Address Latch Enable Pulsed Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W. Table 16. Write AC Characteristics, Write Enable Controlled and Address Latch Enable Pulsed Note: 1. These parameters are applicable only if the following cycle is for the same device.
Figure 12. Suspend and Resume Linear Cycle Waveforms with Bus Idle Table 17. Suspend and Resume Last Linear Cycle Characteristics
Figure 13. Suspend and Resume Linear Cycle Waveforms without Bus Idle Table 18. Suspend and Resume Next Linear Cycle Characteristics
Table 19. Data Polling and Toggle Bit AC Characteristics (1) Note: 1. All other timings are defined in Read AC Characteristics table.
Figure 14. Data Polling DQ7 AC Waveform
Figure 17. Data Toggle DQ6, DQ2 AC Waveforms Note: All other timing are as a normal Read cycle; AILE must be high.
Table 21. Ordering Information Scheme vice, please contact the ST Sales Office nearest to you.
Figure 18. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline Table 22. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Mechanical Data
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com