M5913

M5913 STMICROELECTRONICS | Alldatasheet

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COMBINED SINGLE CHIP PCM CODEC AND FILTER SYNCHRONOUS CLOCKS ONLY AT&T D3/D4 AND CCITT COMPATIBLE TWO TIMING MODES: FIXED DATA RATE MODE 1.536MHz, 1.544MHz, 2.048MHz VARIABLE DATA MODE: 64KHz - 4.096MHz PIN SELECTABLE µ-LAW OR A-LAW OP- ERATION NO EXTERNAL COMPONENTS FOR SAM- PLE-AND-HOLD AND AUTO ZERO FUNC- TIONS LOW POWER DISSIPATION: 0.5mW POWER DOWN 70mW OPERATING EXCELLENT POWER SUPPLY REJECTION

DESCRIPTION

The M5913 is fully integrated PCM (pulse code modulation) codecs and transmit/receive filter us- ing CMOS silicon gate technology. The primary applications for the M5913 are tele- phone systems : - Switching - M5913-Digital PBX’s and Central Office Switching Systems - Concentration - M5913 Subscriber Carrier and Concentrators. The wide dynamic range (78dB) and the minimal conversion time make it ideal products for other applications such as: - Voice Store and Forward - Secure Communications Systems - Digital Echo Cancellers - Satellite Earth Stations. This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. December 1993 BLOCK DIAGRAM DIP 20 ORDERING NUMBER: M5913B1

Symbol Parameter Value Unit VCC With Respect GRDD, GRDA = 0V – 0.6 to 7 V VBB With Respect GRDD, GRDA = 0V - 0.6 to – 7 V GRDD, GRDA In Such Case : 0 ≤ VCC ≤ + 7V, – 7V≤ VBB ≤ 0V ± 0.3 V VI/O Analog Inputs, Analog Outputs and Digital Inputs VBB – 0.3≤ VIN/VOUT ≤ VCC + 0.3 V VO DIG Digital Outputs GRDD – 0.3 ≤ VOUT ≤ VCC + 0.3 V Ptot Total Power Dissipation 1 W Tstg Storage Temperature Range -65 to 150 °C PIN NAMES Symbol Parameter Symbol Parameter VBB Power (-5V) GS X Gain Control PWRO+, PWRO- Power Amplifier Outputs VF XI-, VFXI+ Analog Inputs GS R Gain Setting Input for receive Channel GRDA Analog Ground PDN Power Pown Select NC No Connected CLKSEL Master Clock Select SIG X Transmit Digital Signaling Input LOOP Analog Loop Back ASEL µ or A-law Select SIGR Signaling Bit Output TS X Digital Output - Timeslot Strobe DCLK R Receive Data Rate Clock DCLK X Transmit Data Rate Clock D R Receive Channel Input D X Transmit (Digital) Output FS R Receive Frame Synchronization Clock FS X Transmit Frame Synchronization Clock GRDD Digital Ground CLK X Transmit Master Clock VCC Power (+5V) CLK R Receive Master Clock PIN CONNECTION (Top view) M5913

VBB Most Negative Supply. Input voltage is -5 volts±5%. PWRO+ Non-inverting Output of Power Amplifier. Can drive transformer hybrids or high impedance loads directly in either a differential or single ended configuration. PWRO - Inverting Output of Power Amplifier. Functionally identical and complementary to PWRO+. GS R Input to the gain Setting Network on the Output Power Amplifier, Transmission level can be adjusted over a 12dB range depending on the voltage at GSR . PDN Power Down Select. When PDN is TTL high, the device is active.When low, the device is powered down. CLKSEL input which must be pinstrapped to reflect the master clock frequency at CLKX , CLKR . CLKSEL = VBB 2.048MHz CLKSEL = GRDD 1.544MHz CLKSEL = VCC 1.536MHz LOOP Analog Loopback. When this pin is TTL high, the receive output (PWRO+) is internally connected to VFX I+, GSR is internally connected to PWRO-, and VFX I- is internally connected to GSX . A 0dBm0 digital signal input at DR is returned as a +3dBm0 digital signal output at DX. SIGR Signalling Bit Output, Receive Channel. In fixed data rate mode. SIGR outputs the logical state of the eighth bit of the PCM word in the most recent signaling frame. DCLK R Selects the fixed or variable data rate mode. When DCLKR is connected to VBB , the fixed data rate mode is selected. When DCLK R is not connected to VBB , the device operates in the variable data rate mode. In this mode DCLK R becomes the receive data clock wich operates at TTL levels from 64kB to 4.096MB data rates D R Receive PCM Input. PCM data is clocked in on this lead on eight consecutive negative transitions of the receive data clock: CLKR in the fixed data rate mode and DCLKR in variable data rate mode. FS R 8kHz frame synchronization clock input/timeslot enable, receive channel. A multifunction input which in fixed data rate mode distinguishes between signaling and non-signaling frames by means of a double or single wide pulse respectively. In variable data rate mode this signal must remain high for the entire length of the timeslot. The receive channel enters the standby state whenever FSR is TTL low for 30 miliseconds GRDD Digital Ground for all Internal Logic Circuits. Not internally tied to GRDA. CLK R Receive master and data clock for the fixed data rate mode; receive master clock only in variable data rate mode. CLK X Transmit master and data clock for the fixed data rate mode; transmit master clock only in variable data rate mode. FS X 8kHz frame synchronization clock input/timeslot enable, transmit channel. Operates independently but in an analogous manner to FSR. The transmit channel enters the standby state whenever FSX is TTL low for 30 milliseconds. D X Transmit PCM Output. PCM data is clocked out on this lead on eight consecutive positive transitions of the transmit data clock : CLK in fixed data rate mode and DCLKX in variable data rate mode. TS X/DCLK X Transmit channel timeslot strobe (output) or data clock (input) for the transmit channel. In fixed data rate mode, this pin becomes the transmit data clock which operates at TTL levels from 64kB to 4.096MB data rates. SIGX/ASEL A dual purpose selectsµ-law and pin. When connected to VBB . A law operation is selected. When it is not connected to VBB pin is a TTL level input for signaling operation. This input is transmitted as the eighth bit of the PCM word during signaling frames on the DX lead. NC Not Connected. GRDA Analog ground return for all internal voice circuits. Not internally connected to GRDD. VF XI+ Non inverting analog input to uncommitted transmit operational amplifier. VF XI- Inverting analog input to uncommitted transmit operational amplifier. GS X Output terminal of on-chip uncommitted op amp. Internally, this is the voice signal input to the transmit filter. VCC Most positive supply ; input voltage is + 5 volts±5% M5913

The M5913 provides the analog-to-digital and the digital-to-analog conversion and the transmit and receive filtering necessary to interface a full du- plex (4 wires) voice telephone circuit with the PCM highway of a time division multiplexed (TDM) system. It is intended to be used at the analog termination of a PCM line. The following major functions are provided : Bandpass filtering of the analog signals prior to encoding and after decoding Encoding and decoding of voice and call pro- gress information Encoding and decoding of the signaling and supervision information GENERAL OPERATION System Reliability Features The combo-chip can be powered up by pulsing FS X and/or FSR while a TTL high voltage is ap- plied to PDN, provided that all clocks and sup- plies are connected. The M5913 has internal re- sets on power up (or when V BB or VCC are re-applied) in order to ensure validity of the digital outputs and thereby maintain integrity of the PCM highway. On the transmit channel, digital outputs DX and TS X are held in a high impedance state for ap- proximately four frames (500µs) after power up or application of VBB or VCC . After this delay, DX and TSX will be functional and will occur in the proper timeslot. The analog circuits on the transmit side require approximately 40 milliseconds to reach their equilibrium value due to the autozero circuit setting time. Thus, valid digital information, such as for on/off hook detection, is available almost immediately, while analog information is available after some delay. On the receive channel, the digital output SIG R is also held low for a maximum of four frames after power up or application of V BB or VCC , SIGR will remain low thereafter until it is updated by a sig- naling frame. To further enhance system reliability, TSX and DX will be placed in a high impedance state approxi- mately 20µs after an interruption of CLKX. Simi- larly SIGR will be held low approximately 20µs af- ter an interruption of CLKR. These interruptions could possibly occur with some kind of fault con- dition. Power Down And Standby Modes To minimize power consumption, two power down modes are provided in which most M5913 func- tions are disabled. Only the power down, clock, and frame sync buffers, which are required to power up the device, are enabled in these modes. As shown in table 1, the digital outputs on the ap- propriate channels are placed in a high imped- ance state until the device returns to the active mode. The Power Down mode utilizes an external con- trol signal to the PDN pin. In this mode, power consumption is reduced to an average of 0.5mW. The device is active when the signal is high and inactive when it is low. In the absence of any sig- nal, the PDN pin floats to TTL high allowing the device to remain active continuously. The Standby mode leaves the user an option of powering either channel down separately or pow- ering the entire down by selectively removing FS X and/or FSR . With both channels in the standby state, power consumption is reduced to an aver- age of 1mW. If transmit only operation is desired, FS X should be applied to the device while FSR is held low. Similarly, if receive only operation is de- sired, FSR should be applied while FSX is held low. Fixed Data Rate Mode Fixed data rate timing, is selected by connecting DCLK R to VBB . It employs master clock CLKX, and CLK R , frame synchronization clocks FSX and FSR , and output TSX. CLK X, and CLKR, serve both as the master clock to operate the codec and filter sections and bit clocks to clock the data in and out from the PCM highway. FSX and FSR are 8kHz inputs which set the sampling frequency and distinguish between signaling and non-signaling frames by thir pulse width. A frame synchronization pulse which is one master clock wide designates a non-signaling frame, while a double wide sync pulse enables Device Status Power Down Methods Digital Outputs Status Power Down Mode PDN = TTL low TS X and DX are placed in a high impedance state and SIGR is placed in a TTL low state within 10µs. Stand-by Mode FS X and FSR are TTL low TS X and DX are placed in a high impedance state and SIGR is placed in a TTL low state 30ms after FSX and FS R are removed. Only transmit is on stand-by FSX is TTL low TS X and D X are placed in a high impedance state within 30ms. Only receive is on stand-by FSR is TTL low SIG R is placed in a TTL low state within 30ms. Table 1:Power Down Methods M5913

the signaling function. TSX is a timeslot strobe/buffer enable output which gates the PCM word onto the PCM highway when an external buffer is used to drive the line. Data is transmitted on the highway at D X on the first eight positive transitions of CLKX following the rising edge of FSX. Similarly, on the receive side, data is received on the first eight falling edges of CLK R . The frequency of CLKX and CLKR is selected by the CLKSEL pin to be either 1.536, 1.544 or 2.048MHz. No other frequency of opera- tion is allowed in the fixed data rate mode. Variable Data Rate Mode Variable data rate timing is selected by connect- ing DCLK R to the bit clock for the receive PCM highway rather than to VBB . It employes master clocks CLKX and CLK R , bit clocks DCLKR and DCLK X and frame synchronization clocks FSR and FSX. Variable data rate timing allows for a flexible data frequency. It provides the ability to vary the fre- quency of the bit clocks, from 64kHz to 4096MHz. Master clocks inputs are still restricted to 1.536, 1.544, or 2.048MHz. In this mode, DCLK R and DCLK X become the data clocks for the receive and transmit PCM highways. While FSX is high, PCM data from DX is transmitted onto the highway on the next eight consecutive positive transitions of DCLKX. Simi- larly, while FSR is high, each PCM bit from the highway is received by DR on the next eight con- secutive negative transitions of DCLKR . On the transmit side, the PCM word will be re- peated in all remaining timeslots in the 125µs frame as long as DCLKX is pulsed and FSX is held high. This feature allows the PCM word to be transmitted to the PCM highway more than once per frame, if desired, and is only available in the variable data rate mode. Conversely, signaling is only allowed in the fixed data rate mode since the variable mode provides no means with which to specify a signaling frame. Precision Voltage References No external components are required with the combochip to provide the voltage reference func- tion. Voltage references are generated on-chip and are calibrated during the manufacturing proc- ess. The technique use the bandgap principle to derive a temperature and bias stable reference voltage. These references determine the gain and dynamic range characteristics of the device. Separate references are supplied to the transmit and receive sections. Transmit and receive sec- tion are trimmed independently in the filter stages to a final precision value. With this method the combochip can achieve manufacturing tolerances of typically± 0.04dB in absolute gain for each half channel, providing the user a significant margin for error in other board components. Conversion Laws The M5913 is designed to operate in bothµ-law and A-law systems. The user can select either conversion law according to the voltage present on the SIG X/ASEL pin . In each case the coder and decoder process a companded 8-bit PCM word following CCITT recommandation G.711 for µ-law and A-law conversion. If A-law operation is desired, SIG X should be tied to VBB . Thus, signal- ing is not allowed during A-law operation. Ifµ = 255-law operation is selected, then SIGX is a TTL level input which modifies the LSB on the PCM output in signaling frames TRANSMIT OPERATION Transmit Filter The input section provides gain adjustment in the passband by means of an on-chip uncommitted operational amplifier. This operational amplifier has a common mode range of 2.17V, a maximum DC offset of 25mV, a minimum voltage gain of 5000, and a unity gain bandwidth of typically 1MHz. Gain of up to 20dB can be set without de- grading the performance of the filter. The load im- pedanceto ground (GRDA) at the amplifier output (GS X) must be greater than 10kΩ in parallel high less than 50pF. The input signal on lead VFXI+ can be either AC or DC coupled. The input op amp can also be used in the inverting mode or differential amplifier mode (see figure 3). A low pass anti-aliasing section is included on- chip. This section typically provides 35dB attenu- ation at the sampling frequency. No external com- ponents are required to provide the necessary anti-aliasing function for the switched capacitor section of the transmit filter. The passband section provides flatness and stop- band attenuation which fulfills the AT&T D3/D4 channel bank transmission specification and CCITT recommendation G.712. The M5913 specifications meet or exceed digital class 5 central office switching systems require- ments. The transmit filter transfer characteristics and specifications will be within the limits shown the relative table. A high pass section configuration was chosen to reject low frequency noise from 50 and 60Hz power lines, 17Hz European electric railroads, ringing frequencies and their harmonics, and other low frequency noise. Even though there is high rejection at these fre- quencies, the sharpness of the band edge gives low attenuation at 200Hz. This feature allows the use of low-cost transformer hybrids without exter- nal components. M5913

OUTPUT GAIN SET: DESIGN CONSIDERA- TIONS (refer to figure 4) PWRO+ and PWRO– are low impedance comple- mentary outputs. The voltages at the nodes are: VO at PWRO+ VO at PWRO VO =V O +V O – (total differential response) R1 and R2 are a gain setting resistor network with the center tap connected to the GSR input. A value greater than 10KΩ and less than 100KΩ for R1 + R2 is recommended because: a) The parallel combination of R1 + R2 and RL sets the total loading. b) The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant which has to be minimized to avoid inaccuracies. If VA represents the output voltage without any gain setting network connected, you can have: V O =A VA where A =1 +( R1 /R2) 4 +( R1 /R2) For design purposes, a useful form is R1/R2 as a function of A. R1 / R2 =4A –1 1 –A (allowable values for A are those which make R1/R2 positive) Examples are: If A = 1 (maximum output), then R1/R2 =∞ or V(GSR )=V O ; i.e., GSR is tied to PWRO+ If A = 1/2. then R1/R2 = 2 If A = 1/4 (minimum output) then R1/R2 = 0 or V(GSR )=V O+ ; i.e., GSR is tied to PWRO+ DC CHARACTERISTICS (Tamb = 0 to 70oC, VCC = +5V± 5%, VBB =–5 V ± 5%, GRDA = 0V,unless oth- erwise specified) Typical values are for Tamb =2 5oC and nominal power supply values. Symbol Parameter Test Conditions Min. Typ. Max. Unit DIGITAL INTERFACE IIL Low Level Input Current GRDD ≤ VIN ≤ VIL (note 1) 10 µA IIH High Level Input Current V IH ≤ VIN ≤ VCC 10 µA VIL Input Low Voltage, Except CLKSEL 0.8 V VIH Input High Voltage, Except CLKSEL 2.0 V VOL Output Low Voltage I OL = 3.2mA at DX,T SX and SIGR 0.4 V VOH Output High Voltage I OH = 9.6mA at DX IOH = 1.2mA at SIGR 2.4 V VILO Input Low Voltage, CLKSEL (note 2) V BB VBB + 0.5 V VIIO Input Intermediate Voltage, CLKSEL GRDD -0.5 0.5 V VIHO Input High Voltage, CLKSEL V CC - 0.5 VCC V C OX Digital Output Capacitance (note 3) 5 pF C IN Digital Input Capacitance 5 10 pF Notes: 1. VIN is the voltage on any digital pin. 2. SIGX and DCLK R are TTL level inputs between GRDD and VCC ; they are also pinstraps for mode selection when tied to VBB . Under these conditions VILO is the input low voltage requirement. 3. Timing parameters are guaranteed based on a 100pF load capacitanc e. Up to eight digital outputs may be connected to a common PCM highway without buffering, assuming a board capacitance of 60pF. M5913

Symbol Parameter Test Conditions Min. Typ. Max Unit POWER DISSIPATION All measurements made at fDCLK = 2.048MHz, outputs unloaded ICC1 VCC Operating Current 6 10 mA IBB1 VBB Operating Current 6 9 mA ICC0 VCC Power Down Current PDN ≤ VIL ; after 10µs 40 300 µA IBB0 VBB Power Down Current PDN ≤ VIL ; after 10µs 40 300 µA ICCS VCC Standby Current FS X,F SR ≤ VIL ; after 30ms 300 600 µA IBBS VBB Standby Current FS X,F SR ≤ VIL ; after 30ms 40 300 µA PD1 Operating Power Dissipation 60 100 mW PD0 Power Down Dissipation PDN ≤ VIL ; after 10µs 0.4 3 mW PST Standby Power Dissipation FSX, FS R ≤ VIL; after 30ms 1.7 5 mW ANALOG INTERFACE, RECEIVE FILTER DRIVER AMPLIFIER STAGE IBX1 Input Leakage Current, VFXI+, VFXI- -2.17V ≤ VIN ≤ 2.17V 100 nA R IXI Input Resistance, VFXI+, VFX I- 10 M Ω VOSXI Input Offset Voltage, VFX I+, VFX I- 25 mV CMRR Common Mode Rejection, VF X I+, VFXI- -2.17V ≤ VIN ≤ 2.17V 55 dB AVOL DC Open Loop Voltage Gain, GSX R L = 10K 5000 20.000 fC Open Loop Unity Gain Bandwidth, GSX 1M H z VOXI Output Voltage Swing GSX R L ≥ 10kΩ – 2.17 2.17 V C LXI Load Capacitance, GSX 50 pF R LXI Minimum Load Resistance, GSX 10 k Ω ANALOG INTERFACE, RECEIVE FILTER DRIVER AMPLIFIER STAGE R ORA Output Resistance, PWRO+, PWRO- 1 Ω VOSRA Single-ended Output DC Offset, PWRO+, PWRO- Relative to GRDA -150 75 150 mV C LRA Load Capacitance, PWRO+, PWRO- 100 pF DC CHARACTERISTICS (continued) AC CHARACTERISTICS - TRANSMISSION PARAMETERS Unless otherwie noted, the analog input is a 0dBm0, 1020Hz sine wave1. Input amplifier is set for unity gain, noninverting. The digital inputs is a PCM bit stream generated by passing a 0dBm0, 1020Hz sine wave through an ideal encoder. Receive output is measured single ended, maximum gain configuration2. All output levels are (sin X)/X corrected. Symbol Parameter Test Conditions Min. Typ. Max. Unit GAIN AND DYNAMIC RANGE EmW Encoder Milliwatt Response (transmit gain tolerance) Tamb =2 5°C, VBB = – 5V, VCC =+5 V EmW TS EmW Variation with Temperature and Supplies ± 5% Supplies, 0 to 70°C Relative to Nominal Conditions -0.12 +0.12 dB DmW Digital Milliwatt Response (receive gain tolerance) T amb =2 5°C;V BB = – 5V, VCC =+5 V DmW TS DmW Variation with Temperature and Supplies 0TLP 1X Zero Transmission Level Point Transmit Channel (0dBm0)µ-law Referenced to 600Ω Referenced to 900Ω + 2.76 + 1.00 dBm dBm 0TLP 2X Zero Transmission Level Point Transmit Channel (0dBm0) A-law Referenced to 600Ω Referenced to 900Ω + 2.79 + 1.03 dBm dBm 0TLP 1R Zero Receive Level Point Receive Channel (0dBm0)µ-law Referenced to 600Ω Referenced to 900Ω + 5.76 + 4.00 dBm dBm 0TLP 2R Zero Transmission Level Point Transmit Channel (0dBm0)) A-law Referenced to 600Ω Referenced to 900Ω + 5.79 + 4.03 dBm dBm M5913

Symbol Parameter Test Conditions Min. Typ. Max. Unit GAIN TRACKING Reference Level = – 10dBm0 GT1 X Transmit Gain Tracking Error Sinusoidal Input;µ-law + 3 to – 40dBm0 – 40 to – 50dBm0 – 50 to – 55dBm0 ± 0.2 ± 0.4 ± 1.0 dB dB dB GT2 X Transmit Gain Tracking Error Sinusoidal Input; A-law + 3 to – 40dBm0 – 40 to – 50dBm0 – 50 to – 55dBm0 ± 0.2 ± 0.4 ± 1.0 dB dB dB GT1 R Receive Gain Tracking Error Sinusoidal Input;µ-law + 3 to – 40dBm0 – 40 to – 50dBm0 – 50 to – 55dBm0 ± 0.2 ± 0.4 ± 1.0 dB dB dB GT2 R Receive Gain Tracking Error Sinusoidal Input; A-law + 3 to – 40dBm0 – 40 to – 50dBm0 – 50 to – 55dBm0 ± 0.2 ± 0.4 ± 1.0 dB dB dB NOISE N XC1 Transmit Noise, C-message Weighted VFXI+ = GRDA, VFXI– = GSX 0 13 dBrnc0 N XC2 Transmit Noise, C-message Weighted with Eighth Bit Signaling VF XI+ = GRDA, VFX I– = GSX 6 th Frame Signaling 13 18 dBrnc0 N XP Transmit Noise, Psophometrically Weighted VF XI+ = GRDA, VFX I– = GSX (note 3) – 80 dBrnc0 N RC1 Receive Noise, C-message Weighted: Quiet Code D R = 11111111 Measure at PWRO+ 1 9 dBrnc0 N RC2 Receive Noise, C-message Weighted: Sign Bit Toggle Input to DR is 0 code with Sign Bit Toggle at 1KHz Rate 1 10 dBm0p N RP Receive Noise, Psophometrically Weighted D R = Lowest Positive Decode Level -90 – 81 dB0p N SF Single Frequency NOISE End to End Measurement CCITT G.712.4.2 – 50 dBm0 PSRR 1 VCC Power Supply Rejection, Transmit Channel Idle Channel ; 200mV P-P Signal on Supply ; 0 to 50kHz, Measure at D X –4 0 d B PSRR 2 VBB Power Supply Rejection, Transmit Channel Idle Channel ; 200mV P-P Signal on Supply ; 0 to 50kHz, Measure at D X –4 0 d B PSRR 3 VCC Power Supply Rejection, Receive Channel Idle Channel ; 200mV P-P Signal on Supply ; Measure Narrow Band at PWRO+ Single Ended, 0 to 50kHz –4 0 d B PSRR

4 VBB Power Supply, Rejection Receive

Idle Channel ; 200mV P-P Signal on Supply ; Measure Narrow Band at PWRO+ Single Ended, 0 to 50kHz –4 0 d B CT TR Crosstalk, Transmit to Receive, Single Ended Outputs VF XI+ = 0dBm0, 1.02kHz, D R = Lowest Positive Decode Level, Measure at PWRO+ –8 0 d B CT RT Crosstalk, Receive to Transmit, Single Ended Outputs D B = 0dBm0, 1.02kHz, VF XI+ = GRDA, Measure at D X –8 0 d B Notes: 1. 0dBm0 is defined as the zero reference point of the channel under test (0TLP). This correspon ds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrmst (µLaw) dual 1.068 Vrmst or a output 1.516 Vrmst (A-Law) 2. Unity gain input amplifier : GSX is connected to VFXI, Signal input VFXI+; Maximum gain output amplifier: GSR is connect ed to PWRO, output to PWRO+. 3. Noise free: DX PCM Code stable at 01010101. AC CHARACTERISTICS (continued) M5913

A.C. CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit DISTORTION SD1 X Transmit Signal to Distortion,µ-law Sinusoidal Input; CCITT G.712-method 2 0 ≤ VF X I+≤ – 30dBm0 – 40dBm0 – 45dBm0 dB dB dB SD2 X Transmit Signal to Distortion, A-law Sinusoidal Input, CCITT G.712-method 2 0 ≤ VF X I+≤ – 30dBm0 – 40dBm0 – 45dBm0 dB dB dB SD1 R Transmit Signal to Distortion, µ-law Sinusoidal Input , CCITT G.712-method 2 0 ≤ VF X I+≤ – 30dBm0 – 40dBm0 – 45dBm0 dB dB dB SD2 R Receive Signal to Distortion, A-law Sinusoidal Input; CCITT G.712-method 2 0 ≤ VF X I+≤ – 30dBm0 – 40dBm0 – 45dBm0 dB dB dB DP X1 Transmit Single Frequency Distortion Products AT & T Adivisory # 64 (3.8) 0dBm0 Input Signal –4 6 d B DP R1 Receive Single Frequency Distortion Products AT & T Adivisory # 64 (3.8) 0dBm0 Input Signal –4 6 d B IMD 1 Intermodulation Distortion, End to End Measurement CCITT G.712 (7.1) – 35 dB IMD 2 Intermodulation Distortion, End to End Measurement CCITT G.712 (7.2) – 49 dB SOS Spurious Out of Band Signals, End to End Measurement CCITT G.712 (6.1) – 30 dBm0 SIS Spurious in Band Signals, End to End Measurement CCITT G.712 (9) – 40 dBm0 D AX Transmit Absolute Delay Fixed Data Rate CLK X = 2.048MHz, 0dBm0, 1.02kHz Signal at VF XI+ Measure at DX 300 µs D DX Transmit Differential Envelope Delay Relative to DAX f = 500 – 600Hz f = 600 – 1000Hz f = 1000 – 2600Hz f = 2600 – 2800Hz 170 µs µs µs µs D AR Receive Absolute Delay Fixed data rate, CLK R = 2.048MHz; Digital input is DMW codes. Measure at PWRO+ 190 µs D DR Receive Differential Envelope Delay Relative to DAR f = 500 – 600Hz f = 600 – 1000Hz f = 1000 – 2600Hz f = 2600 – 2800Hz 110 µs µs µs µs M5913

TRANSMIT CHANNEL TRANSFER CHARACTERISTICS (Input amplifier is set for unity gain, noninverting; maximum gain output.) Symbol Parameter Test Conditions Min. Typ. Max. Unit G RX Gain Relative to Gain at 1.02 kHz 0 dBm0 Signal Input at VFX I+ 16.67Hz –3 0 d B 50Hz –2 5 d B 60Hz –2 3 d B 200Hz – 1.8 – 0.125 dB 300 to 3000Hz – 0.125 + 0.125 dB 3300Hz – 0.35 + 0.03 dB 3400Hz – 0.7 – 0.10 dB 4000Hz –1 4 d B 4600Hz and Above –3 2 d B A.C. CHARACTERISTICS (continued) Figure 5:Transmit Filter M5913

RECEIVE CHANNEL TRANSFER CHARACTERISTICS Symbol Parameter Test Conditions Min. Typ. Max. Unit G RR Gain Relative to Gainat 1.02kHz 0dBm0 Signal Input at DR below 200Hz + 0.125 dB 200Hz – 0.5 + 0.125 dB 300 to 3000Hz – 0.125 + 0.125 dB 3300Hz – 0.35 + 0.03 dB 3400Hz – 0.7 – 0.1 dB 4000Hz –1 4 d B 4600Hz and Above –3 0 d B A.C. CHARACTERISTICS (continued) Figure 6:Receive Filter M5913

AC CHARACTERISTICS - TIMING PARAMETERS Symbol Parameter Test Conditions Min. Typ. Max. Unit CLOCK SECTION tCY Clock Period, CLKX, CLKR fCLKX =fCLKR = 2.048MHz 488 ns tCLK Clock Pulse Width CLK X,C L KR 195 ns tDCLK Data Clock Pulse Width1 64kHz ≤ fDCLK ≤ 2.048MHz 195 ns tCDC Clock Duty Cycle CLK X,C L KR 40 50 60 % tr,tf Clock Rise and Fall Time 5 30 ns TRANSMIT SECTION, FIXED DATA RATE MODE 2 tDZX Data Enabled on TS Entry 0 < C LOAD < 100pF 0 145 ns tDDX Data Delay from CLKX 0<C LOAD < 100pF 0 145 ns tHZX Data Float on TS Exit C LOAD = 0 60 190 ns tSON Timeslot X to Enable 0 < C LOAD < 100pF 0 145 ns tSOFF Timeslot X to Disable C LOAD = 0 50 190 ns tFSD Frame Sync Delay 0 120 ns tSS Signal Setup Time 0 ns tSH Signal Setup Time 0 ns RECEIVE SECTION, FIXED DATA RATE MODE tDSR Receive Data Setup 10 ns tDHR Receive Data Hold 60 ns tFSD Frame Sync Delay 0 120 ns tSIGR SIGR Update 0 2 µs TRANSMIT SECTION, FIXED DATA RATE MODE 2 tTSDX Timeslot Delay from DCLKX -80 80 ns tFSD Frame Sync Delay 0 120 ns tDDX Data Delay from DCLKX 0 < CLOAD < 100pF 0 100 ns tDON Timeslot to DX Active 0 < C LOAD < 100pF 0 50 ns tDOFF Timeslot to DX Inactive 0 < C LOAD < 100pF 0 80 ns fDX Data Clock Frequency 64 2048 1 KHz tDFSX Data Delay from FSX tTSDX = 80ns 0 140 ns RECEIVE SECTION, FIXED DATA RATE MODE tTSDR Timeslot Delay from DCLKR -80 80 ns tFSD Frame Sync Delay 0 120 ns tDSR Receive Data Setup Time 10 ns tDHR Receive Data Hold Time 60 ns tDR Data Clock Frequency 64 2048 1 kHz tSER Timeslot End Receive Time 0 ns 64KB OPERATION, VARIABLE DATA RATE MODE tFSLX Transmit Frame Sync Minimum Downtime FS X is TTL high for remainder of frame 488 ns tFSLR Receive Frame Sync Miniumum Downtime FS R is TTL high for remainder of frame 1952 ns tDCLK Data Clock Pulse Width 10 µs Notes: 1. Devices are available wich operate at data rates up to 4.096MHz; the minimum data clock pulse width for these devices is 110ns 2. Timing parameters tDZX ,tHZX , and tSOFF are referenced to a high impedance state. M5913

WAVEFORMS: Fixed Data Rate Timing - Transmit Timing NOTE: All timing paramete rs referenced to VIH and VILexcept tDZX ,tSOFF and tHZX which reference a high impedance state. NOTE: All timing paramete rs referenced to VIH and VIL M5913

AC Timing Input, Output Waveform M5913

DIP20 PACKAGE MECHANICAL DATA DIM. mm inch a1 0.254 0.010 B 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L 3.3 0.130 Z 1.34 0.053 M5913

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