M58WR064

M58WR064ET STMICROELECTRONICS | Alldatasheet

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64 Mbit (4Mb x 16, Multiple Bank, Burst)

Figure 1. Package

M58WR064ET, M58WR064EB SUMMARY DESCRIPTION The M58WR064E is a 64 Mbit (4Mbit x16) non-vol- atile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2.2V V DD supply for the circuitry and a 1.65V to 3.3V VDDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to speed up custom- er programming. The device features an asymmetrical block archi- tecture. M58WR064E has an array of 135 blocks, and is divided into 4 Mbit banks. There are 15 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 pa- rameter blocks of 4 KWords and 7 main blocks of 32 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory maps are shown in Figure 4. The Param- eter Blocks are located at the top of the memory address space for the M58WR064ET, and at the bottom for the M58WR064EB. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage V DD . There are two Enhanced Factory programming commands available to speed up programming. Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the tim- ings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC stan- dards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 54MHz. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switch- es to the Automatic Standby mode. In this condi- tion the power consumption is reduced to the standby value I DD4 and the outputs are still driven. The M58WR064E features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any acciden- tal programming or erasure. There is an additional hardware protection against program and erase. When V PP ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at Power- Up. The device includes a Protection Register and a Security Block to increase the protection of a sys- tem’s design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. The Security Block, pa- rameter block 0, can be permanently protected by the user. Figure 5, shows the Security Block and Protection Register Memory Map. The memory is offered in a VFBGA56, 7.7 x 9 mm 0.75 mm ball pitch package and is supplied with all the bits erased (set to ’1’).

Figure 2. Logic Diagram Table 1. Signal Names

Figure 3. VFBGA Connections (Top view through package) Table 2. Bank Architecture

Figure 4. Memory Map

8 Main

32 KWord000000h

32 KWord038000h

32 KWord300000h

32 KWord338000h

32 KWord340000h

32 KWord378000h

32 KWord380000h

32 KWord3B8000h

32 KWord3C0000h

32 KWord3F0000h

4 KWord3F8000h

4 KWord3FF000h

8 Parameter

4 KWord000000h

32 KWord008000h

32 KWord040000h

32 KWord078000h

32 KWord080000h

32 KWord0B8000h

32 KWord0C0000h

32 KWord0F8000h

32 KWord3F8000h

7 Main

M58WR064ET, M58WR064EB SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Bus Write operation. Chip Enable (E ). The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. When Chip Enable is at V ILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Output Enable (G ).The Output Enable controls data outputs during the Bus Read operation of the memory. Write Enable (W ).The Write Enable controls the Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Write Protect (WP ). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V IL, the Lock- Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or un- locked. (refer to Table 13, Lock Status). Reset (RP ). The Reset input provides a hard- ware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is re- duced to the Reset Supply Current I DD2 . Refer to Table 2, DC Characteristics - Currents for the val- ue of I DD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal op- eration. Exiting reset mode the device enters asynchronous read mode, but a negative transi- tion of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic with- out any additional circuitry. It can be tied to V RPH (refer to Table 19, DC Characteristics). Latch Enable (L).Latch Enable latches the ad- dress bits on its rising edge. The address latch is transparent when Latch Enable is at V IL and it is inhibited when Latch Enable is at V IH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Clock (K).The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configura- tion settings) when Latch Enable is at V IL. Clock is don't care during asynchronous read and in write operations. Wait (WAIT).Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high imped- ance when Chip Enable is at V IH or Reset is at VIL. It can be configured to be active during the wait cy- cle or one clock cycle in advance. The WAIT signal is not gated by Output Enable. V DD Supply Voltage .VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage.VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD . VDDQ can be tied to VDD or can use a separate supply. VPP Program Supply Voltage.VPP i s b o t h a control input and a power supply pin. The two functions are selected by the voltage range ap- plied to the pin. If V PP is kept in a low voltage range (0V to VDDQ ) VPP is seen as a control input. In this case a volt- age lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 en- ables these functions (see Tables 18 and 19, DC Characteristics for the relevant values). V PP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase op- erations continue. If V PP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable un- til the Program/Erase algorithm is completed. VSS Ground. VSS ground is the reference for the core supply. It must be connected to the system ground. VSSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by VDDQ . VSSQ must be connected to VSS Note: Each device in a system should have V DD , VDDQ and VPP decoupled with a 0.1µF ce- ramic capacitor close to the pin (high frequen- cy, inherently low inductance capacitors should be as close as possible to the pack-

dress Latch, Output Disable, Standby and Reset. See Table 3, Bus Operations, for a summary. not affect Bus Write operations. the memory (see Command Interface section). details of the timing requirements. aborted and the memory content is no longer valid. Table 3. Bus Operations

1. L can be tied to VIH if the valid address has been previously latched.
2. WAIT signal polarity is configured using the Set Configuration Register command.

the progress or the result of the operation. invalid combination of commands will be ignored. plain in detail how to perform each command. Table 4. Command Codes

M58WR064ET, M58WR064EB COMMAND INTERFACE - STANDARD COMMANDS The following commands are the basic commands used to read, write to and configure the device. Refer to Table 5, Standard Commands, in con- junction with the following text descriptions. Read Array Command The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command and re- turn the addressed bank to Read Array mode. Subsequent read operations will read the ad- dressed location and output the data. A Read Ar- ray command can be issued in one bank while programming or erasing in another bank. However if a Read Array command is issued to a bank cur- rently executing a Program or Erase operation the command will be executed but the output data is not guaranteed. Read Status Register Command The Status Register indicates when a Program or Erase operation is complete and the success or failure of operation itself. Issue a Read Status Register command to read the Status Register content. The Read Status Register command can be issued at any time, even during Program or Erase operations. The following read operations output the content of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G returns to VIH. Either E or G must be toggled to update the latched data. See Table 8 for the description of the Status Register Bits. This mode supports asyn- chronous or single synchronous reads only. Read Electronic Signature Command The Read Electronic Signature command reads the Manufacturer and Device Codes, the Block Locking Status, the Protection Register, and the Configuration Register. The Read Electronic Signature command consists of one write cycle to an address within one of the banks. A subsequent Read operation in the same bank will output the Manufacturer Code, the De- vice Code, the protection Status of the blocks in the targeted bank, the Protection Register, or the Configuration Register (see Table 6). If a Read Electronic Signature command is issued in a bank that is executing a Program or Erase op- eration the bank will go into Read Electronic Sig- nature mode, subsequent Bus Read cycles will output the Electronic Signature data and the Pro- gram/Erase controller will continue to program or erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads. Read CFI Query Command The Read CFI Query command is used to read data from the Common Flash Interface (CFI). The Read CFI Query Command consists of one Bus Write cycle, to an address within one of the banks. Once the command is issued subsequent Bus Read operations in the same bank read from the Common Flash Interface. If a Read CFI Query command is issued in a bank that is executing a Program or Erase operation the bank will go into Read CFI Query mode, subse- quent Bus Read cycles will output the CFI data and the Program/Erase controller will continue to Program or Erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support page mode or syn- chronous burst reads. The status of the other banks is not affected by the command (see Table 11). After issuing a Read CFI Query command, a Read Array command should be issued to the addressed bank to return the bank to Read Array mode. See Appendix C, Common Flash Interface, Tables 30, 31, 32, 33, 34, 36, 37, 38 and 39 for details on the information contained in the Common Flash In- terface memory area. Clear Status Register Command The Clear Status Register command can be used to reset (set to ‘0’) error bits 1, 3, 4 and 5 in the Sta- tus Register. One bus write cycle is required to is- sue the Clear Status Register command. The Clear Status Register command does not change the Read mode of the bank. The error bits in the Status Register do not auto- matically return to ‘0’ when a new command is is- sued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Block Erase Command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. The Block Erase command can be issued at any moment, re- gardless of whether the block has been pro- grammed or not. Two Bus Write cycles are required to issue the command. ■ The first bus cycle sets up the Erase command. ■ The second latches the block address in the internal state machine and starts the Program/ Erase Controller.

M58WR064ET, M58WR064EB If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits 4 and 5 are set and the command aborts. Erase aborts if Reset turns to V IL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode un- til a Read Array, Read CFI Query or Read Elec- tronic Signature command is issued. During Erase operations the bank containing the block being erased will only accept the Read Ar- ray, Read Status Register, Read Electronic Signa- ture, Read CFI Query and the Program/Erase Suspend command, all other commands will be ig- nored. Refer to Dual Operations section for de- tailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. See Appendix C, Figure 25, Block Erase Flow- chart and Pseudo Code, for a suggested flowchart for using the Block Erase command. Program Command The memory array can be programmed word-by- word. Only one Word in one bank can be pro- grammed at any one time. Two bus write cycles are required to issue the Program Command. ■ The first bus cycle sets up the Program command. ■ The second latches the Address and the Data to be written and starts the Program/Erase Controller. After programming has started, read operations in the bank being programmed output the Status Register content. During Program operations the bank being pro- grammed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend com- mand. Refer to Dual Operations section for de- tailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cy- cles. Programming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. See Appendix C, Figure 21, Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. A Bank Erase operation cannot be suspended. One bus write cycle is required to issue the Pro- gram/Erase command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to ‘1’. The com- mand can be addressed to any bank. During Program/Erase Suspend the Command In- terface will accept the Program/Erase Resume, Read Array (cannot read the erase-suspended block or the program-suspended Word), Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Clear sta- tus Register, Program, Block Lock, Block Lock- Down or Block Unlock commands will also be ac- cepted. The block being erased may be protected by issuing the Block Lock, Block Lock-Down or Protection Register Program commands. Only the blocks not being erased may be read or pro- grammed correctly. When the Program/Erase Re- sume command is issued the operation will complete. Refer to the Dual Operations section for detailed information about simultaneous opera- tions allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to V IH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 24, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 26, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command can be written to any address. The Program/Erase Resume command does not change the read mode of the banks. If the sus- pended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corre- sponding data. If the bank was in Read Array mode subsequent read operations will output in- valid data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be re- sumed until the programming operation has com- pleted. It is possible to accumulate suspend operations. For example: suspend an erase oper- ation, start a programming operation, suspend the

M58WR064ET, M58WR064EB programming operation then read the array. See Appendix C, Figure 24, Program Suspend & Re- sume Flowchart and Pseudo Code, and Figure 26, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Resume command. Protection Register Program Command The Protection Register Program command is used to Program the 128 bit user One-Time-Pro- grammable (OTP) segment of the Protection Reg- ister and the Protection Register Lock. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protec- tion Register Program command. ■ The first bus cycle sets up the Protection Register Program command. ■ The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register. Bit 1 of the Pro- tection Lock Register also protects bit 2 of the Pro- tection Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of Parameter Block #0 (see Figure 5, Security Block and Protection Register Memory Map). Attempting to program a previously protect- ed Protection Register will result in a Status Reg- ister error. The protection of the Protection Register and/or the Security Block is not revers- ible. The Protection Register Program cannot be sus- pended. See Appendix C, Figure 28, Protection Register Program Flowchart and Pseudo Code, for a flowchart for using the Protection Register Program command. Set Configuration Register Command The Set Configuration Register command is used to write a new value to the Burst Configuration Control Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Configuration Register command. ■ The first cycle writes the setup command and the address corresponding to the Configuration Register content. ■ The second cycle writes the Configuration Register data and the confirm command. The Read mode of the banks is not modified when the Set Configuration Register command is is- sued. The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1 on A1, etc.; the other address bits are ignored. Block Lock Command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. ■ The first bus cycle sets up the Block Lock command. ■ The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 13 shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix C, Figure 27, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock command. Block Unlock Command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to is- sue the Block Unlock command. ■ The first bus cycle sets up the Block Unlock command. ■ The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 13 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and Ap- pendix C, Figure 27, Locking Operations Flow- chart and Pseudo Code, for a flowchart for using the Unlock command. Block Lock-Down Command A locked or unlocked block can be locked-down by issuing the Block Lock-Down command. A locked- down block cannot be programmed or erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock com- mand. Two Bus Write cycles are required to issue the Block Lock-Down command. ■ The first bus cycle sets up the Block Lock command.

using the Read Electronic Signature command. for using the Lock-Down command. Table 5. Standard Commands Register Data, CRD=Configuration Register Data.

1. Must be same bank as in the first cycle. The signature addresses are listed in Table 6.
2. Any address within the bank can be used.

Table 6. Electronic Signature Codes Note: CR=Configuration Register. Figure 5. Security Block and Protection Register Memory Map

M58WR064ET, M58WR064EB COMMAND INTERFACE - FACTORY PROGRAM COMMANDS The Factory Program commands are used to speed up programming. They require VPP to be at VPPH except for the Bank Erase command which also operates at VPP = VDD . Refer to Table 7, Fac- tory Program Commands, in conjunction with the following text descriptions. The use of Factory Program commands requires certain operating conditions. ■ VPP must be set to VPPH (except for Bank Erase command), ■ VDD must be within operating range, ■ Ambient temperature, TA must be 25°C ± 5°C, ■ The targeted block must be unlocked. Bank Erase Command The Bank Erase command can be used to erase a bank. It sets all the bits within the selected bank to ’1’. All previous data in the bank is lost. The Bank Erase command will ignore any protected blocks within the bank. If all blocks in the bank are pro- tected then the Bank Erase operation will abort and the data in the bank will not be changed. The Status Register will not output any error. Bank Erase operations can be performed at both V PP = VPPH and VPP = VDD . Two Bus Write cycles are required to issue the command. ■ The first bus cycle sets up the Bank Erase command. ■ The second latches the bank address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Bank Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the bank must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode un- til a Read Array, Read CFI Query or Read Elec- tronic Signature command is issued. During Bank Erase operations the bank being erased will only accept the Read Array, Read Sta- tus Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. For optimum performance, Bank Erase com- mands should be limited to a maximum of 100 Pro- gram/Erase cycles per Block. After 100 Program/ Erase cycles the internal algorithm will still operate properly but some degradation in performance may occur. Dual operations are not supported during Bank Erase operations and the command cannot be suspended. Typical Erase times are given in Table 14, Pro- gram, Erase Times and Program/Erase Endur- ance Cycles. Double Word Program Command The Double Word Program command improves the programming throughput by writing a page of two adjacent words in parallel. The two words must differ only for the address A0. Three bus write cycles are necessary to issue the Double Word Program command. ■ The first bus cycle sets up the Double Word Program Command. ■ The second bus cycle latches the Address and the Data of the first word to be written. ■ The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations in the bank being programmed output the Status Register content after the pro- gramming has started. During Double Word Program operations the bank being programmed will only accept the Read Ar- ray, Read Status Register, Read Electronic Signa- ture and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Double Word Program oper- ations and the command cannot be suspended. Typical Program times are given in Table 14, Pro- gram, Erase Times and Program/Erase Endur- ance Cycles. Programming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. See Appendix C, Figure 22, Double Word Pro- gram Flowchart and Pseudo Code, for the flow- chart for using the Double Word Program command. Quadruple Word Program Command The Quadruple Word Program command im- proves the programming throughput by writing a page of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. Five bus write cycles are necessary to issue the Quadruple Word Program command. ■ The first bus cycle sets up the Double Word Program Command. ■ The second bus cycle latches the Address and the Data of the first word to be written.

M58WR064ET, M58WR064EB ■ The third bus cycle latches the Address and the Data of the second word to be written. ■ The fourth bus cycle latches the Address and the Data of the third word to be written. ■ The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the pro- gramming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. During Quadruple Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Sig- nature and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Quadru- ple Word Program operations and the command cannot be suspended. Typical Program times are given in Table 14, Program, Erase Times and Pro- gram/Erase Endurance Cycles. See Appendix C, Figure 23, Quadruple Word Pro- gram Flowchart and Pseudo Code, for the flow- chart for using the Quadruple Word Program command. Enhanced Factory Program Command The Enhanced Factory Program command can be used to program large streams of data within any one block. It greatly reduces the total program- ming time when a large number of Words are writ- ten to a block at any one time. Dual operations are not supported during the En- hanced Factory Program operation and the com- mand cannot be suspended. For optimum performance the Enhanced Factory Program commands should be limited to a maxi- mum of 10 program/erase cycles per block. If this limit is exceeded the internal algorithm will contin- ue to work properly but some degradation in per- formance is possible. Typical Program times are given in Table 14. The Enhanced Factory Program command has four phases: the Setup Phase, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary and the Exit Phase. Refer to Table 7, Enhanced Factory Program Command and Figure 29, Enhanced Factory Program Flowchart. Setup Phase. The Enhanced Factory Program command requires two Bus Write operations to ini- tiate the command. ■ The first bus cycle sets up the Enhanced Factory Program command. ■ The second bus cycle confirms the command. The Status Register P/E.C. Bit 7 should be read to check that the P/E.C. is ready. After the confirm command is issued, read operations output the Status Register data. The read Status Register command must not be issued as it will be interpreted as data to program. Program Phase. The Program Phase requires n+1 cycles, where n is the number of Words (refer to Table 7, Enhanced Factory Program Command and Figure 29, Enhanced Factory Program Flow- chart). Three successive steps are required to issue and execute the Program Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address can either remain the Start Address, in which case the P/E.C. increments the address location or the address can be incremented in which case the P/E.C. jumps to the new address. If any address that is not in the same block as the Start Address is given with data FFFFh, the Program Phase terminates and the Verify Phase begins. The Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the programming phase. If the data is not FFFFh, the command is ignored. The memory is now set to enter the Verify Phase. Verify Phase.The Verify Phase is similar to the Program Phase in that all Words must be resent to the memory for them to be checked against the programmed data. The Program/Erase Controller checks the stream of data with the data that was programmed in the Program Phase and repro- grams the memory location if necessary. Three successive steps are required to execute the Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word, to be verified. The Status Register bit SR0 should be read to check that the Program/Erase Controller is ready for the next Word.

M58WR064ET, M58WR064EB 2. Each subsequent Word to be verified is latched with a new Bus Write operation. The Words must be written in the same order as in the Program Phase. The address can remain the Start Address or be incremented. If any address that is not in the same block as the Start Address is given with data FFFFh, the Verify Phase terminates. Status Register bit SR0 should be read to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been verified, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Verify Phase. If the Verify Phase is successfully completed the memory remains in Read Status Register mode. If the Program/Erase Controller fails to reprogram a given location, the error will be signaled in the Sta- tus Register. Exit Phase.Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has returned to Read mode. A full Status Register check should be done to ensure that the block has been successfully pro- grammed. See the section on the Status Register for more details. Quadruple Enhanced Factory Program Command The Quadruple Enhanced Factory Program com- mand can be used to program one or more pages of four adjacent Words in parallel. The four Words must differ only for the addresses A0 and A1. Dual operations are not supported during Quadru- ple Enhanced Factory Program operations and the command cannot be suspended. The Quadruple Enhanced Factory Program com- mand has four phases: the Setup Phase, the Load Phase where the data is loaded into the buffer, the combined Program and Verify Phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the Exit Phase. Unlike the En- hanced Factory Program it is not necessary to re- submit the data for the Verify Phase. The Load Phase and the Program and Verify Phase can be repeated to program any number of pages within the block. Setup Phase. The Quadruple Enhanced Factory Program command requires one Bus Write opera- tion to initiate the load phase. After the setup command is issued, read operations output the Status Register data. The Read Status Register command must not be issued as it will be interpreted as data to program. Load Phase. The Load Phase requires 4 cycles to load the data (refer to Table 7, Factory Program Commands and Figure 30, Quadruple Enhanced Factory Program Flowchart). Once the first Word of each Page is written it is impossible to exit the Load phase until all four Words have been written. Two successive steps are required to issue and execute the Load Phase of the Quadruple En- hanced Factory Program command. 1. Use one Bus Write operation to latch the Start Address and the first Word of the first Page to be programmed. For subsequent Pages the first Word address can remain the Start Address (in which case the next Page is programmed) or can be any address in the same block. If any address with data FFFFh is given that is not in the same block as the Start Address, the device enters the Exit Phase. For the first Load Phase Status Register bit SR7 should be read after the first Word has been issued to check that the command has been accepted (bit SR7 set to ‘0’). This check is not required for subsequent Load Phases. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address is only checked for the first Word of each Page as the order of the Words to be programmed is fixed. The memory is now set to enter the Program and Verify Phase. Program and Verify Phase.In the Program and Verify Phase the four Words that were loaded in the Load Phase are programmed in the memory array and then verified by the Program/Erase Con- troller. If any errors are found the Program/Erase Controller reprograms the location. During this phase the Status Register shows that the Pro- gram/Erase Controller is busy, Status Register bit SR7 set to ‘0’, and that the device is not waiting for new data, Status Register bit SR0 set to ‘1’. When Status Register bit SR0 is set to ‘0’ the Program and Verify phase has terminated. Once the Verify Phase has successfully complet- ed subsequent pages in the same block can be loaded and programmed. The device returns to the beginning of the Load Phase by issuing one Bus Write operation to latch the Address and the first of the four new Words to be programmed. Exit Phase.Finally, after all the pages have been programmed, write one Bus Write operation with data FFFFh to any address outside the block con- taining the Start Address, to terminate the Load and Program and Verify Phases. Status Register bit SR7 set to ‘1’ and bit SR0 set to ‘0’ indicate that the Quadruple Enhanced Facto- ry Program command has terminated. A full Status Register check should be done to ensure that the block has been sucessfully programmed. See the section on the Status Register for more details. If the Program and Verify Phase has successfully completed the memory returns to Read mode. If

Table 7. Factory Program Commands Note: 1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address.

1. WA1 is the Start Address. NOT WA1 is any address that is not in the same block as WA1.
2. Address can remain Starting Address WA1 or be incremented.
3. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0.
4. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
5. A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register and

check that the memory is ready to accept the next data. n = number of Words, i = number of Pages to be programmed.

1. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so subsequent

Words in each Page can be written to any address.

1. Any address within the bank can be used.
2. Any address within the block can be used.

M58WR064ET, M58WR064EB STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more de- tails. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to V IH. The Status Register can only be read using single asynchronous or single synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during Pro- gram and Erase operations. The various bits convey information about the sta- tus and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on er- rors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the ad- dressed bank. The bits in the Status Register are summarized in Table 8, Status Register Bits. Refer to Table 8 in conjunction with the following text descriptions. Program/Erase Controller Status Bit (SR7).The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Pro- gram/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low im- mediately after a Program/Erase Suspend com- mand is issued until the Program/Erase Controller pauses. After the Program/Erase Controller paus- es the bit is High. During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Reg- ister should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, V PP Status and Block Lock Status bits should be tested for errors. Erase Suspend Status Bit (SR6).The Erase Suspend Status bit indicates that an Erase opera- tion has been suspended or is going to be sus- pended in the addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Re- sume command. The Erase Suspend Status should only be consid- ered valid when the Program/Erase Controller Sta- tus bit is High (Program/Erase Controller inactive). SR7 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status Bit (SR5).The Erase Status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maxi- mum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be re- set Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status Bit (SR4).The Program Status bit is used to identify a Program failure or an at- tempt to program a ‘1’ to an already programmed bit when V PP = VPPH . When the Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. After an attempt to program a '1' to an already pro- grammed bit, the Program Status bit SR4 only goes High (set to '1') if V PP = VPPH (if VPP is differ- ent from VPPH , SR4 remains Low (set to '0') and the attempt is not shown). The Program Status bit should be read once the Program/Erase Controller Status bit is High (Pro- gram/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. V PP Status Bit (SR3).The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program

M58WR064ET, M58WR064EB or Erase operation. Indeterminate results can oc- cur if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to ‘0’), the volt- age on the VPP pin was sampled at a valid voltage; when the VPP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK , the memory is protected and Pro- gram and Erase operations cannot be performed. Once set High, the VPP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status Bit (SR2).The Pro- gram Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend com- mand has been issued and the memory is waiting for a Program/Erase Resume command. The Pro- gram Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command be- ing issued therefore the memory may still com- plete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is is- sued the Program Suspend Status bit returns Low. Block Protection Status Bit (SR1).The Block Protection Status bit can be used to identify if a Program or Block Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to ‘1’), a Program or Erase operation has been at- tempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register com- mand or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. Bank Write/Multiple Word Program Status Bit (SR0).The Bank Write Status bit indicates wheth- er the addressed bank is programming or erasing. In Enhanced Factory Program mode the Multiple Word Program bit shows if a Word has finished programming or verifying depending on the phase. The Bank Write Status bit should only be consid- ered valid when the Program/Erase Controller Sta- tus SR7 is Low (set to ‘0’). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to ‘0’), the addressed bank is executing a Program or Erase operation. When the Program/Erase Con- troller Status bit is Low (set to ‘0’) and the Bank Write Status bit is High (set to ‘1’), a Program or Erase operation is being executed in a bank other than the one being addressed. In Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to ‘0’), the de- vice is ready for the next Word, if the Multiple Word Program Status bit is High (set to ‘1’) the device is not ready for the next Word. Note: Refer to Appendix C, Flowcharts and Pseu- do Codes, for using the Status Register.

Table 8. Status Register Bits Note: Logic level '1' is High, '0' is Low.

M58WR064ET, M58WR064EB CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will per- form. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power-Up the device is configured for asynchronous page read (CR15 = 1). The Configuration Register bits are described in Table 9. They specify the selec- tion of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 6 and 7 for examples of synchronous burst configurations. Read Select Bit (CR15) The Read Select bit, CR15, is used to switch be- tween asynchronous and synchronous Bus Read operations. When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst Read is support- ed in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to’1’ for asynchronous access. X-Latency Bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Ta- ble 9, Configuration Register. The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system pa- rameters. Two conditions must be satisfied: 1. Depending on whether t AVK_CPU or tDELAY is supplied either one of the following two equations must be satisfied: (n + 1) t K ≥ tACC - tAVK_CPU + tQVK_CPU (n + 2) tK ≥ tACC + tDELAY + tQVK_CPU 2. and also tK > tKQV + tQVK_CPU where n is the chosen X-Latency configuration code t K is the clock period tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last t DELAY is address valid, L Low, or E Low to clock, whichever occurs last tQVK_CPU is the data setup time required by the system CPU, tKQV is the clock to data valid time tACC is the random access time of the device. Refer to Figure 6, X-Latency and Data Output Configuration Example. Wait Polarity Bit (CR10) In synchronous burst mode the Wait signal indi- cates whether the output data are valid or a WAIT state must be inserted. The Wait Polarity bit is used to set the polarity of the Wait signal. When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait Polarity bit is set to ‘1’ the Wait signal is active High (default). Data Output Configuration Bit (CR9) The Data Output Configuration bit determines whether the output remains valid for one or two clock cycles. When the Data Output Configuration Bit is ’0’ the output data is valid for one clock cycle, when the Data Output Configuration Bit is ’1’ the output data is valid for two clock cycles. The Data Output Configuration depends on the condition: ■ tK > tKQV + tQVK_CPU where tK is the clock period, tQVK_CPU is the data setup time required by the system CPU and tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 6, X-Latency and Data Output Configuration Exam- ple. Wait Configuration Bit (CR8) In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When WAIT is asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid. When the Wait bit is ’0’ the Wait out- put pin is asserted during the wait state. When the Wait bit is ’1’ (default) the Wait output pin is assert- ed one clock cycle before the wait state. Burst Type Bit (CR7) The Burst Type bit is used to configure the se- quence of addresses read as sequential or inter- leaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses; when the Burst Type bit is ’1’ (default) the memory outputs from sequential addresses. See Tables 10, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode. Valid Clock Edge Bit (CR6) The Valid Clock Edge bit, CR6, is used to config- ure the active edge of the Clock, K, during Syn- chronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock is active. Wrap Burst Bit (CR3) The burst reads can be confined inside the 4 or 8 Word boundary (wrap) or overcome the boundary

M58WR064ET, M58WR064EB (no wrap). The Wrap Burst bit is used to select be- tween wrap and no wrap. When the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not wrap. Burst length Bits (CR2-CR0) The Burst Length bits set the number of Words to be output during a Synchronous Burst Read oper- ation as result of a single address latch cycle. They can be set for 4 words, 8 words or continu- ous burst, where all the words are read sequential- ly. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8 words no-wrap, depending on the starting address, the device as- serts the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1,2 or 3 posi- tions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 10, Burst Type Definition. CR14, CR5 and CR4 are reserved for future use.

Table 9. Configuration Register

0 Synchronous Read

1 Asynchronous Read (Default at power-on)

111 Reserved (default)

0 WAIT is active Low

1 WAIT is active high (default)

0 Data held for one clock cycle

1 Data held for two clock cycles (default)

0 WAIT is active during wait state

1 WAIT is active one data cycle before wait state (default)

0 Interleaved

1 Sequential (default)

0 Falling Clock edge

1 Rising Clock edge (default)

0 Wrap

1 No Wrap (default)

111 Continuous (CR7 m ust be set to ‘1’) (default)

Table 10. Burst Type Definition

M58WR064ET, M58WR064EB READ MODES Read operations can be performed in two different ways depending on the settings in the Configura- tion Register. If the clock signal is ‘don’t care’ for the data output, the read operation is Asynchro- nous; if the data output is synchronized with clock, the read operation is Synchronous. The Read mode and data output format are deter- mined by the Configuration Register. (See Config- uration Register section for details). All banks supports both asynchronous and synchronous read operations. The Multiple Bank architecture allows read operations in one bank, while write op- erations are being executed in another (see Ta- bles 11 and 12). Asynchronous Read Mode In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data corre- sponding to the address latched, that is the mem- ory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Reg- ister must be set to ‘1’ for Asynchronous opera- tions. In Asynchronous Read mode a Page of data is in- ternally read and stored in a Page Buffer. The Page has a size of 4 Words and is addressed by A0 and A1 address inputs. The address inputs A0 and A1 are not gated by Latch Enable in Asyn- chronous Read mode. The first read operation within the Page has a longer access time (T acc, Random access time), subsequent reads within the same Page have much shorter access times. If the Page changes then the normal, longer timings apply again. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Ac- cess Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. During Asynchronous Read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, the WAIT signal is always asserted. See Table 20, Asynchronous Read AC Character- istics, Figure 10, Asynchronous Random Access Read AC Waveform and Figure 11, Asynchronous Page Read AC Waveform for details. Synchronous Burst Read Mode In Synchronous Burst Read mode the data is out- put in bursts synchronized with the clock. It is pos- sible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read opera- tions, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchro- nous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are con- figured in the Configuration Register. A burst sequence is started at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and after a delay of 2 to 5 clock cycles (X latency bits CR13-CR11) the corresponding data are out- put on each clock cycle. The number of Words to be output during a Syn- chronous Burst Read operation can be configured as 4 or 8 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Con- figuration bit CR9). The order of the data output can be modified through the Burst Type and the Wrap Burst bits in the Configuration Register. The burst sequence may be configured to be sequential or interleaved (CR7). The burst reads can be confined inside the 4 or 8 Word boundary (Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to the Burst Length (4 or 8 Words), the wrapped configuration has no impact on the output sequence. Interleaved mode is not allowed in Con- tinuous Burst Read mode or with No Wrap se- quences. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst se- quence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. WAIT is asserted during X latency, the Wait state and at the end of 4- and 8-Word burst. It is only deasserted when output data are valid. In Contin- uous Burst Read mode a Wait state will occur when crossing the first 64 Word boundary. If the burst starting address is aligned to a 4 Word Page, the Wait state will not occur. The WAIT signal can be configured to be active Low or active High (default) by setting CR10 in the Configuration Register. The WAIT signal is mean- ingful only in Synchronous Burst Read mode, in

only the first data output after the X latency is valid. erations are possible at any moment. pendix D, Command Interface State Tables. Table 11. Dual Operations Allowed In Other Banks Table 12. Dual Operations Allowed In Same Bank Note: 1. Not allowed in the Block or Word that is being erased or programmed.

1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.

M58WR064ET, M58WR064EB BLOCK LOCKING The M58WR064E features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. ■ Lock/Unlock - this first level allows software- only control of block locking. ■ Lock-Down - this second level requires hardware interaction before locking can be changed. ■ VPP ≤ VPPLK - the third level offers a complete hardware protection against program and erase on all blocks. The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 13, de- fines all of the possible protection states (WP DQ1, DQ0), and Appendix C, Figure 27, shows a flowchart for the locking operations. Reading a Block’s Lock Status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subse- quent reads at the address specified in Table 6, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when enter- ing Lock-Down. DQ1 indicates the Lock-Down sta- tus and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or af- ter a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase oper- ations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software com- mands. An Unlocked block can be Locked by issu- ing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be un- locked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status can- not be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. Locked- Down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from pro- gram, erase and protection status changes. When WP =1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individual- ly unlocked to the (1,1,0) state by issuing the soft- ware command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase opera- tion, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After complet- ing any desired lock, read, or program operations, resume the erase operation with the Erase Re- sume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix , Command Interface State Table, for detailed information on which commands are valid during erase suspend.

Table 13. Lock Status in the Read Electronic Signature command with A1 = VIH and A0 = VIL.

1. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
2. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

Table 14. Program, Erase Times and Program, Erase Endurance Cycles

1. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms).
2. Excludes the time needed to execute the command sequence.
3. Measurements performed at 25°C. T

A = 25°C ±5°C for Quadruple Word, Double Word and Quadruple Enhanced Factory Program.

Table 15. Absolute Maximum Ratings

ing on the quoted parameters. Table 16. Operating and AC Measurement Conditions Figure 8. AC Measurement I/O Waveform Figure 9. AC Measurement Load Circuit Table 17. Capacitance Note: Sampled only, not 100% tested.

Table 18. DC Characteristics - Currents Note: 1. Sampled only, not 100% tested.

1. VDD Dual Operation current is the sum of read and program or erase currents.

4 Word 6 13 mA

8 Word 8 14 mA

4 Word 7 16 mA

8 Word 10 18 mA

Table 19. DC Characteristics - Voltages

Figure 10. Asynchronous Random Access Read AC Waveforms Note. Write Enable, W, is High, WAIT is active Low.

Figure 11. Asynchronous Page Read AC Waveforms

Table 20. Asynchronous Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV .

Figure 12. Synchronous Burst Read AC Waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.

1. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, K, can be configured as the active edge.

Here the active edge of K is the rising one.

Figure 13. Single Synchronous Read AC Waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.

1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. WAIT is always asserted when addressed bank is in Read CFI, Read SR or Read electronic signature mode.

WAIT signals valid data if the addressed bank is in Read Array mode.

1. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, K, can be configured as the active edge.

Here the active edge of K is the rising one.

Figure 14. Clock input AC Waveform Table 21. Synchronous Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. For other timings please refer to Table 20, Asynchronous Read AC Characteristics.

Figure 15. Write AC Waveforms, Write Enable Controlled

Table 22. Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.

1. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a

different bank tWHEL is 0ns.

1. Meaningful only if L is always kept low.

Figure 16. Write AC Waveforms, Chip Enable Controlled

Table 23. Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested.

1. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a

different bank tWHEL is 0ns.

Figure 17. Reset and Power-up AC Waveforms Table 24. Reset and Power-up AC Characteristics Note: 1. The device Reset is possible but not guaranteed if tPLPH < 50ns.

1. Sampled only, not 100% tested.
2. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.

Figure 18. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline Note: Drawing is not to scale. Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data

Figure 19. VFBGA56 Daisy Chain - Package Connections (Top view through package)

Figure 20. VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package)

Table 26. Ordering Information Scheme Table 27. Daisy Chain Ordering Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. vice, please contact the ST Sales Office nearest to you.

Table 28. Top Boot Block Addresses,

M58WR064ET, M58WR064EB Note: There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 contains the banks that are made up of the parameter and main blocks. Bank 9 79 32 1B8000-1BFFFF 80 32 1B0000-1B7FFF 81 32 1A8000-1AFFFF 82 32 1A0000-1A7FFF 83 32 198000-19FFFF 84 32 190000-197FFF 85 32 188000-18FFFF 86 32 180000-187FFF Bank 10 87 32 178000-17FFFF 88 32 170000-177FFF 89 32 168000-16FFFF 90 32 160000-167FFF 91 32 158000-15FFFF 92 32 150000-157FFF 93 32 148000-14FFFF 94 32 140000-147FFF Bank 11 95 32 138000-13FFFF 96 32 130000-137FFF 97 32 128000-12FFFF 98 32 120000-127FFF 99 32 118000-11FFFF 100 32 110000-117FFF 101 32 108000-10FFFF 102 32 100000-107FFF Bank 12 103 32 0F8000-0FFFFF 104 32 0F0000-0F7FFF 105 32 0E8000-0EFFFF 106 32 0E0000-0E7FFF 107 32 0D8000-0DFFFF 108 32 0D0000-0D7FFF 109 32 0C8000-0CFFFF 110 32 0C0000-0C7FFF Bank 13 111 32 0B8000-0BFFFF 112 32 0B0000-0B7FFF 113 32 0A8000-0AFFFF 114 32 0A0000-0A7FFF 115 32 098000-09FFFF 116 32 090000-097FFF 117 32 088000-08FFFF 118 32 080000-087FFF Bank 14 119 32 078000-07FFFF 120 32 070000-077FFF 121 32 068000-06FFFF 122 32 060000-067FFF 123 32 058000-05FFFF 124 32 050000-057FFF 125 32 048000-04FFFF 126 32 040000-047FFF Bank 15 127 32 038000-03FFFF 128 32 030000-037FFF 129 32 028000-02FFFF 130 32 020000-027FFF 131 32 018000-01FFFF 132 32 010000-017FFF 133 32 008000-00FFFF 134 32 000000-007FFF

Table 29. Bottom Boot Block Addresses,

M58WR064ET, M58WR064EB Note: There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 contains the banks that are made up of the parameter and main blocks. Bank 5 54 32 178000-17FFFF 53 32 170000-177FFF 52 32 168000-16FFFF 51 32 160000-167FFF 50 32 158000-15FFFF 49 32 150000-157FFF 48 32 148000-14FFFF 47 32 140000-147FFF Bank 4 46 32 138000-13FFFF 45 32 130000-137FFF 44 32 128000-12FFFF 43 32 120000-127FFF 42 32 118000-11FFFF 41 32 110000-117FFF 40 32 108000-10FFFF 39 32 100000-107FFF Bank 3 38 32 0F8000-0FFFFF 37 32 0F0000-0F7FFF 36 32 0E8000-0EFFFF 35 32 0E0000-0E7FFF 34 32 0D8000-0DFFFF 33 32 0D0000-0D7FFF 32 32 0C8000-0CFFFF 31 32 0C0000-0C7FFF Bank 2 30 32 0B8000-0BFFFF 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 0A0000-0A7FFF 26 32 098000-09FFFF 25 32 090000-097FFF 24 32 088000-08FFFF 23 32 080000-087FFF Bank 1 22 32 078000-07FFFF 21 32 070000-077FFF 20 32 068000-06FFFF 19 32 060000-067FFF 18 32 058000-05FFFF 17 32 050000-057FFF 16 32 048000-04FFFF 15 32 040000-047FFF Parameter Bank 14 32 038000-03FFFF 13 32 030000-037FFF 12 32 028000-02FFFF 11 32 020000-027FFF 10 32 018000-01FFFF 9 32 010000-017FFF 8 32 008000-00FFFF 7 4 007000-007FFF 6 4 006000-006FFF 5 4 005000-005FFF 4 4 004000-004FFF 3 4 003000-003FFF 2 4 002000-002FFF 1 4 001000-001FFF 0 4 000000-000FFF

DQ7), the other outputs (DQ8-DQ15) are set to 0. Array command to return to Read mode. Table 30. Query Structure Overview detailed in Tables 31, 32, 33, 34, 36 and 1. Query data is always presented on the lowest order data outputs. Table 31. CFI Query Identification String

Table 32. CFI Query System Interface Information Table 33. Device Geometry Definition

Table 34. Primary Algorithm-Specific Extended Query Table contains less significant byte.

M58WR064ET, M58WR064EB Table 35. Protection Register Information Table 36. Burst Read Information Table 37. Bank and Erase Block Region Information Note: 1. The variable P is a pointer which is defined at CFI offset 15h.

1. Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks

that are made up of the parameter and main blocks. determine page-mode data output width.

8 Bytes

(P+17)h = 50h 0007h Synchronous mode read capability configuration 3 Cont.

Description

(P+18)h =51h 02h (P+18)h =51h 02h Number of Bank Regions within the device Offset Data Description Value

M58WR064ET, M58WR064EB Table 38. Bank and Erase Block Region 1 Information (P+19)h =52h 0Fh (P+19)h =52h 01h Number of identical banks within Bank Region 1 (P+1A)h =53h 00h (P+1A)h =53h 00h (P+1B)h =54h 11h (P+1B)h =54h 11h Number of program or erase operations allowed in region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+1C)h =55h 00h (P+1C)h =55h 00h Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+1D)h =56h 00h (P+1D)h =56h 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+1E)h =57h 01h (P+1E)h =57h 02h Types of erase block regions in region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region. (2) (P+1F)h =58h 07h (P+1F)h =58h 07h Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+20)h =59h 00h (P+20)h =59h 00h (P+21)h =5Ah 00h (P+21)h =5Ah 20h (P+22)h =5Bh 01h (P+22)h =5Bh 00h (P+23)h =5Ch 64h (P+23)h =5Ch 64h Bank Region 1 (Erase Block Type 1) Minimum block erase cycles × 1000(P+24)h =5Dh 00h (P+24)h =5Dh 00h (P+25)h =5Eh 01h (P+25)h =5Eh 01h Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved 5Eh 01 5Eh 01 (P+26)h =5Fh 03h (P+26)h =5Fh 03h Bank Region 1 (Erase Block Type 1): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+27)h =60h 06h Bank Region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+28)h =61h 00h (P+29)h =62h 00h (P+2A)h =63h 01h (P+2B)h =64h 64h Bank Region 1 (Erase Block Type 2) Minimum block erase cycles × 1000(P+2C)h =65h 00h (P+2D)h =66h 01h Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved

M58WR064ET, M58WR064EB Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks that are made up of the parameter and main blocks. Table 39. Bank and Erase Block Region 2 Information (P+27)h =60h 01h (P+2F)h =68h 0Fh Number of identical banks within bank region 2 (P+28)h =61h 00h (P+30)h =69h 00h (P+29)h =62h 11h (P+31)h =6Ah 11h Number of program or erase operations allowed in bank region Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+2A)h =63h 00h (P+32)h =6Bh 00h Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+2B)h =64h 00h (P+33)h =6Ch 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+2C)h =65h 02h (P+34)h =6Dh 01h Types of erase block regions in region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region. (2) (P+2D)h =66h 06h (P+35)h =6Eh 07h Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+2E)h =67h 00h (P+36)h =6Fh 00h (P+2F)h =68h 00h (P+37)h =70h 00h (P+30)h =69h 01h (P+38)h =71h 01h (P+31)h =6Ah 64h (P+39)h =72h 64h Bank Region 2 (Erase Block Type 1) Minimum block erase cycles × 1000(P+32)h =6Bh 00h (P+3A)h =73h 00h (P+33)h =6Ch 01h (P+3B)h =74h 01h Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved M58WR064ET (top) M58WR064EB (bottom)

M58WR064ET, M58WR064EB Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 con- tains the banks that are made up of the parameter and main blocks. (P+34)h =6Dh 03h (P+3C)h =75h 03h Bank Region 2 (Erase Block Type 1): Page mode and synchronous mode capabilities (defined in table 10) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+35)h =6Eh 07h Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+36)h =6Fh 00h (P+37)h =70h 20h (P+38)h =71h 00h (P+39)h =72h 64h Bank Region 2 (Erase Block Type 2) Minimum block erase cycles × 1000(P+3A)h =73h 00h (P+3B)h =74h 01h Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+3C)h =75h 03h Bank Region 2 (Erase Block Type 2): Page mode and synchronous mode capabilities (defined in table 10) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+3D)h =76h (P+3D)h =76h Feature Space definitions (P+3E)h =77h (P+3E)h =77h Reserved M58WR064ET (top) M58WR064EB (bottom)

Figure 21. Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 22. Double Word Program Flowchart and Pseudo code

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
3. Any address within the bank can equally be used.

Figure 23. Quadruple Word Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
3. Any address within the bank can equally be used.

Figure 24. Program Suspend & Resume Flowchart and Pseudo Code

Figure 25. Block Erase Flowchart and Pseudo Code Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations.

1. Any address within the bank can be used also.

Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code

Figure 27. Locking Operations Flowchart and Pseudo Code Note: 1. Any address within the bank can equally be used.

Figure 28. Protection Register Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 29. Enhanced Factory Program Flowchart Note: 1. Address can remain Starting Address WA1 or be incremented.

M58WR064ET, M58WR064EB Enhanced Factory Program Pseudo Code efp_command(addressFlow,dataFlow,n) /* n is the number of data to be programmed */ /* setup phase */ writeToFlash(addressFlow[0],0x30); writeToFlash(addressFlow[0],0xD0); status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); else{ /*Program Phase*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1) /*Ready for first data*/ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ writeToFlash(another_block_address,FFFFh); /* Verify Phase */ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ writeToFlash(another_block_address,FFFFh); /* exit program phase */ /* Exit Phase */ /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR4==1) /*program failure error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler();

Figure 30. Quadruple Enhanced Factory Program Flowchart any address in the same block. so subsequent Words in each Page can be written to any address.

M58WR064ET, M58WR064EB Quadruple Enhanced Factory Program Pseudo Code quad_efp_command(addressFlow,dataFlow,n) /* n is the number of pages to be programmed.*/ /* Setup phase */ writeToFlash(addressFlow[0],0x75); for (i=0; i++; i< n){ /*Data Load Phase*/ /*First Data*/ writeToFlash(addressFlow[i],dataFlow[i,0]); /*at the first data of the first page, Quad-EFP may be aborted*/ if (First_Page) { status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block er- ror*/ error_handler(); /*2nd data*/ writeToFlash(addressFlow[i],dataFlow[i,1]); /*3rd data*/ writeToFlash(addressFlow[i],dataFlow[i,2]); /*4th data*/ writeToFlash(addressFlow[i],dataFlow[i,3]); /* Program&Verify Phase */ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ }while (status_register.SR0==1) /* Exit Phase */ writeToFlash(another_block_address,FFFFh); /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR1==1) /*program to protected block error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR4==1) /*program failure error*/ error_handler();

Table 40. Command Interface States - Modify Table, Next State tory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.

1. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data out-
2. The two cycle command should be issued to the same bank address.
3. If the P/E.C. is active, both cycles are ignored.
4. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.
5. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’.EFP and Quad EFP are busy if Block Address is

first EFP Address. Any other commands are treated as data.

Table 41. Command Interface States - Modify Table, Next Output tory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.

1. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data out-
2. The two cycle command should be issued to the same bank address.
3. If the P/E.C. is active, both cycles are ignored.
4. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.
5. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A

Table 42. Command Interface States - Lock Table, Next State tory Program, P/E. C. = Program/Erase Controller.

1. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’. EFP and Quad EFP are busy if Block Address is

first EFP Address. Any other commands are treated as data.

1. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.
2. If the P/E.C. is active, both cycles are ignored.
3. Illegal commands are those not defined in the command set.

Table 43. Command Interface States - Lock Table, Next Output tory Program, P/E. C. = Program/Erase Controller.

1. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.
2. If the P/E.C. is active, both cycles are ignored.
3. Illegal commands are those not defined in the command set.

M58WR064ET, M58WR064EB

REVISION HISTORY

Table 44. Document Revision History Automatic Standby mode added. Hexadecimal Code for Quadruple Word Program Setup modified. Double/Quadruple Word Program command descriptions modified. Exit Phase in the Quadruple Enhanced Factory Program command modified. and/or specified. Figures 4, 7, 12, 13, 15, 16, 17 and 23 modified. Figure 14 added. (revision version 02 equals 2.0). Revision history moved to end of document. Addresses modified in Table 5 and note to Figure 13, modified. Mode” and “Single Synchronous Read Mode” paragraphs clarified. 85ns Speed Class removed, 80ns Speed Class added. 70ns Speed Class characterized (certain timings modified). Document promoted from Product Preview to full Datasheet status. Command and Synchronous Burst Read Mode. waveform modified in Figure 11, Asynchronous Page Read AC Waveforms. tGLQV , tAVLH , tLLH in Table 20 and all the timings in Table 21 were modified. Data reserved at addresses 35h and 38h in Table 33, Device Geometry Definition.

M58WR064ET, M58WR064EB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.