M58WR016KU STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Features

■ Supply voltage –V DD = 1.7 V to 2 V for Program, Erase and Read –V DDQ = 1.7 V to 2 V for I/O buffers –V PP = 9 V for fast Program ■ Multiplexed address/data ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 86 MHz – Random access: 60 ns, 70 ns ■ Synchronous Burst Read Suspend ■ Programming time – 10 µs by word typical for Factory Program – Double/Quadruple Word Program option – Enhanced Factory Program options ■ Memory blocks – Multiple Bank memory array: 4 Mbit Banks – Parameter Blocks (top or bottom location) ■ Dual operations – Program Erase in one Bank while Read in others – No delay between Read and Write operations ■ Block locking – All blocks locked at Power up – Any combination of blocks can be locked –W P for Block Lock-Down ■ Security – 128 bit user programmable OTP cells – 64 bit unique device number ■ Common Flash Interface (CFI) ■ 100 000 program/erase cycles per block ■ Electronic signature – Manufacturer Code: 20h – Top device code, M58WR016KU: 8823h M58WR032KU: 8828h – Bottom device code, M58WR016KL: 8824h M58WR032KL: 8829h ■ ECOPACK® packages available VFBGA44 (ZA) 7.5 × 5 mm FBGA

Description M58WRxxxKU, M58WRxxxKL

1 Description

The M58WR016KU/L and M58WR032KU/L are 16-Mbit (1 Mbit ×16) and 32- Mbit (2 Mbit ×16) non-volatile Flash memories, respectively. In the rest of the document, they will be referred to as M58WRxxxKU/L unless otherwise specified. The M58WRxxxKU/L may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 V to 2 V VDD supply for the circuitry and a 1.7 V to 2 V VDDQ supply for the Input/Output pins. An optional 9 V VPP power supply is provided to speed up customer programming. The first sixteen address lines are multiplexed with the Data Input/Output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines, A16-Amax, are the Most Significant Bit addresses. The device features an asymmetrical block architecture:

  • the M58WR016KU/L have an array of 39 blocks, and are divided into 4 Mbit banks. There are 3 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords.
  • the M58WR032KU/L have an array of 71 blocks, and are divided into 4 Mbit banks. There are 7 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The Parameter Blocks are located at the top of the memory address space for the M58WR016KU and M58WR032KU, and at the bottom for the M58WR016KL and M58WR032KL. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage V DD . There are two Enhanced Factory programming commands available to speed up programming. Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 86 MHz. The synchronous burst read operation can be suspended and resumed.

M58WRxxxKU, M58WRxxxKL Description The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value IDD4 and the outputs are still driven. The M58WRxxxKU/L features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V PP ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at Power-Up. The device includes a Protection Register to increase the protection of a system’s design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. The memory is available in a VFBGA44 7.5 × 5 mm, 10 × 4 active ball array, 0.5 mm pitch package. It is supplied with all the bits erased (set to ’1’).

Figure 1. Logic diagram

  1. Amax is equal to A19 in the M58WR016KU/L and, to A20 in the M58WR032KU/L.

Table 1. Signal names

  1. Amax is equal to A19 in the M58WR016KU/L and, to A20 in the M58WR032KU/L.

Figure 2. VFBGA44 connections (top view through package) Note1: Ball D5 is A20 in the M58WR032KU/L, it is Not Connected internally (NC) in the M58WR016KU/L.

2 Package mechanical

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 3. VFBGA44 7.5 × 5 mm, 10 × 4 ball array, 0.50 mm pitch, bottom view

Table 2. VFBGA44 7.5 × 5 mm, 10 × 4 ball array, 0.50mm pitch, package

3 Part numbering

Devices are shipped from the factory with the memory content bits erased to ’1’. Table 3. Ordering information scheme

4 Revision history

Table 4. Document revision history 30-Jan-2007 1 Initial release.