M58WR016QB

M58WR016QT NUMONYX | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 110

Technical content

Datasheet sections

• 1 Summary description
• 2 Signal descriptions
• 2.1 Address Inputs (A0-Amax)
• 2.2 Data Input/Output (DQ0-DQ15)
• 2.3 Chip Enable (E )
• 2.4 Output Enable (G )
• 2.5 Write Enable (W )
• 2.6 Write Protect (WP )
• 2.7 Reset (RP )
• 2.8 Latch Enable (L )
• 2.9 Clock (K)
• 2.10 Wait (WAIT)
• 2.12 V DDQ supply voltage
• 2.13 V PP Program supply voltage
• 2.14 V SS Ground
• 2.15 V SSQ Ground
• 3 Bus operations
• 3.1 Bus Read
• 3.2 Bus Write
• 3.3 Address Latch
• 3.4 Output Disable
• 3.5 Standby
• 3.6 Reset
• 4 Command interface
• 5 Command interface - standard commands
• 5.1 Read Array command
• 5.2 Read Status Register command

Datasheet sections

• 7.0.7 Block Protection Status Bit (SR1)
• 7.0.8 Bank Write/Multiple Word Program Status Bit (SR0)
• 8 Configuration Register
• 8.1 Read Select Bit (CR15)
• 8.2 X-Latency Bits (CR13-CR11)
• 8.3 Wait Polarity Bit (CR10)
• 8.4 Data Output Configuration Bit (CR9)
• 8.5 Wait Configuration Bit (CR8)
• 8.6 Burst Type Bit (CR7)
• 8.7 Valid Clock Edge Bit (CR6)
• 8.8 Wrap Burst Bit (CR3)
• 8.9 Burst length Bits (CR2-CR0)
• 9 Read modes
• 9.1 Asynchronous Read mode
• 9.2 Synchronous Burst Read mode
• 9.2.1 Synchronous Burst Read Suspend
• 9.3 Single Synchronous Read mode
• 10 Dual operations and Multiple Bank architectu re
• 11 Block locking
• 11.1 Reading a Block’s lock status
• 11.2 Locked state
• 11.3 Unlocked state
• 11.4 Lock-Down state
• 11.5 Locking operations during Erase Suspend
• 12 Program and erase times and endurance cycles
• 13 Maximum rating
• 14 DC and AC parameters
• 15 Package mechanical

16 Mbit and 32 Mbit (x16, Multiple Bank, Burst)

1.8V supply Flash memories Feature summary ■ Supply voltage –V DD = 1.7V to 2V for Program, Erase and Read –V DDQ = 1.7V to 2.24V for I/O Buffers –V PP = 12V for fast Program (optional) ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 66MHz – Asynchronous/ Synchronous Page Read mode – Random access: 60ns, 70ns, 80ns ■ Synchronous Burst Read Suspend ■ Programming time – 8µs by Word typical for Fast Factory Program – Double/Quadruple Word Program option – Enhanced Factory Program options ■ Memory blocks – Multiple Bank memory array: 4 Mbit Banks – Parameter blocks (top or bottom location) ■ Dual operations – Program Erase in one bank while Read in others – No delay between Read and Write operations ■ Block locking – All blocks locked at Power up – Any combination of blocks can be locked –W P for Block Lock-Down ■ Security – 128 bit user programmable OTP cells – 64 bit unique device number ■ Common Flash Interface (CFI) ■ 100,000 program/erase cycles per block ■ Electronic signature – Manufacturer Code: 20h – Device Codes: M58WR016QT (Top): 8812h. M58WR016QB (Bottom): 8813h M58WR032QT (Top): 8814h M58WR032QB (Bottom): 8815h ■ ECOPACK® package available FBGA VFBGA56 (ZB) 7.7 x 9 mm www.numonyx.com

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Contents

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Contents

Table 26. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, package mechanical

Summary description M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB

1 Summary description

The M58WR016QT/B and M58WR032QT/B are 16 Mbit (1 Mbit x16) and 32 Mbit (2 Mbit x16) non-volatile Flash memories, respectively. They will be referred to as M58WRxxxQT/B throughout the document unless otherwise specified. The M58WRxxxQT/B may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.7V to 2V VDD supply for the circuitry and a 1.7V to 2.24V VDDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to speed up customer programming. The VPP pin can also be used as a control pin to provide absolute protection against program or erase. The device features an asymmetrical block architecture.

• M58WR016QT/B has an array of 39 blocks, and is divided into 4 Mbit banks. There are 3 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords.
• M58WR032QT/B has an array of 71 blocks, and is divided into 4 Mbit banks. There are 7 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architectures are summarized in Table 2 and Table 3, and the memory maps are shown in Figure 3 and Figure 4. The Parameter Blocks are located at the top of the memory address space for the M58WR016QT and M58WR032QT, and at the bottom for the M58WR016QB and M58WR032QB. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage V DD. There are two Enhanced Factory programming commands available to speed up programming. Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 66MHz. The synchronous burst read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value I DD4 and the outputs are still driven. The M58WRxxxQT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Summary description preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at Power- Up. The device includes a Protection Register to increase the protection of a system’s design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by Numonyx, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. Figure 5 shows the Protection Register Memory Map. The memory is offered in a VFBGA56, 7.7 x 9mm, 8x7 active ball array, 0.75 mm pitch package and is supplied with all the bits erased (set to ’1’). In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.

Figure 1. Logic Diagram

1. Amax is equal to A19 for the M58WR0 16QT/B and to A20 for the M58WR032QT/B.

Table 1. Signal names

1. Amax is equal to A19 for the M58WR0 16QT/B and to A20 for the M58WR032QT/B.

Figure 2. VFBGA Connections (Top view through package)

1. Ball B3 is A20 in the M58WR032QT/B and it is Not Connected internally (NC) in the M58WR016QT/B.

Table 2. M58WR016QT/B Bank architecture

Figure 3. M58WR016QT/B memory map Table 3. M58WR032QT/B Bank architecture

8 Main

32 KWord00000h

32 KWord38000h

32 KWord40000h

32 KWord78000h

32 KWord80000h

32 KWordB8000h

32 KWordC0000h

32 KWordF0000h

4 KWordF8000h

4 KWordFF000h

8 Parameter

4 KWord00000h

32 KWord08000h

32 KWordF8000h

7 Main

Figure 4. M58WR032QT/B memory map

32 KWord000000h

32 KWord038000h

32 KWord100000h

32 KWord138000h

32 KWord140000h

32 KWord178000h

32 KWord180000h

32 KWord1B8000h

32 KWord1C0000h

32 KWord1F0000h

4 KWord1F8000h

4 KWord1FF000h

4 KWord000000h

32 KWord008000h

32 KWord040000h

32 KWord078000h

32 KWord080000h

32 KWord0B8000h

32 KWord0C0000h

32 KWord0F8000h

32 KWord1F8000h

Signal descriptions M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB

2 Signal descriptions

See Figure 1: Logic Diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.

2.1 Address Inputs (A0-Amax)

Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

2.2 Data Input/Output (DQ0-DQ15)

The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Bus Write operation.

2.3 Chip Enable (E )

The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V ILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level.

2.4 Output Enable (G )

The Output Enable controls data outputs during the Bus Read operation of the memory.

2.5 Write Enable (W )

The Write Enable controls the Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.

2.6 Write Protect (WP )

Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V IL, the Lock-Down is enabled and the protection status of the Locked- Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 14: Lock status).

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Signal descriptions

2.7 Reset (RP )

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current I DD2. Refer to Table 19: DC characteristics - currents for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to V RPH (refer to Table 20: DC characteristics - voltages).

2.8 Latch Enable (L )

Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.

2.9 Clock (K)

The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at V IL. Clock is don't care during asynchronous read and in write operations.

2.10 Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at V IH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAIT signal is not gated by Output Enable.

2.11 V DD supply voltage

VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase).

2.12 V DDQ supply voltage

VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply.

Signal descriptions M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB

2.13 V PP Program supply voltage

VPP is a power supply pin. The Supply Voltage VDD and the Program Supply Voltage VPP can be applied in any order. The pin can also be used as a control input. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP in the VPP1 range enables these functions (see Tables 19 and 20, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed.

2.14 V SS Ground

VSS ground is the reference for the core supply. It must be connected to the system ground.

2.15 V SSQ Ground

VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS. Note: Each device in a system should have V DD, VDDQ and VPP decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 9: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Bus operations

3 Bus operations

There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 4: Bus operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations.

3.1 Bus Read

Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at V IL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 10, 11, 12 and 13 Read AC Waveforms, and Tables 21 and 22 Read AC Characteristics, for details of when the output becomes valid.

3.2 Bus Write

Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the write operation by toggling Latch Enable. In this case the Latch Enable should be tied to V IH during the bus write operation. See Figures 16 and 17, Write AC Waveforms, and Tables 23 and 24, Write AC Characteristics, for details of the timing requirements.

3.3 Address Latch

Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at V IL during address latch operations. The addresses are latched on the rising edge of Latch Enable.

3.4 Output Disable

The outputs are high impedance when the Output Enable is at VIH.

3.5 Standby

3.6 Reset

Table 4. Bus operations (1)

1. WAIT signal polarity is configured us ing the Set Configuration Register command.
2. L can be tied to VIH if the valid address has been previously latched.

4 Command interface

All Bus Write operations to the memory are interpreted by the Command Interface. whose output may be read at any time to monitor the progress or the result of the operation. DD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will be ignored. Interface States - Modify and Lock Tables, for a summary of the Command Interface. Table 5. Command codes

Command interface - standard commands M58WR016QT, M58WR016QB, M58WR032QT,

5 Command interface - standard commands

The following commands are the basic commands used to read, write to and configure the device. Refer to Table 6: Standard commands, in conjunction with the following text descriptions.

5.1 Read Array command

The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command and return the addressed bank to Read Array mode. Subsequent read operations will read the addressed location and output the data. A Read Array command can be issued in one bank while programming or erasing in another bank. However if a Read Array command is issued to a bank currently executing a Program or Erase operation the command will be executed but the output data is not guaranteed.

5.2 Read Status Register command

The Status Register indicates when a Program or Erase operation is complete and the success or failure of operation itself. Issue a Read Status Register command to read the Status Register content. The Read Status Register command can be issued at any time, even during Program or Erase operations. The following read operations output the content of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G returns to VIH. Either E or G must be toggled to update the latched data. See Table 9 for the description of the Status Register Bits. This mode supports asynchronous or single synchronous reads only.

5.3 Read Electronic Signature command

The Read Electronic Signature command reads the Manufacturer and Device Codes, the Block Locking Status, the Protection Register, and the Configuration Register. The Read Electronic Signature command consists of one write cycle to an address within one of the banks. A subsequent Read operation in the same bank will output the Manufacturer Code, the Device Code, the protection Status of the blocks in the targeted bank, the Protection Register, or the Configuration Register (see Table 7). If a Read Electronic Signature command is issued in a bank that is executing a Program or Erase operation the bank will go into Read Electronic Signature mode, subsequent Bus Read cycles will output the Electronic Signature data and the Program/Erase controller will continue to program or erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - standard com-

5.4 Read CFI Query command

The Read CFI Query command is used to read data from the Common Flash Interface (CFI). The Read CFI Query Command consists of one Bus Write cycle, to an address within one of the banks. Once the command is issued subsequent Bus Read operations in the same bank read from the Common Flash Interface. If a Read CFI Query command is issued in a bank that is executing a Program or Erase operation the bank will go into Read CFI Query mode, subsequent Bus Read cycles will output the CFI data and the Program/Erase controller will continue to Program or Erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads. The status of the other banks is not affected by the command (see Table 12). After issuing a Read CFI Query command, a Read Array command should be issued to the addressed bank to return the bank to Read Array mode. See Appendix B, Tables 33, 34, 35, 36, 37, 38, 39, 40, 41 and 42 for details on the information contained in the Common Flash Interface memory area.

5.5 Clear Status Register command

The Clear Status Register command can be used to reset (set to ‘0’) error bits SR1, SR3, SR4 and SR5 in the Status Register. One bus write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not change the Read mode of the bank. The error bits in the Status Register do not automatically return to ‘0’ when a new command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command.

Command interface - standard commands M58WR016QT, M58WR016QB, M58WR032QT,

5.6 Block Erase command

The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. The Block Erase command can be issued at any moment, regardless of whether the block has been programmed or not. Two Bus Write cycles are required to issue the command.

• The first bus cycle sets up the Erase command.
• The second latches the block address in the internal state machine and starts the Program/Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued. During Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 15: Program/Erase times and endurance cycles. See Appendix C, Figure 24: Block Erase flowchart and pseudo code, for a suggested flowchart for using the Block Erase command.

5.7 Program command

The memory array can be programmed Word-by-Word. Only one Word in one bank can be programmed at any one time. If the block is protected, the program operation will abort, the data in the block will not be changed and the Status Register will output the error. Two bus write cycles are required to issue the Program Command.

• The first bus cycle sets up the Program command.
• The second latches the Address and the Data to be written and starts the Program/Erase Controller. After programming has started, read operations in the bank being programmed output the Status Register content. During Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 15: Program/Erase times and endurance cycles. Programming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. See Appendix C, Figure 20: Program flowchart and pseudo code, for the flowchart for using the Program command.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - standard com-

5.8 Program/Erase Suspend command

The Program/Erase Suspend command is used to pause a Program or Block Erase operation. A Bank Erase operation cannot be suspended. One bus write cycle is required to issue the Program/Erase command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to ‘1’. The command can be addressed to any bank. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array (cannot read the erase-suspended block or the program-suspended Word), Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Clear status Register, Program, Block Lock, Block Lock-Down or Block Unlock commands will also be accepted. The block being erased may be protected by issuing the Block Lock, Block Lock-Down or Protection Register Program commands. Only the blocks not being erased may be read or programmed correctly. When the Program/Erase Resume command is issued the operation will complete. Refer to the Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to V IH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 23: Program Suspend & Resume flowchart and pseudo code, and Figure 25: Erase Suspend & Resume flowchart and pseudo code for flowcharts for using the Program/Erase Suspend command.

5.9 Program/Erase Resume command

The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command can be written to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. If the bank was in Read Array mode subsequent read operations will output invalid data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the programming operation has completed. It is possible to accumulate suspend operations. For example: suspend an erase operation, start a programming operation, suspend the programming operation then read the array. See Appendix C, Figure 23: Program Suspend & Resume flowchart and pseudo code, and Figure 25: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using the Program/Erase Resume command.

Command interface - standard commands M58WR016QT, M58WR016QB, M58WR032QT,

5.10 Protection Register Program command

The Protection Register Program command is used to Program the 128 bit user One-Time- Programmable (OTP) segment of the Protection Register and the Protection Register Lock. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protection Register Program command.

• The first bus cycle sets up the Protection Register Program command.
• The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 5: Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register is not reversible. The Protection Register Program cannot be suspended. See Appendix C, Figure 27: Protection Register Program flowchart and pseudo code, for a flowchart for using the Protection Register Program command.

5.11 Set Configuration Register command

The Set Configuration Register command is used to write a new value to the Configuration Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Configuration Register command.

• The first cycle writes the setup command and the address corresponding to the Configuration Register content.
• The second cycle writes the Configuration Register data and the confirm command. Read operations output the memory array content after the Set Configuration Register command is issued. The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1 on A1, etc.; the other address bits are ignored.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - standard com-

5.12 Block Lock command

The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command.

• The first bus cycle sets up the Block Lock command.
• The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 14 shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or power- down/power-up. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix C, Figure 26: Locking operations flowchart and pseudo code, for a flowchart for using the Lock command.

5.13 Block Unlock command

The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command.

• The first bus cycle sets up the Block Unlock command.
• The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 14 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 26: Locking operations flowchart and pseudo code, for a flowchart for using the Unlock command.

5.14 Block Lock-Down command

A locked or unlocked block can be locked-down by issuing the Block Lock-Down command. A locked-down block cannot be programmed or erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command.

• The first bus cycle sets up the Block Lock command.
• The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 14 shows the Lock Status after issuing a Block Lock- Down command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 26: Locking operations flowchart and pseudo code, for a flowchart for using the Lock-Down command.

Table 6. Standard commands (1)

1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data,
2. Must be same bank as in the first cyc le. The signature addresses are listed in Table 7.
3. Any address within the bank can be used.

Figure 5. Protection Register Memory Map Table 7. Electronic signature codes

1. CR = Configuration Register.

Command interface - factory program commands M58WR016QT, M58WR016QB, M58WR032QT,

6 Command interface - factory program commands

The Factory Program commands are used to speed up programming. They require VPP to be at VPPH except for the Bank Erase command which also operates at VPP = VDD. Refer to Table 8: Factory Program commands, in conjunction with the following text descriptions. The use of Factory Program commands requires certain operating conditions.

• VPP must be set to VPPH (except for Bank Erase comand),
• VDD must be within operating range,
• Ambient temperature, TA must be 25°C ± 5°C,
• The targeted block must be unlocked.

6.1 Bank Erase command

The Bank Erase command can be used to erase a bank. It sets all the bits within the selected bank to ’1’. All previous data in the bank is lost. The Bank Erase command will ignore any protected blocks within the bank. If all blocks in the bank are protected then the Bank Erase operation will abort and the data in the bank will not be changed. The Status Register will not output any error. Bank Erase operations can be performed at both V PP = VPPH and VPP = VDD. Two Bus Write cycles are required to issue the command.

• The first bus cycle sets up the Bank Erase command.
• The second latches the bank address in the internal state machine and starts the Program/Erase Controller. If the second bus cycle is not Write Bank Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to V IL. As data integrity cannot be guaranteed when the Erase operation is aborted, the bank must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued. During Bank Erase operations the bank being erased will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. For optimum performance, Bank Erase commands should be limited to a maximum of 100 Program/Erase cycles per Block. After 100 Program/Erase cycles the internal algorithm will still operate properly but some degradation in performance may occur. Dual Operations are not supported during Bank Erase operations and the command cannot be suspended. Typical Erase times are given in Table 15: Program/Erase times and endurance cycles.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - factory pro-

6.2 Double Word Program command

The Double Word Program command improves the programming throughput by writing a page of two adjacent words in parallel. The two words must differ only for the address A0. If the block is protected, the Double Word Program operation will abort, the data in the block will not be changed and the Status Register will output the error. Three bus write cycles are necessary to issue the Double Word Program command.

• The first bus cycle sets up the Double Word Program Command.
• The second bus cycle latches the Address and the Data of the first word to be written.
• The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations in the bank being programmed output the Status Register content after the programming has started. During Double Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Double Word Program operations and the command cannot be suspended. Typical Program times are given in Table 15: Program/Erase times and endurance cycles. Programming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. See Appendix C, Figure 21: Double Word Program flowchart and pseudo code, for the flowchart for using the Double Word Program command.

Command interface - factory program commands M58WR016QT, M58WR016QB, M58WR032QT,

6.3 Quadruple Word Program command

The Quadruple Word Program command improves the programming throughput by writing a page of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. If the block is protected, the Quadruple Word Program operation will abort, the data in the block will not be changed and the Status Register will output the error. Five bus write cycles are necessary to issue the Quadruple Word Program command.

• The first bus cycle sets up the Double Word Program Command.
• The second bus cycle latches the Address and the Data of the first word to be written.
• The third bus cycle latches the Address and the Data of the second word to be written.
• The fourth bus cycle latches the Address and the Data of the third word to be written.
• The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. During Quadruple Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Quadruple Word Program operations and the command cannot be suspended. Typical Program times are given in Table 15: Program/Erase times and endurance cycles. See Appendix C, Figure 22: Quadruple Word Program flowchart and pseudo code, for the flowchart for using the Quadruple Word Program command.

6.4 Enhanced Factory Program command

The Enhanced Factory Program command can be used to program large streams of data within any one block. It greatly reduces the total programming time when a large number of Words are written to a block at any one time. Dual operations are not supported during the Enhanced Factory Program operation and the command cannot be suspended. For optimum performance the Enhanced Factory Program commands should be limited to a maximum of 10 program/erase cycles per block. If this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical Program times are given in Table 15. If the block is protected, the Enhanced Factory Program operation will abort, the data in the block will not be changed and the Status Register will output the error. The Enhanced Factory Program command has four phases: the Setup Phase, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary and the Exit Phase. Refer to Table 8: Factory Program commands, and Figure 28: Enhanced Factory Program flowchart.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - factory pro-

6.4.1 Setup Phase

The Enhanced Factory Program command requires two Bus Write operations to initiate the command.

• The first bus cycle sets up the Enhanced Factory Program command.
• The second bus cycle confirms the command. the confirm command is issued, read operations output the Status Register data. The read Status Register command must not be issued as it will be interpreted as data to program.

6.4.2 Program Phase

The Program Phase requires n+1 cycles, where n is the number of Words (refer to Table 8: Factory Program commands, and Figure 28: Enhanced Factory Program flowchart). Three successive steps are required to issue and execute the Program Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address can either remain the Start Address, in which case the P/E.C. increments the address location or the address can be incremented in which case the P/E.C. jumps to the new address. If any address that is not in the same block as the Start Address is given with data FFFFh, the Program Phase terminates and the Verify Phase begins. The Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the programming phase. If the data is not FFFFh, the command is ignored. The memory is now set to enter the Verify Phase.

Command interface - factory program commands M58WR016QT, M58WR016QB, M58WR032QT,

6.4.3 Verify Phase

The Verify Phase is similar to the Program Phase in that all Words must be resent to the memory for them to be checked against the programmed data. The Program/Erase Controller checks the stream of data with the data that was programmed in the Program Phase and reprograms the memory location if necessary. Three successive steps are required to execute the Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word, to be verified. The Status Register bit SR0 should be read to check that the Program/Erase Controller is ready for the next Word. 2. Each subsequent Word to be verified is latched with a new Bus Write operation. The Words must be written in the same order as in the Program Phase. The address can remain the Start Address or be incremented. If any address that is not in the same block as the Start Address is given with data FFFFh, the Verify Phase terminates. Status Register bit SR0 should be read to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been verified, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Verify Phase. If the Verify Phase is successfully completed the memory remains in Read Status Register mode. If the Program/Erase Controller fails to reprogram a given location, the error will be signaled in the Status Register.

6.4.4 Exit Phase

Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has returned to Read mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details.

6.5 Quadruple Enhanced Factory Program command

The Quadruple Enhanced Factory Program command can be used to program one or more pages of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. Dual operations are not supported during Quadruple Enhanced Factory Program operations and the command cannot be suspended. If the block is protected, the Quadruple Enhanced Factory Program operation will abort, the data in the block will not be changed and the Status Register will output the error. The Quadruple Enhanced Factory Program command has four phases: the Setup Phase, the Load Phase where the data is loaded into the buffer, the combined Program and Verify Phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the Exit Phase. Unlike the Enhanced Factory Program it is not necessary to resubmit the data for the Verify Phase. The Load Phase and the Program and Verify Phase can be repeated to program any number of pages within the block.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Command interface - factory pro-

6.5.1 Setup Phase

The Quadruple Enhanced Factory Program command requires one Bus Write operation to initiate the load phase. After the setup command is issued, read operations output the Status Register data. The Read Status Register command must not be issued as it will be interpreted as data to program.

6.5.2 Load Phase

The Load Phase requires 4 cycles to load the data (refer to Table 8: Factory Program commands, and Figure 29: Quadruple Enhanced Factory Program flowchart). Once the first Word of each Page is written it is impossible to exit the Load phase until all four Words have been written. Two successive steps are required to issue and execute the Load Phase of the Quadruple Enhanced Factory Program command. 1. Use one Bus Write operation to latch the Start Address and the first Word of the first Page to be programmed. For subsequent Pages the first Word address can remain the Start Address (in which case the next Page is programmed) or can be any address in the same block. If any address with data FFFFh is given that is not in the same block as the Start Address, the device enters the Exit Phase. For the first Load Phase Status Register bit SR7 should be read after the first Word has been issued to check that the command has been accepted (bit SR7 set to ‘0’). This check is not required for subsequent Load Phases. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address is only checked for the first Word of each Page as the order of the Words to be programmed is fixed. The memory is now set to enter the Program and Verify Phase.

6.5.3 Program and Verify Phase

In the Program and Verify Phase the four Words that were loaded in the Load Phase are programmed in the memory array and then verified by the Program/Erase Controller. If any errors are found the Program/Erase Controller reprograms the location. During this phase the Status Register shows that the Program/Erase Controller is busy, Status Register bit SR7 set to ‘0’, and that the device is not waiting for new data, Status Register bit SR0 set to ‘1’. When Status Register bit SR0 is set to ‘0’ the Program and Verify phase has terminated. Once the Verify Phase has successfully completed subsequent pages in the same block can be loaded and programmed. The device returns to the beginning of the Load Phase by issuing one Bus Write operation to latch the Address and the first of the four new Words to be programmed.

6.5.4 Exit Phase

Finally, after all the pages have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Load and Program and Verify Phases. Status Register bit SR7 set to ‘1’ and bit SR0 set to ‘0’ indicate that the Quadruple Enhanced Factory Program command has terminated. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details.

signaled in the Status Register. Table 8. Factory Program commands (1)

1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address.
2. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0.
3. Any address within the bank can be used.
4. Word Addresses 1,2,3 and 4 must be consecut ive Addresses differing only for A0 and A1.
5. A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register

and check that the memory is ready to accept the next data. n = number of Words, i = number of Pages to be programmed.

1. Any address within the block can be used.
2. WA1 is the Start Address. NOT WA1 is any add ress that is not in the same block as WA1.
3. Address can remain Starting Address WA1 or be incremented.
4. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so

subsequent Words in each Page can be written to any address.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Status Register

7 Status Register

The Status Register provides information on the current or previous Program or Erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to V IH. The Status Register can only be read using single asynchronous or single synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during Program and Erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the addressed bank. The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to Table 9 in conjunction with the following text descriptions.

7.0.1 Program/Erase Cont roller Status Bit (SR7)

The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, operations the Program/Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, V PP Status and Block Lock Status bits should be tested for errors.

7.0.2 Erase Suspend Status Bit (SR6)

The Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be suspended in the addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR7 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low.

Status Register M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB

7.0.3 Erase Status Bit (SR5)

The Erase Status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

7.0.4 Program Status Bit (SR4)

The Program Status bit is used to identify a Program failure or an attempt to program a ‘1’ to an already programmed bit when VPP = VPPH. When the Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. After an attempt to program a '1' to an already programmed bit, the Program Status bit SR4 only goes High (set to '1') if VPP = VPPH (if VPP is different from VPPH, SR4 remains Low (set to '0') and the attempt is not shown). The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.

7.0.5 V PP Status Bit (SR3)

The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the VPP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Status Register

7.0.6 Program Suspend Status Bit (SR2)

The Program Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low.

7.0.7 Block Protecti on Status Bit (SR1)

The Block Protection Status bit can be used to identify if a Program or Block Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to ‘1’), a Program or Erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.

7.0.8 Bank Write/Multiple Wo rd Program Status Bit (SR0)

The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Enhanced Factory Program mode the Multiple Word Program bit shows if a Word has finished programming or verifying depending on the phase. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to ‘0’). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to ‘0’), the addressed bank is executing a Program or Erase operation. When the Program/Erase Controller Status bit is Low (set to ‘0’) and the Bank Write Status bit is High (set to ‘1’), a Program or Erase operation is being executed in a bank other than the one being addressed. In Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to ‘0’), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to ‘1’) the device is not ready for the next Word. Note: Refer to Appendix C: Flowcharts and pseudo codes, for using the Status Register.

Table 9. Status Register bits

1. Logic level '1' is High, '0' is Low.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Configuration Register

8 Configuration Register

The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power- Up the device is configured for asynchronous page read (CR15 = 1). The Configuration Register bits are described in Table 10. They specify the selection of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 6 and 7 for examples of synchronous burst configurations.

8.1 Read Select Bit (CR15)

The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to’1’ for asynchronous access.

8.2 X-Latency Bits (CR13-CR11)

The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 10: Configuration Register bits. The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: 1. Depending on whether t AVK_CPU or tDELAY is supplied either one of the following two equations must be satisfied: (n + 1) tK ≥ tACC - tAVK_CPU + tQVK_CPU (n + 2) tK ≥ tACC + tDELAY + tQVK_CPU 2. and also tK > tKQV + tQVK_CPU where:

• n is the chosen X-Latency configuration code
• tK is the clock period
• tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last
• tDELAY is address valid, L Low, or E Low to clock, whichever occurs last
• tQVK_CPU is the data setup time required by the system CPU,
• tKQV is the clock to data valid time
• tACC is the random access time of the device. Refer to Figure 6: X-Latency and data output configuration example.

Configuration Register M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB

8.3 Wait Polarity Bit (CR10)

In synchronous burst mode the Wait signal indicates whether the output data are valid or a WAIT state must be inserted. The Wait Polarity bit is used to set the polarity of the Wait signal. When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait Polarity bit is set to ‘1’ the Wait signal is active High (default).

8.4 Data Output Configuration Bit (CR9)

The Data Output Configuration bit determines whether the output remains valid for one or two clock cycles. When the Data Output Configuration Bit is ’0’ the output data is valid for one clock cycle, when the Data Output Configuration Bit is ’1’ the output data is valid for two clock cycles. The Data Output Configuration depends on the condition:

• tK > tKQV + tQVK_CPU where tK is the clock period, tQVK_CPU is the data setup time required by the system CPU and tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 6: X-Latency and data output configuration example.

8.5 Wait Configuration Bit (CR8)

In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When WAIT is asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid. When the Wait bit is ’0’ the Wait output pin is asserted during the wait state. When the Wait bit is ’1’ (default) the Wait output pin is asserted one clock cycle before the wait state.

8.6 Burst Type Bit (CR7)

The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses; when the Burst Type bit is ’1’ (default) the memory outputs from sequential addresses. See Table 11: Burst type definition, for the sequence of addresses output from a given starting address in each mode.

8.7 Valid Clock Edge Bit (CR6)

The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock is active.

8.8 Wrap Burst Bit (CR3)

The burst reads can be confined inside the 4 or 8 Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Configuration Register the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not wrap.

8.9 Burst length Bits (CR2-CR0)

The Burst Length bits set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8, 16 Words no-wrap, depending on the starting address, the device asserts the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 Word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 16 Word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 11: Burst type definition. CR14, CR5 and CR4 are reserved for future use.

Table 10. Configuration Register bits

0 Synchronous Read

1 Asynchronous Read (Default at power-on)

111 Reserved (default)

0 WAIT is active Low

1 WAIT is active high (default)

0 Data held for one clock cycle

1 Data held for two clock cycles (default)

0 WAIT is active during wait state

1 WAIT is active one data cycle before wait state (default)

0 Interleaved

1 Sequential (default)

0 Falling Clock edge

1 Rising Clock edge (default)

1 No Wrap (default)

111 Continuous (CR7 must be set to ‘1’) (default)

Table 11. Burst type definition

4 Words 8 Words 16 Words Continuous

Figure 6. X-Latency and data output configuration example Table 11. Burst type definition (continued) Notes: 1. Settings shown: X-latency = 4, Data Output held for one clock cycle.

1. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.

Figure 7. Wait configuration example Note: Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.

Read modes M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB

9 Read modes

Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is Asynchronous; if the data output is synchronized with clock, the read operation is Synchronous. The Read mode and data output format are determined by the Configuration Register. (See Configuration Register section for details). All banks supports both asynchronous and synchronous read operations. The Multiple Bank architecture allows read operations in one bank, while write operations are being executed in another (see Tables 12 and 13).

9.1 Asynchronous Read mode

In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for Asynchronous operations. In Asynchronous Read mode a Page of data is internally read and stored in a Page Buffer. The Page has a size of 4 Words and is addressed by A0 and A1 address inputs. The address inputs A0 and A1 are not gated by Latch Enable in Asynchronous Read mode. The first read operation within the Page has a longer access time (T acc, Random access time), subsequent reads within the same Page have much shorter access times. If the Page changes then the normal, longer timings apply again. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. During Asynchronous Read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, the WAIT signal is always asserted. See Table 21: Asynchronous Read AC characteristics, Figure 10: Asynchronous Random Access Read AC waveforms, and Figure 11: Asynchronous Page Read AC waveforms for details.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Read modes

9.2 Synchronous Burst Read mode

In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence is started at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and after a delay of 2 to 5 clock cycles (X latency bits CR13-CR11) the corresponding data are output on each clock cycle. The number of Words to be output during a Synchronous Burst Read operation can be configured as 4, 8, 16 Words, or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Burst Type and the Wrap Burst bits in the Configuration Register. The burst sequence may be configured to be sequential or interleaved (CR7). The burst reads can be confined inside the 4, 8 or 16 Word boundary (Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to the Burst Length (4, 8 or 16 Words) the wrapped configuration has no impact on the output sequence. Interleaved mode is not allowed in Continuous Burst Read mode or with No Wrap sequences. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 16 Word boundary and the starting address was at the end of a four word boundary. WAIT is asserted during X latency, the Wait state and at the end of 4-, 8- or 16-Word burst. It is only deasserted when output data are valid. In Continuous Burst Read mode a Wait state will occur when crossing the first 16 Word boundary. If the burst starting address is aligned to a 4 Word Page, the Wait state will not occur. The WAIT signal can be configured to be active Low or active High (default) by setting CR10 in the Configuration Register. The WAIT signal is meaningful only in Synchronous Burst Read mode, in other modes, WAIT is always asserted (except for Read Array mode). See Table 22: Synchronous Read AC characteristics, and Figure 12: Synchronous Burst Read AC waveforms, for details.

Read modes M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB

9.2.1 Synchronous Burst Read Suspend

A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) in which case the initial latency time can be reduced to zero, or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when E is low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The clock signal is then halted at V IH or at VIL, and G goes high. When G becomes low again and the clock signal restarts, the Synchronous Burst Read operation is resumed exactly where it stopped. WAIT being gated by E remains active and will not revert to high-impedance when G goes high. So if two or more devices are connected to the system’s READY signal, to prevent bus contention the WAIT signal of the Flash memory should not be directly connected to the system’s READY signal. See Table 22: Synchronous Read AC characteristics and Figure 14: Synchronous Burst Read Suspend AC waveforms, for details.

9.3 Single Synchronous Read mode

Single Synchronous Read operations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is always asserted. See Table 22: Synchronous Read AC characteristics and Figure 13: Single Synchronous Read AC waveforms, for details.

10 Dual operations and Multiple Bank architecture

from one bank while another bank is being programmed or erased. that read operations are possible at any moment. Tables 12 and 13 show the dual operations possible in other banks and in the same bank. Table 12. Dual operations allowed in other banks

Table 13. Dual operations allowed in same bank

1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase
2. Not allowed in the Block or Word that is being erased or programmed.

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Block locking

11 Block locking

The M58WRxxxQT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection.

• Lock/Unlock - this first level allows software-only control of block locking.
• Lock-Down - this second level requires hardware interaction before locking can be changed.
• VPP ≤ VPPLK - the third level offers a complete hardware protection against program and erase on all blocks. The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 14, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 26, shows a flowchart for the locking operations.

11.1 Reading a Block’s lock status

The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 7, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system.

11.2 Locked state

The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.

11.3 Unlocked state

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered- down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command.

Block locking M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB

11.4 Lock-Down state

Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. Locked-Down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP =1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is Low, blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was high. Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked state.

11.5 Locking operations during Erase Suspend

Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix Appendix D: Command interface state tables, for detailed information on which commands are valid during erase suspend.

Table 14. Lock status

1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for

a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL.

1. All blocks are locked at power-up, so the de fault configuration is 001 or 101 according to WP status.
2. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

12 Program and erase times and endurance cycles

condition. The best case is when all the bits in the block or bank are at ‘0’ (preprogrammed). The worst case is when all the bits in the block or bank are at ‘1’ (not preprogrammed). Usually, the system overhead is negligible with respect to the erase time. Table 15. Program/Erase times and endurance cycles (1)

1. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms).
2. Values are liable to change with the external system-level overhead (command sequence and Status

Register polling execution).

1. Measurements performed at 25°C. T A = 25°C ±5°C for Quadruple Word, Double Word and Quadruple

Table 15. Program/Erase times and endurance cycles (1) (continued)

13 Maximum rating

and other relevant quality documents. Table 16. Absolute maximum ratings

14 DC and AC parameters

Figure 8. AC measurement I/O waveform Table 17. Operating and AC measurement conditions Input and Output Timing Ref.

Figure 9. AC measurement load circuit Table 18. Capacitance (1)

1. Sampled only, not 100% tested.

Table 19. DC characteristics - currents

4 Word 7 16 mA

8 Word 10 18 mA

16 Word 12 22 mA

4 Word 8 17 mA

8 Word 11 20 mA

16 Word 14 25 mA

1. Sampled only, not 100% tested.
2. V DD Dual Operation current is the sum of read and program or erase currents.

Table 20. DC characteristics - voltages

Figure 10. Asynchronous Random Access Read AC waveforms Notes: 1. Write Enable, W, is High, WAIT is active Low.

1. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.

Figure 11. Asynchronous Page Read AC waveforms

1. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.

Table 21. Asynchronous Read AC characteristics

1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.

Figure 12. Synchronous Burst Read AC waveforms Notes 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.

1. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, K, can be configured as the active edge.

Here the active edge of K is the rising one.

1. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.

Figure 13. Single Synchronous Read AC waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.

1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. WAIT is always asserted when addressed bank is in Read CFI, Read SR or Read electronic signature mode.

WAIT signals valid data if the addressed bank is in Read Array mode.

1. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, K, can be configured as the active edge.

Here the active edge of K is the rising one.

1. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.

Figure 14. Synchronous Burst Read Suspend AC waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. The CLOCK signal can be held high or low
3. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge.

Here, the active edge is the rising one. Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.

Figure 15. Clock input AC waveform Table 22. Synchronous Read AC characteristics (1) (2)

1. Sampled only, not 100% tested.
2. For other timings please refer to Table 21: Asynchronous Read AC characteristics.

Figure 16. Write AC waveforms, Write Enable controlled Note: Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.

Table 23. Write AC characteristics, Write Enable controlled (1)

1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept low.
3. t WHEL has this value when reading from the targeted bank or when reading from any address after a Set

Configuration Register have been issued, tWHEL is 0ns.

Figure 17. Write AC waveforms, Chip Enable controlled Note: Amax is equal to A19 in the M58WR016QT/B and to A20 in the M58WR032QT/B.

Table 24. Write AC characteristics, Chip Enable controlled (1)

1. Sampled only, not 100% tested.
2. t WHEL has this value when reading from the targeted bank or when reading from any address after a Set

Configuration Register have been issued, tWHEL is 0ns.

Figure 18. Reset and Power-up AC waveforms Table 25. Reset and Power-up AC characteristics

1. The device Reset is possible but not guaranteed if t PLPH < 50ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP

in order to allow proper CPU initialization during Power-Up or Reset.

Figure 19. VFBGA56 - 7.7x9mm, 8x7 ball ar ray, 0.75mm pitch, Bottom View Package

16 Part numbering

Table 27. Ordering information scheme

device, please contact the Numonyx Sales Office nearest to you. Table 28. Daisy chain ordering scheme

Table 29. Top boot block addresses, M58WR016QT

1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;

Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 30. Bottom boot block addresses, M58WR016QB Table 29. Top boot block addresses, M58WR016QT (continued)

1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only;

Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 31. Top boot block addresses, M58WR032QT Table 30. Bottom boot block addresses, M58WR016QB (continued)

Table 31. Top boot block addresses, M58WR032QT (continued)

1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;

Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 32. Bottom boot block addresses, M58WR032QB

Table 32. Bottom boot block addresses, M58WR032QB (continued)

1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only;

Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank).

software to upgrade itself when necessary. lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0. been written by Numonyx. Issue a Read Array command to return to Read mode. Table 33. Query structure overview (1)

1. The Flash memory display the CFI data structure w hen CFI Query command is issued. In this table are

Table 34. CFI Query identification string

Table 35. CFI query system interface information

Table 36. Device geometry definition

1. Applies to M58WR016QT/B only.

2 MBytes

1. Applies to M58WR032QT/B only.

4 MBytes

Table 37. Primary algorithm-specific extended query table (P+5)h contains less significant byte.

Common Flash Interface M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Table 38. Protection Register Information (P+E)h = 47h 0001h Number of protection register fields in JEDEC ID space. Table 39. Burst Read information determine page-mode data output width. bit 0-2 if the device is configured for its maximum word width. (P+18)h = 51h 0007h Synchronous mode read capability configuration 4 Cont. Table 40. Bank and erase block region information (1) (2)

1. The variable P is a pointer which is defined at CFI offset 15h.
2. Bank Regions. There are two Bank Regions, see Table 29 and Table 30 for the M58WR016QT/B and see

Table 31 and Table 32 for the M58WR032QT/B.

Description

(P+19)h = 52h 02h (P+19)h = 52h 02h Number of Bank Regions within the device

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Common Flash Interface Table 41. Bank and erase block region 1 information (1) (P+1A)h = 53h 03h(2) (P+1A)h = 53h 01h Number of identical banks within Bank Region 107h(3) (P+1B)h = 54h 00h (P+1B)h = 54h 00h (P+1C)h = 55h 11h (P+1C)h = 55h 11h Number of program or erase operations allowed in Bank region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+1D)h = 56h 00h (P+1D)h = 56h 00h Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+1E)h = 57h 00h (P+1E)h = 57h 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+1F)h = 58h 01h (P+1F)h = 58h 02h Types of erase block regions in Bank region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(4) (P+20)h = 59h 07h (P+20)h = 59h 07h Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks in each bank Bits 16-31: n×256 = number of bytes in erase block region (P+21)h = 5Ah 00h (P+21)h = 5Ah 00h (P+22)h = 5Bh 00h (P+22)h = 5Bh 20h (P+23)h = 5Ch 01h (P+23)h = 5Ch 00h (P+24)h = 5Dh 64h (P+24)h = 5Dh 64h Bank Region 1 (Erase Block Type 1) Minimum block erase cycles × 1000(P+25)h = 5Eh 00h (P+25)h = 5Eh 00h (P+26)h = 5Fh 01h (P+26)h = 5Fh 01h Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved 5Eh 01 5Eh 01 (P+27)h = 60h 03h (P+27)h = 60h 03h Bank Region 1 (Erase Block Type 1): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved

Common Flash Interface M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB (P+28)h = 61h 06h Bank Region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+29)h = 62h 00h (P+2A)h = 63h 00h (P+2B)h = 64h 01h (P+2C)h = 65h 64h Bank Region 1 (Erase Block Type 2) Minimum block erase cycles × 1000(P+2D)h = 66h 00h (P+2E)h = 67h 01h Bank Region 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+2F)h = 68h 03h Bank Region 1 (Erase Block Type 2): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Applies to the M58WR016QT/B only. 3. Applies to the M58WR032QT/B only. 4. Bank Regions. There are two Bank Regions, see Table 29 and Table 30 for the M58WR016QT/B and see Table 31 and Table 32 for the M58WR032QT/B. Table 41. Bank and erase block region 1 information (1) (continued)

M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB Common Flash Interface Table 42. Bank and erase block region 2 information (1) 03h(2) Number of identical banks within bank region 207h(3) (P+29)h = 62h 00h (P+31)h = 6Ah 00h (P+2A)h = 63h 11h (P+32)h = 6Bh 11h Number of program or erase operations allowed in bank region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+2B)h = 64h 00h (P+33)h = 6Ch 00h Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+2C)h = 65h 00h (P+34)h = 6Dh 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+2D)h = 66h 02h (P+35)h = 6Eh 01h Types of erase block regions in Bank region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(4) (P+2E)h = 67h 06h (P+36)h = 6Fh 07h Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks in each bank Bits 16-31: n×256 = number of bytes in erase block region (P+2F)h = 68h 00h (P+37)h = 70h 00h (P+30)h = 69h 00h (P+38)h = 71h 00h (P+31)h = 6Ah 01h (P+39)h = 72h 01h (P+32)h = 6Bh 64h (P+3A)h = 73h 64h Bank Region 2 (Erase Block Type 1) Minimum block erase cycles × 1000(P+33)h = 6Ch 00h (P+3B)h = 74h 00h (P+34)h = 6Dh 01h (P+3C)h = 75h 01h Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved

Common Flash Interface M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB (P+35)h = 6Eh 03h (P+3D)h = 76h 03h Bank Region 2 (Erase Block Type 1): Page mode and synchronous mode capabilities (defined in Table 39) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+36)h = 6Fh 07h Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+37)h = 70h 00h (P+38)h = 71h 20h (P+39)h = 72h 00h (P+3A)h = 73h 64h Bank Region 2 (Erase Block Type 2) Minimum block erase cycles × 1000(P+3B)h = 74h 00h (P+3C)h = 75h 01h Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+3D)h = 76h 03h Bank Region 2 (Erase Block Type 2): Page mode and synchronous mode capabilities (defined in Table 39) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+3E)h = 77h (P+3E)h = 77h Feature Space definitions (P+3F)h = 78h (P+3F)h = 78h Reserved 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Applies to the M58WR016QT/B only. 3. Applies to the M58WR032QT/B only. 4. Bank Regions. There ar e two Bank Regions, see Table 29 and Table 30 for the M58WR016QT/B and see Table 31 and Table 32 for the M58WR032QT/B. Table 42. Bank and erase block region 2 information (1) (continued)

Figure 20. Program flowchart and pseudo code

1. Status check of SR1 (Protected Block), SR3 (V PP Invalid) and SR4 (Program Error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cl eared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 21. Double Word Program flowchart and pseudo code

1. Status check of SR1 (Protected Block), SR3 (V PP Invalid) and SR4 (Program Error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Address 1 and Address 2 mu st be consecutive addresses differing only for bit A0.
3. Any address within the bank can equally be used.

Figure 22. Quadruple Word Program flowchart and pseudo code

1. Status check of SR1 (Protected Block), SR3 (V PP Invalid) and SR4 (Program Error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
3. Any address within the bank can equally be used.

Figure 23. Program Suspend & Resume flowchart and pseudo code

1. The Read Status Register command (Write 70h) can be issu ed just before or just after the Program Resume command.

Figure 24. Block Erase flowchart and pseudo code

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can be used also.
3. Amax is equal to A19 in the M58WR 016QT/B and to A20 in the M58WR032QT/B.

Figure 25. Erase Suspend & Resume flowchart and pseudo code

1. The Read Status Register command (Write 70h) can be is sued just before or just after the Erase Resume command.

Figure 26. Locking operations flowchart and pseudo code

1. Any address within the bank can equally be used.

Figure 27. Protection Register Program flowchart and pseudo code

1. Status check of SR1 (Protected Block), SR3 (V PP Invalid) and SR4 (Program Error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cl eared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 28. Enhanced Factory Program flowchart

1. Address can remain Starting Address WA1 or be incremented.

Flowcharts and pseudo codes M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB C.1 Enhanced Factory Program pseudo code efp_command(addressFlow,dataFlow,n) /* n is the number of data to be programmed */ /* setup phase */ writeToFlash(addressFlow[0],0x30); writeToFlash(addressFlow[0],0xD0); status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); else{ /*Program Phase*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1) /*Ready for first data*/ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ writeToFlash(another_block_address,FFFFh); /* Verify Phase */ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ writeToFlash(another_block_address,FFFFh); /* exit program phase */ /* Exit Phase */ /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR4==1) /*program failure error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler();

Figure 29. Quadruple Enhanced Factory Program flowchart

1. Address can remain Starting Address WA1 (in which case the next Page is programmed) or can be any address in the
2. The address is only checked for the first Word of each Page as the order to program the Words is fixed, so subsequent

Words in each Page can be written to any address.

Flowcharts and pseudo codes M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB C.2 Quadruple Enhanced Factory Program Pseudo Code quad_efp_command(addressFlow,dataFlow,n) /* n is the number of pages to be programmed.*/ /* Setup phase */ writeToFlash(addressFlow[0],0x75); for (i=0; i++; i< n){ /*Data Load Phase*/ /*First Data*/ writeToFlash(addressFlow[i],dataFlow[i,0]); /*at the first data of the first page, Quad-EFP may be aborted*/ if (First_Page) { status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); /*2nd data*/ writeToFlash(addressFlow[i],dataFlow[i,1]); /*3rd data*/ writeToFlash(addressFlow[i],dataFlow[i,2]); /*4th data*/ writeToFlash(addressFlow[i],dataFlow[i,3]); /* Program&Verify Phase */ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ }while (status_register.SR0==1) /* Exit Phase */ writeToFlash(another_block_address,FFFFh); /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR1==1) /*program to protected block error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR4==1) /*program failure error*/ error_handler();

Table 43. Command interface states - modify table, next state (1)

1. CI = Command Interface, CR = Configuration Register, EFP = E nhanced Factory Program, Quad EFP = Quadruple Enhanced Factory

Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.

1. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data outpu t.
2. The two cycle command should be iss ued to the same bank address.
3. If the P/E.C. is active, both cycles are ignored.
4. The Clear Status Register command clears the Status Regist er error bits except when the P/E.C. is busy or suspended.
5. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’.EFP and Quad EFP are busy if Block Address is first EFP

Address. Any other commands are treated as data.

Table 44. Command interface states - modify table, next output state

1. CI = Command Interface, CR = Configuration Register , EFP = Enhanced Factory Program, Quad EFP = Quadruple
2. The output state shows the type of data that appears at the outputs if the bank address is the same as the command

state does not depend on the bank’s output state.

1. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined
2. The two cycle command should be issued to the same bank address.
3. If the P/E.C. is active , both cycles are ignored.
4. The Clear Status Register command clears the Status Regist er error bits except when the P/E.C. is busy or suspended.

Table 45. Command interface states - lock table, next state

1. CI = Command Interface, CR = Configuration Register , EFP = Enhanced Factory Program, Quad EFP = Quadruple

Enhanced Factory Program, P/E. C. = Program/Erase Controller.

1. If the P/E.C. is active , both cycles are ignored.
2. EFP and Quad EFP exit when Block Address is diffe rent from first Block Address and data is FFFFh.
3. Illegal commands are those not defined in the command set.
4. EFP and Quad EFP are allowed only when Status Register bi t SR0 is set to ‘0’. EFP and Quad EFP are busy if Block

Address is first EFP Address. Any other commands are treated as data.

Table 46. Command interface states - lock table, next output state

1. CI = Command Interface, CR = Configuration R egister, EFP = Enhanced Factory Program, Quad EFP =

Quadruple Enhanced Factory Program, P/E. C. = Program/Erase Controller.

1. If the P/E.C. is active, both cycles are ignored.
2. EFP and Quad EFP exit when Block Address is diff erent from first Block Address and data is FFFFh.
3. Illegal commands are those not defined in the command set.

Table 47. Document revision history command in Table 6: Standard commands. from Min to Max in Table 20: DC characteristics - voltages. tWHQV removed from Figure 16, Table 23, Figure 17 and Table 24. Note 3 modified. Data modified at address offset 31h in Table 36. 12-Nov-2007 2 Applied Numonyx branding.