M58WR016KU60ZA6E

M58WR016KU NUMONYX | Alldatasheet

Document overview

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• PDF pages: 123

Technical content

Datasheet sections

• 1 Description
• 2 Signal descriptions
• 2.1 Address inputs (ADQ0-ADQ15, A16-Amax)
• 2.2 Data input/output (ADQ0-ADQ15)
• 2.3 Chip Enable (E )
• 2.4 Output Enable (G )
• 2.5 Write Enable (W )
• 2.6 Write Protect (WP )
• 2.7 Reset/Power-Down (RP )
• 2.8 Latch Enable (L )
• 2.9 Clock (K)
• 2.10 Wait (WAIT)
• 2.11 Bus Invert (BINV)
• 2.13 V DDQ supply voltage
• 2.14 V PP Program supply voltage
• 2.15 V SS ground
• 2.16 V SSQ ground
• 3 Bus operations
• 3.1 Bus Read
• 3.2 Bus Write
• 3.3 Address Latch
• 3.4 Output Disable
• 3.5 Standby
• 3.6 Reset/Power-Down
• 4 Command interface
• 5 Command interface - Standard commands
• 5.1 Read Array command

Datasheet sections

• 7.7 Block Protection Status bit (SR1)
• 7.8 Bank Write/Multiple Word Program Status bit (SR0)
• 8 Configuration Register
• 8.1 Read Select bit (CR15)
• 8.2 Bus Invert Configuration (CR14)
• 8.3 X-Latency bits (CR13-CR11)
• 8.4 Wait Polarity bit (CR10)
• 8.5 Data Output Configuration bit (CR9)
• 8.6 Wait Configuration bit (CR8)
• 8.7 Burst Type bit (CR7)
• 8.8 Valid Clock Edge bit (CR6)
• 8.9 Power-Down bit (CR5)
• 8.10 Wrap Burst bit (CR3)
• 8.11 Burst length bits (CR2-CR0)
• 9 Read modes
• 9.1 Asynchronous Read mode
• 9.2 Synchronous Burst Read mode
• 9.2.1 Synchronous Burst Read Suspend
• 9.3 Single Synchronous Read mode
• 10 Dual operations and multiple bank architectu re
• 11 Block locking
• 11.1 Reading a block’s lock status
• 11.2 Locked state
• 11.3 Unlocked state
• 11.4 Lock-Down state
• 11.5 Locking operations during Erase Suspend
• 12 Program and erase times and endurance cycles
• 13 Maximum rating

Features

■ Supply voltage –V DD = 1.7 V to 2 V for Program, Erase and Read –V DDQ = 1.7 V to 2 V for I/O buffers –V PP = 9 V for fast Program ■ Multiplexed address/data ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 86 MHz – Random Access: 60 ns, 70 ns ■ Synchronous Burst Read Suspend ■ Programming time – 10 µs by Word typical for Factory Program – Double/Quadruple Word Program option – Enhanced Factory Program options ■ Memory blocks – Multiple Bank memory array: 4 Mbit Banks – Parameter Blocks (top or bottom location) ■ Dual operations – Program Erase in one Bank while Read in others – No delay between Read and Write operations ■ Block locking – All blocks locked at Power up – Any combination of blocks can be locked –W P for Block Lock-Down ■ Security – 128 bit user programmable OTP cells – 64 bit unique device number ■ Common Flash Interface (CFI) ■ 100,000 program/erase cycles per block ■ Electronic signature – Manufacturer Code: 20h – Top Device Code, M58WR016KU: 8823h M58WR032KU: 8828h M58WR064KU: 88C0h – Bottom Device Code, M58WR016KL: 8824h M58WR032KL: 8829h M58WR064KL: 88C1h ■ ECOPACK® packages available VFBGA44 (ZA) 7.5 × 5 mm FBGA www.numonyx.com

M58WRxxxKU, M58WRxxxKL Contents 7.5 V

M58WRxxxKU, M58WRxxxKL Contents

M58WRxxxKU, M58WRxxxKL Description

1 Description

The M58WR016KU/L, M58WR032KU/L and M58WR064KU/L are 16-Mbit (1 Mbit × 16), 32- Mbit (2 Mbit × 16) and 64-Mbit (4 Mbit × 16) non-volatile Flash memories, respectively. In the rest of the document, they will be referred to as M58WRxxxKU/L unless otherwise specified. The M58WRxxxKU/L may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.7 V to 2 V VDD supply for the circuitry and a 1.7 V to 2 V VDDQ supply for the Input/Output pins. An optional 9 V VPP power supply is provided to speed up customer programming. The first sixteen address lines are multiplexed with the Data Input/Output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines, A16-Amax, are the Most Significant Bit addresses. The device features an asymmetrical block architecture:

• the M58WR016KU/L have an array of 39 blocks, and are divided into 4 Mbit banks. There are 3 banks each containing 8 main blocks of 32 Kwords, and one parameter bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.
• the M58WR032KU/L have an array of 71 blocks, and are divided into 4 Mbit banks. There are 7 banks each containing 8 main blocks of 32 Kwords, and one parameter bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.
• the M58WR064KU/L have an array of 135 blocks, and are divided into 4 Mbit banks. There are 15 banks each containing 8 main blocks of 32 Kwords, and one parameter bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architectures are summarized in Tables 2, 3 and 4, and the memory maps are shown in Figures 3, 4 and 5. The Parameter Blocks are located at the top of the memory address space for the M58WR016KU, M58WR032KU and M58WR064KU, and at the bottom for the M58WR016KL, M58WR032KL and M58WR064KL. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage V DD. There are two Enhanced Factory programming commands available to speed up programming. Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 86 MHz. The synchronous burst read operation can be suspended and resumed.

Description M58WRxxxKU, M58WRxxxKL The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value IDD4 and the outputs are still driven. The M58WRxxxKU/L features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V PP ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at Power- Up. The device includes a Protection Register to increase the protection of a system’s design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by Numonyx, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. Figure 6, shows the Protection Register memory map. The memory is available in a VFBGA44 7.5 × 5 mm, 10 × 4 active ball array, 0.5 mm pitch package. It is supplied with all the bits erased (set to ’1’).

Figure 1. Logic diagram

1. Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the

Table 1. Signal names

1. Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L.

Figure 2. VFBGA44 connections (top view through package) Note1: Ball D5 is A20 in the M58WR032KU/L and M58WR064KU/L, it is Not Connected internally (NC) in the M58WR016KU/L. Ball C4 is A21 in the M58WR064KU/L, it is Not Connected internally (NC) in the M58WR016KU/L and M58WR032KU/L.

Table 2. M58WR016KU/L bank architecture Table 3. M58WR032KU/L bank architecture Table 4. M58WR064KU/L bank architecture

Figure 3. M58WR016KU/L memory map

8 Main

32 KWord00000h

32 KWord38000h

32 KWord40000h

32 KWord78000h

32 KWord80000h

32 KWordB8000h

32 KWordC0000h

32 KWordF0000h

4 KWordF8000h

4 KWordFF000h

8 Parameter

4 KWord00000h

32 KWord08000h

32 KWordF8000h

7 Main

Figure 4. M58WR032KU/L memory map

32 KWord000000h

32 KWord038000h

32 KWord100000h

32 KWord138000h

32 KWord140000h

32 KWord178000h

32 KWord180000h

32 KWord1B8000h

32 KWord1C0000h

32 KWord1F0000h

4 KWord1F8000h

4 KWord1FF000h

4 KWord000000h

32 KWord008000h

32 KWord040000h

32 KWord078000h

32 KWord080000h

32 KWord0B8000h

32 KWord0C0000h

32 KWord0F8000h

32 KWord1F8000h

Figure 5. M58WR064KU/L memory map

32 KWord300000h

32 KWord338000h

32 KWord340000h

32 KWord378000h

32 KWord380000h

32 KWord3B8000h

32 KWord3C0000h

32 KWord3F0000h

4 KWord3F8000h

4 KWord3FF000h

32 KWord3F8000h

M58WRxxxKU, M58WRxxxKL Signal descriptions

2 Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.

2.1 Address inputs (ADQ0-ADQ15, A16-Amax)

Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller.

2.2 Data input/output (ADQ0-ADQ15)

The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Bus Write operation.

2.3 Chip Enable (E )

The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V ILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.

2.4 Output Enable (G )

The Output Enable controls data outputs during the Bus Read operation of the memory.

2.5 Write Enable (W )

The Write Enable controls the Bus Write operation of the memory’s Command Interface. The data is latched on the rising edge of Chip Enable or Write Enable whichever occurs first.

2.6 Write Protect (WP )

Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the Locked- Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 17: Lock status).

Signal descriptions M58WRxxxKU, M58WRxxxKL

2.7 Reset/Power-Down (RP )

The Reset/Power-Down input provides a hardware reset of the memory, and/or power-down functions, depending on the settings in the Configuration Register. When Reset/Power- Down is at V IL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Standby Supply Current IDD3, or to the Reset/Power- Down Supply Current IDD2 if the Power-Down function is enabled. Refer to Table 22: DC characteristics - currents, for the value of IDD2 and IDD3. After reset all blocks are in the Locked state and the bits of the Configuration Register are reset except for Power-Down bit CR5. When Reset/Power-Down is at V IH, the device is in normal operation. Exiting reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs.

2.8 Latch Enable (L )

Latch Enable latches the ADQ0-ADQ15 and A16-Amax address bits on its rising edge. The address latch is transparent when Latch Enable is at V IL and it is inhibited when Latch Enable is at VIH.

2.9 Clock (K)

The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at V IL. Clock is don't care during asynchronous read and in write operations.

2.10 Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at V IH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAIT signal is forced deasserted when Output Enable is at VIH.

2.11 Bus Invert (BINV)

Bus invert is an input/output signal used to reduce the amount of power required to switch the external address/data bus. Power is saved by inverting the data on ADQ0-ADQ15 each time the inversion results in a reduced number of pin transitions. Data is inverted when BINV is at V IH (i.e. if the data is AAAAh and BINV is at VIH, AAAAh becomes 5555h). BINV is high impedance when Chip Enable or Output Enable is at VIH or when Reset/Power Down is at VIL.

2.12 V DD supply voltage

VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase).

M58WRxxxKU, M58WRxxxKL Signal descriptions

2.13 V DDQ supply voltage

VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply.

2.14 V PP Program supply voltage

VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0 V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP in the VPP1 range enables these functions (see Tables 22 and 23, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If V PP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed.

2.15 V SS ground

VSS ground is the reference for the core supply. It must be connected to the system ground.

2.16 V SSQ ground

VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS. Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1 µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 10: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.

Bus operations M58WRxxxKU, M58WRxxxKL

3 Bus operations

There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 5: Bus operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations.

3.1 Bus Read

Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at V IL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 11, 12 and 13 Read AC Waveforms, and Tables 24 and 25 Read AC Characteristics, for details of when the output becomes valid.

3.2 Bus Write

Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands and Input Data are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses must also be latched prior to the write operation by toggling Latch Enable (when Chip Enable is at V IL). The Latch Enable must be tied to VIH during the bus write operation. See Figures 16 and 17, Write AC Waveforms, and Tables 26 and 27, Write AC Characteristics, for details of the timing requirements.

3.3 Address Latch

Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at V IL during address latch operations. The addresses are latched on the rising edge of Latch Enable.

3.4 Output Disable

The outputs are high impedance when the Output Enable is at VIH.

3.5 Standby

during a program or erase operation, the device enters Standby mode when finished.

3.6 Reset/Power-Down

and the memory content is no longer valid. Table 5. Bus operations

1. WAIT signal polarity is configured us ing the Set Configuration Register command.

4 Command interface

All Bus Write operations to the memory are interpreted by the Command Interface. whose output may be read at any time to monitor the progress or the result of the operation. DD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will be ignored. Interface States - Modify and Lock Tables, for a summary of the Command Interface. Table 6. Command codes

M58WRxxxKU, M58WRxxxKL Command interface - Standard commands

5 Command interface - Standard commands

The following commands are the basic commands used to read, write to and configure the device. Refer to Table 7: Standard commands, in conjunction with the following text descriptions.

5.1 Read Array command

The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command and return the addressed bank to Read Array mode. Subsequent read operations will read the addressed location and output the data. A Read Array command can be issued in one bank while programming or erasing in another bank. However if a Read Array command is issued to a bank currently executing a Program or Erase operation the command will be executed but the output data is not guaranteed.

5.2 Read Status Register command

The Status Register indicates when a Program or Erase operation is complete and the success or failure of operation itself. Issue a Read Status Register command to read the Status Register content. The Read Status Register command can be issued at any time, even during Program or Erase operations. The following read operations output the content of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G returns to VIH. Either E or G must be toggled to update the latched data. See Table 10 for the description of the Status Register Bits. This mode supports asynchronous or single synchronous reads only.

5.3 Read Electronic Signature command

The Read Electronic Signature command reads the Manufacturer and Device Codes, the Block Locking Status, the Protection Register, and the Configuration Register. The Read Electronic Signature command consists of one write cycle to an address within one of the banks. A subsequent Read operation in the same bank will output the Manufacturer Code, the Device Code, the protection Status of the blocks in the targeted bank, the Protection Register, or the Configuration Register (see Table 8). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during Protection Register Program operations. Dual operations between the Parameter bank and the Electronic Signature location are not allowed (see Table 16: Dual operation limitations for details). If a Read Electronic Signature command is issued in a bank that is executing a Program or Erase operation the bank will go into Read Electronic Signature mode, subsequent Bus Read cycles will output the Electronic Signature data and the Program/Erase controller will continue to program or erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support synchronous burst reads.

Command interface - Standard commands M58WRxxxKU, M58WRxxxKL

5.4 Read CFI Query command

The Read CFI Query command is used to read data from the Common Flash Interface (CFI). The Read CFI Query Command consists of one Bus Write cycle, to an address within one of the banks. Once the command is issued subsequent Bus Read operations in the same bank read from the Common Flash Interface. If a Read CFI Query command is issued in a bank that is executing a Program or Erase operation the bank will go into Read CFI Query mode, subsequent Bus Read cycles will output the CFI data and the Program/Erase controller will continue to Program or Erase in the background. This mode supports asynchronous or single synchronous reads only, it does not support synchronous burst reads. The status of the other banks is not affected by the command (see Table 14). After issuing a Read CFI Query command, a Read Array command should be issued to the addressed bank to return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI memory space are not allowed (see Table 16: Dual operation limitations). See Appendix B: Common Flash Interface, Tables 37, 38, 39, 40, 41, 42, 43, 44, 45 and 46 for details on the information contained in the Common Flash Interface memory area.

5.5 Clear Status Register command

The Clear Status Register command can be used to reset (set to ‘0’) error bits SR1, SR3, SR4 and SR5 in the Status Register. One bus write cycle is required to issue the Clear Status Register command. After the Clear Status Register command the bank returns to read mode. The error bits in the Status Register do not automatically return to ‘0’ when a new command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command.

M58WRxxxKU, M58WRxxxKL Command interface - Standard commands

5.6 Block Erase command

The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. The Block Erase command can be issued at any moment, regardless of whether the block has been programmed or not. Two Bus Write cycles are required to issue the command.

• The first bus cycle sets up the Erase command.
• The second latches the block address in the Program/Erase Controller and starts it. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued. During Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 18: Program, erase times and endurance cycles. See Appendix C, Figure 24: Block Erase flowchart and pseudocode, for a suggested flowchart for using the Block Erase command.

5.7 Program command

The memory array can be programmed word-by-word. Only one Word in one bank can be programmed at any one time. If the block is protected then the Program operation will abort, the data in the block will not be changed and the Status Register will output the error. Two bus write cycles are required to issue the Program Command.

• The first bus cycle sets up the Program command.
• The second latches the Address and the Data to be written and starts the Program/Erase Controller. After programming has started, read operations in the bank being programmed output the Status Register content. During Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 18: Program, erase times and endurance cycles. Programming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. See Appendix C, Figure 20: Program flowchart and pseudocode, for the flowchart for using the Program command.

Command interface - Standard commands M58WRxxxKU, M58WRxxxKL

5.8 Program/Erase Suspend command

The Program/Erase Suspend command is used to pause a Program or Block Erase operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to ‘1’. The command can be addressed to any bank. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array (cannot read the suspended block), Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Clear Status Register, Set Configuration Register, Program, Block Lock, Block Lock-Down or Block Unlock command will also be accepted. The block being erased may be protected by issuing the Block Lock or Block Lock-Down commands. Only the blocks not being erased may be read or programmed correctly. When the Program/Erase Resume command is issued the operation will complete. Refer to the Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to V IH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 23: Program Suspend & Resume flowchart and pseudocode, and Figure 25: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using the Program/Erase Suspend command.

5.9 Program/Erase Resume command

The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command can be written to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. If the bank was in Read Array mode subsequent read operations will output invalid data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the programming operation has completed. It is possible to accumulate suspend operations. For example: suspend an erase operation, start a programming operation, suspend the programming operation then read the array. See Appendix C, Figure 23: Program Suspend & Resume flowchart and pseudocode, and Figure 25: Erase Suspend & Resume flowchart and pseudocode, for flowcharts for using the Program/Erase Resume command.

M58WRxxxKU, M58WRxxxKL Command interface - Standard commands

5.10 Protection Register Program command

The Protection Register Program command is used to Program the 128 bit user One-Time- Programmable (OTP) segment of the Protection Register and the Protection Register Lock. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protection Register Program command.

• The first bus cycle sets up the Protection Register Program command.
• The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (Figure 6: Protection Register memory map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register is not reversible. The Protection Register Program cannot be suspended. Dual operations between the Parameter Bank and the Protection Register memory space are not allowed (see Table 16: Dual operation limitations for details). See Appendix C, Figure 27: Protection Register Program flowchart and pseudocode, for a flowchart for using the Protection Register Program command.

5.11 Set Configuration Register command

The Set Configuration Register command is used to write a new value to the Configuration Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Configuration Register command.

• The first cycle writes the setup command and the address corresponding to the Configuration Register content.
• The second cycle writes the Configuration Register data and the confirm command. Once the command is issued the memory returns to Read mode. The values of the Configuration Register must always be presented on ADQ15-ADQ0. CR0 is on ADQ0, CR1 on ADQ1, etc.; the other address bits are ignored.

Command interface - Standard commands M58WRxxxKU, M58WRxxxKL

5.12 Block Lock command

The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command.

• The first bus cycle sets up the Block Lock command.
• The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 17 shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or power- down/power-up. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix C, Figure 26: Locking operations flowchart and pseudocode, for a flowchart for using the Lock command.

5.13 Block Unlock command

The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command.

• The first bus cycle sets up the Block Unlock command.
• The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 17 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 26: Locking operations flowchart and pseudocode, for a flowchart for using the Unlock command.

5.14 Block Lock-Down command

A locked or unlocked block can be locked-down by issuing the Block Lock-Down command. A locked-down block cannot be programmed or erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command.

• The first bus cycle sets up the Block Lock command.
• The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 17 shows the Lock Status after issuing a Block Lock- Down command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 26: Locking operations flowchart and pseudocode, for a flowchart for using the Lock-Down command.

Table 7. Standard commands

1. Must be same bank as in the first cyc le. The signature addresses are listed in Table 8
2. Any address within the bank can be used.
3. X = Don't Care, WA = Word Address in targeted ban k, RD = Read Data, SRD = Status Register Data,

CRD = Configuration Register Data.

Figure 6. Protection Register memory map Table 8. Electronic signature codes

1. CR = Configuration Register

M58WRxxxKU, M58WRxxxKL Command interface - Factory program commands

6 Command interface - Factory program commands

The Factory Program commands are used to speed up programming. They require VPP to be at VPPH. Refer to Table 9: Factory Program commands, in conjunction with the following text descriptions.

6.1 Double Word Program command

The Double Word Program command improves the programming throughput by writing a page of two adjacent words in parallel. The two words must differ only for the address ADQ0. If the block is protected then the Double Word Program operation will abort, the data in the block will not be changed and the Status Register will output the error. If programming is attempted with V PP ≠ VPPH, the command is ignored. Three bus write cycles are necessary to issue the Double Word Program command.

• The first bus cycle sets up the Double Word Program Command.
• The second bus cycle latches the Address and the Data of the first word to be written.
• The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations in the bank being programmed output the Status Register content after the programming has started. During Double Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Double Word Program operations and the command cannot be suspended. Typical Program times are given in Table 18: Program, erase times and endurance cycles. Programming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. See Appendix C, Figure 21: Double Word Program flowchart and pseudocode, for the flowchart for using the Double Word Program command.

Command interface - Factory program commands M58WRxxxKU, M58WRxxxKL

6.2 Quadruple Word Program command

The Quadruple Word Program command improves the programming throughput by writing a page of four adjacent words in parallel. The four words must differ only for the addresses ADQ0 and ADQ1. If the block is protected then the Quadruple Word Program operation will abort, the data in the block will not be changed and the Status Register will output the error. If programming is attempted with V PP ≠ VPPH, the command is ignored. Five bus write cycles are necessary to issue the Quadruple Word Program command.

• The first bus cycle sets up the Double Word Program Command.
• The second bus cycle latches the Address and the Data of the first word to be written.
• The third bus cycle latches the Address and the Data of the second word to be written.
• The fourth bus cycle latches the Address and the Data of the third word to be written.
• The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. During Quadruple Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Quadruple Word Program operations and the command cannot be suspended. Typical Program times are given in Table 18: Program, erase times and endurance cycles. See Appendix C, Figure 22: Quadruple Word Program flowchart and pseudocode, for the flowchart for using the Quadruple Word Program command.

M58WRxxxKU, M58WRxxxKL Command interface - Factory program commands

6.3 Enhanced Factory Program command

The Enhanced Factory Program command can be used to program large streams of data within any one block. It greatly reduces the total programming time when a large number of words are written to a block at any one time. The use of the Enhanced Factory Program command requires certain operating conditions.

• VPP must be set to VPPH
• VDD must be within operating range
• Ambient temperature TA must be 30°C ± 10°C
• The targeted block must be unlocked Dual operations are not supported during the Enhanced Factory Program operation and the command cannot be suspended. For optimum performance the Enhanced Factory Program commands should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical Program times are given in Table 18. If the block is protected then the Enhanced Factory Program operation will abort, the data in the block will not be changed and the Status Register will output the error. The Enhanced Factory Program command has four phases: the Setup Phase, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary and the Exit Phase. Refer to Table 9: Factory Program commands, and Figure 28: Enhanced Factory Program flowchart.

6.3.1 Setup Phase

The Enhanced Factory Program command requires two Bus Write operations to initiate the command.

• The first bus cycle sets up the Enhanced Factory Program command.
• The second bus cycle confirms the command. confirm command is issued, read operations output the Status Register data. The read Status Register command must not be issued as it will be interpreted as data to program.

Command interface - Factory program commands M58WRxxxKU, M58WRxxxKL

6.3.2 Program Phase

The Program Phase requires n+1 cycles, where n is the number of words (refer to Table 9: Factory Program commands and Figure 28: Enhanced Factory Program flowchart). Three successive steps are required to issue and execute the Program Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next word. 2. Each subsequent word to be programmed is latched with a new Bus Write operation. The address can either remain the Start Address, in which case the P/E.C. increments the address location or the address can be incremented in which case the P/E.C. jumps to the new address. If any address that is not in the same block as the Start Address is given with data FFFFh, the Program Phase terminates and the Verify Phase begins. The Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next word. 3. Finally, after all words have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the programming phase. The memory is now set to enter the Verify Phase.

6.3.3 Verify Phase

The Verify Phase is similar to the Program Phase in that all words must be resent to the memory for them to be checked against the programmed data. The Program/Erase Controller checks the stream of data with the data that was programmed in the Program Phase and reprograms the memory location if necessary. Three successive steps are required to execute the Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first word, to be verified. The Status Register bit SR0 should be read to check that the Program/Erase Controller is ready for the next word. 2. Each subsequent word to be verified is latched with a new Bus Write operation. The words must be written in the same order as in the Program Phase. The address can remain the Start Address or be incremented. If any address that is not in the same block as the Start Address is given with data FFFFh, the Verify Phase terminates. Status Register bit SR0 should be read to check that the P/E.C. is ready for the next word. 3. Finally, after all words have been verified, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Verify Phase. If the Verify Phase is successfully completed the memory remains in Read Status Register mode. If the Program/Erase Controller fails to reprogram a given location, the error will be signaled in the Status Register.

6.3.4 Exit Phase

Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has returned to Read mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details.

M58WRxxxKU, M58WRxxxKL Command interface - Factory program commands

6.4 Quadruple Enhanced Factory Program command

The Quadruple Enhanced Factory Program command can be used to program one or more pages of four adjacent words in parallel. The four words must differ only for the addresses ADQ0 and ADQ1. V PP must be set to VPPH during Quadruple Enhanced Factory Program. If the block is protected then the Quadruple Enhanced Factory Program operation will abort, the data in the block will not be changed and the Status Register will output the error. It has four phases: the Setup Phase, the Load Phase where the data is loaded into the buffer, the combined Program and Verify Phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the Exit Phase. Unlike the Enhanced Factory Program it is not necessary to resubmit the data for the Verify Phase. The Load Phase and the Program and Verify Phase can be repeated to program any number of pages within the block.

6.4.1 Setup Phase

The Quadruple Enhanced Factory Program command requires one Bus Write operation to initiate the load phase. After the setup command is issued, read operations output the Status Register data. The Read Status Register command must not be issued as it will be interpreted as data to program.

6.4.2 Load Phase

The Load Phase requires 4 cycles to load the data (refer to Table 9: Factory Program commands and Figure 29: Quadruple enhanced factory program flowchart). Once the first word of each Page is written it is impossible to exit the Load phase until all four words have been written. Two successive steps are required to issue and execute the Load Phase of the Quadruple Enhanced Factory Program command. 1. Use one Bus Write operation to latch the Start Address and the first word of the first Page to be programmed. For subsequent Pages the first word address can remain the Start Address (in which case the next Page is programmed) or can be any address in the same block. If any address with data FFFFh is given that is not in the same block as the Start Address, the device enters the Exit Phase. For the first Load Phase Status Register bit SR7 should be read after the first word has been issued to check that the command has been accepted (bit SR7 set to ‘0’). This check is not required for subsequent Load Phases. 2. Each subsequent word to be programmed is latched with a new Bus Write operation. The address is only checked for the first word of each Page as the order of the words to be programmed is fixed. The memory is now set to enter the Program and Verify Phase.

Command interface - Factory program commands M58WRxxxKU, M58WRxxxKL

6.4.3 Program and Verify Phase

In the Program and Verify Phase the four words that were loaded in the Load Phase are programmed in the memory array and then verified by the Program/Erase Controller. If any errors are found the Program/Erase Controller reprograms the location. During this phase the Status Register shows that the Program/Erase Controller is busy, Status Register bit SR7 set to ‘0’, and that the device is not waiting for new data, Status Register bit SR0 set to ‘1’. When Status Register bit SR0 is set to ‘0’ the Program and Verify phase has terminated. Once the Verify Phase has successfully completed subsequent pages in the same block can be loaded and programmed. The device returns to the beginning of the Load Phase by issuing one Bus Write operation to latch the Address and the first of the four new words to be programmed.

6.4.4 Exit Phase

Finally, after all the pages have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Load and Program and Verify Phases. Status Register bit SR7 set to ‘1’ and bit SR0 set to ‘0’ indicate that the Quadruple Enhanced Factory Program command has terminated. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. If the Program and Verify Phase has successfully completed the memory returns to Read mode. If the P/E.C. fails to program and reprogram a given location, the error will be signaled in the Status Register.

Table 9. Factory Program commands (1)

1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address.
2. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0.
3. Any address within the bank can be used.
4. Word Addresses 1,2,3 and 4 must be consecut ive Addresses differing only for A0 and A1.
5. A Bus Read must be done between each Write cycle where the dat a is programmed or verified to read the Status Register

and check that the memory is ready to accept the next data. n = number of words, i = number of Pages to be programmed.

1. Any address within the block can be used.
2. WA1 is the Start Address. NOT WA1 is any add ress that is not in the same block as WA1.
3. Address can remain Starting Address WA1 or be incremented.
4. Address is only checked for the first word of each Page as the order to program the words in each page is fixed so

subsequent words in each Page can be written to any address.

Status Register M58WRxxxKU, M58WRxxxKL

7 Status Register

The Status Register provides information on the current or previous Program or Erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to V IH. The Status Register can only be read using single asynchronous or single synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during Program and Erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the addressed bank. The bits in the Status Register are summarized in Table 10: Status Register bits. Refer to Table 10 in conjunction with the following text descriptions.

7.1 Program/Erase Controller Status bit (SR7)

The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, operations the Program/Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, V PP Status and Block Lock Status bits should be tested for errors.

7.2 Erase Suspend Status bit (SR6)

The Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be suspended in the addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR7 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low.

M58WRxxxKU, M58WRxxxKL Status Register

7.3 Erase Status bit (SR5)

The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

7.4 Program Status bit (SR4)

The Program Status bit is used to identify either a Program failure, or an attempt to program a ‘1’ to an already programmed bit when VPP = VPPH. When the Program Status bit goes High (set to ‘1’) after a Program failure, the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. After an attempt to program a ‘1’ to an already programmed bit, the Program Status bit SR4 only goes High (set to ’1’) if VPP = VPPH (if VPP ≠ VPPH, SR4 remains Low (set to ‘0’) and the attempt is not shown). The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.

7.5 V PP Status bit (SR3)

The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the VPP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

Status Register M58WRxxxKU, M58WRxxxKL

7.6 Program Suspend Status bit (SR2)

The Program Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low.

7.7 Block Protection Status bit (SR1)

The Block Protection Status bit can be used to identify if a Program or Block Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to ‘1’), a Program or Erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.

7.8 Bank Write/Multiple Word Program Status bit (SR0)

The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Enhanced Factory Program mode the Multiple Word Program bit shows if a word has finished programming or verifying depending on the phase. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to ‘0’). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to ‘0’), the addressed bank is executing a Program or Erase operation. When the Program/Erase Controller Status bit is Low (set to ‘0’) and the Bank Write Status bit is High (set to ‘1’), a Program or Erase operation is being executed in a bank other than the one being addressed. In Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to ‘0’), the device is ready for the next word, if the Multiple Word Program Status bit is High (set to ‘1’) the device is not ready for the next word. Note: Refer to Appendix C: Flowcharts and pseudocodes, for using the Status Register.

Table 10. Status Register bits

1. Logic level '1' is High, '0' is Low.

Configuration Register M58WRxxxKU, M58WRxxxKL

8 Configuration Register

The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power- Up the device is configured for asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 12 They specify the selection of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 7 and 8 for examples of synchronous burst configurations.

8.1 Read Select bit (CR15)

The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to’1’ for asynchronous access.

8.2 Bus Invert Configuration (CR14)

The Bus Invert Configuration bit is used to enable the BINV functionality. When the functionality is enabled, if the BINV pin operates as an input pin (during write bus operations), the BINV signal must always be driven; if it operates as an output pin (during read bus operations), the functionality is valid only during synchronous read operations.

8.3 X-Latency bits (CR13-CR11)

to Figure 7: X-latency and data output configuration example. the device and the Frequency used to read the Flash memory in Synchronous mode.

8.4 Wait Polarity bit (CR10)

Polarity bit is set to ‘1’ the Wait signal is active High.

8.5 Data Output Configuration bit (CR9)

• tK > tKQV + tQVK_CPU where tK is the clock period, tQVK_CPU is the data setup time required by the system CPU and tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 7: X-latency and data output configuration example.

8.6 Wait Configuration bit (CR8)

asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid. bit is ’1’ the Wait output pin is asserted one clock cycle before the wait state. Table 11. X-latency settings

30 MHz 33 ns 2

40 MHz 25 ns 3

54 MHz 19 ns 4

66 MHz 15 ns 4

86 MHz 12 ns 5

Configuration Register M58WRxxxKU, M58WRxxxKL

8.7 Burst Type bit (CR7)

The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses; when the Burst Type bit is ’1’ the memory outputs from sequential addresses. See Table 13: Burst type definition, for the sequence of addresses output from a given starting address in each mode.

8.8 Valid Clock Edge bit (CR6)

The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock is active.

8.9 Power-Down bit (CR5)

The Power-Down bit is used to enable or disable the Power-Down function. When it is set to ‘0’ the Power-Down function is disabled. If the Reset/Power-Down, RP , pin goes Low (VIL), the device is reset and the supply current IDD is reduced to the Standby value IDD3. When the Power-Down bit is set to ‘1’ the Power-Down function is enabled. If the Reset/Power- Down, RP , pin goes Low (VIL) the device switches to the Power-Down state and the supply current IDD is reduced to the Reset/Power-Down value, IDD2. The recovery time after a Reset/Power-Down, RP, pulse is significantly longer when Power- Down is enabled (see Table 28: Reset and Power-up ac characteristics).

8.10 Wrap Burst bit (CR3)

The burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not wrap.

M58WRxxxKU, M58WRxxxKL Configuration Register

8.11 Burst length bits (CR2-CR0)

The Burst Length bits set the number of words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8, 16 words no-wrap, depending on the starting address, the device asserts the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1, 2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 16 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 13: Burst type definition. CR4 is reserved for future use.

Table 12. Configuration Register

0 Synchronous Read

1 Asynchronous Read (Default at power-on)

0 BINV (power save) disabled (default)

1 BINV (power save) enabled

111 Reserved (default)

0 WAIT is active Low (default)

1 WAIT is active High

0 Data held for one clock cycle

1 Data held for two clock cycles (default)

0 WAIT is active during wait state (default)

1 WAIT is active one data cycle before wait state

0 Interleaved

1 Sequential (default)

0 Falling Clock edge

1 Rising Clock edge (default)

0 Power-Down disabled (default)

1 Power-Down enabled

1 No Wrap (default)

111 Continuous (CR7 must be set to ‘1’) (default)

Table 13. Burst type definition

Table 13. Burst type definition (continued)

Figure 7. X-latency and data output configuration example

1. Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L.
2. Settings shown: X-latency = 4, Data Output held for one clock cycle.

Figure 8. Wait configuration example

1. Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L.

M58WRxxxKU, M58WRxxxKL Read modes

9 Read modes

Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is Asynchronous; if the data output is synchronized with clock, the read operation is Synchronous. The Read mode and data output format are determined by the Configuration Register. (See Configuration Register section for details). All banks supports both asynchronous and synchronous read operations. The Multiple Bank architecture allows read operations in one bank, while write operations are being executed in another (see Tables 14 and 15).

9.1 Asynchronous Read mode

In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for Asynchronous operations. In Asynchronous Read mode, the WAIT signal is always deasserted. The device features an Automatic Standby mode. During asynchronous read operations, after a bus inactivity of 150 ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value I DD4 and the outputs are still driven. See Table 24: Asynchronous Read ac characteristics, and Figure 11: Asynchronous random access read ac waveforms.

Read modes M58WRxxxKU, M58WRxxxKL

9.2 Synchronous Burst Read mode

In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence is started at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable. Addresses are internally incremented and after a delay of 2 to 5 clock cycles (X latency bits CR13-CR11) the corresponding data are output on each clock cycle. The number of words to be output during a Synchronous Burst Read operation can be configured as 4, 8 or 16 words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Burst Type and the Wrap Burst bits in the Configuration Register. The burst sequence may be configured to be sequential or interleaved (CR7). The burst reads can be confined inside the 4, 8 or 16 word boundary (Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to the Burst Length (4, 8 or 16 words), the wrapped configuration has no impact on the output sequence. Interleaved mode is not allowed in Continuous Burst Read mode or with No Wrap sequences. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 16 word boundary and the starting address was at the end of a four word boundary. WAIT is asserted during X-latency, the Wait state and at the end of a 4, 8 and 16 word burst. It is only deasserted when output data are valid or when G is at VIH. In Continuous Burst Read mode a Wait state will occur when crossing the first 16 word boundary. If the burst starting address is aligned to a 4 word Page, the Wait state will not occur. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 25: Synchronous Read ac characteristics, and Figure 12: Synchronous Burst Read ac waveforms, for details.

M58WRxxxKU, M58WRxxxKL Read modes

9.2.1 Synchronous Burst Read Suspend

A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when E is low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The clock signal is then halted at V IH or at VIL, and G goes high. When G becomes low again and the clock signal restarts, the Synchronous Burst Read operation is resumed exactly where it stopped. WAIT being gated by E remains active and will not revert to high-impedance when G goes high. So if two or more devices are connected to the system’s READY signal, to prevent bus contention the WAIT signal of the Flash memory should not be directly connected to the system’s READY signal. See Table 25: Synchronous Read ac characteristics, and Figure 14: Synchronous Burst Read Suspend ac waveforms for details.

9.3 Single Synchronous Read mode

Single Synchronous Read operations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is deasserted when Output Enable, G , is at VIH or for the one clock cycle during which output data is valid. Otherwise, it is asserted. See Table 25: Synchronous Read ac characteristics and Figure 13: Single Synchronous Read ac waveforms, for details.

10 Dual operations and multiple bank architecture

executed from one bank while another bank is being programmed or erased. that read operations are possible at any moment. Tables 14 and 15 show the dual operations possible in other banks and in the same bank. complete list of possible commands refer to Appendix D: Command interface state tables. Table 14. Dual operations allowed in other banks

Table 15. Dual operations allowed in same bank

1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase
2. Not allowed in the Block or word that is being erased or programmed.

Table 16. Dual operation limitations

Block locking M58WRxxxKU, M58WRxxxKL

11 Block locking

The M58WRxxxKU/L features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection.

• Lock/Unlock - this first level allows software-only control of block locking.
• Lock-Down - this second level requires hardware interaction before locking can be changed.
• VPP ≤ VPPLK - the third level offers a complete hardware protection against program and erase on all blocks. The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 17, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C: Flowcharts and pseudocodes, Figure 26, shows a flowchart for the locking operations.

11.1 Reading a block’s lock status

The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 8, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system.

11.2 Locked state

The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.

11.3 Unlocked state

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered- down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command.

M58WRxxxKU, M58WRxxxKL Block locking

11.4 Lock-Down state

Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. Locked-Down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP =1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is Low, blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was high. Device reset or power-down resets all blocks, including those in Lock-Down, to the Locked state.

11.5 Locking operations during Erase Suspend

Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix D: Command interface state tables, for detailed information on which commands are valid during erase suspend.

Table 17. Lock status

1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for

a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL.

1. All blocks are locked at power-up, so the de fault configuration is 001 or 101 according to WP status.
2. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

12 Program and erase times and endurance cycles

depends on the voltage supply used. Table 18. Program, erase times and endurance cycles (1)

1. The difference between preprogrammed and not preprogrammed is not significant (‹30 ms).
2. Values are liable to change with the external system- level overhead (command sequence and Status Register polling
3. Measurements performed at 25°C. T A = 30°C ±10°C for Quadruple Word, Double Word and Quadruple Enhanced Factory

13 Maximum rating

and other relevant quality documents. Table 19. Absolute maximum ratings

14 DC and AC parameters

Figure 9. AC measurement I/O waveform Table 20. Operating and ac measurement conditions

Figure 10. AC measurement load circuit Table 21. Capacitance (1)

1. Sampled only, not 100% tested.

Table 22. DC characteristics - currents

1. Sampled only, not 100% tested.
2. V DD Dual operation current is the sum of read and program or erase currents.

Table 23. DC characteristics - voltages

Figure 11. Asynchronous random access read ac waveforms Notes: 1- WAIT is active Low. 2- Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L.

Table 24. Asynchronous Read ac characteristics

1. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
2. Sampled only, not 100% tested.

Figure 12. Synchronous Burst Read ac waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

1. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge.
3. The BINV signal has the waveform shown only if it has been enabled with the Configuration Register. If it is disabled, it remains low.
4. Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L.

Figure 13. Single Synchronous Read ac waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge.
3. The BINV signal has the shown waveform only if it has been enabled with the Configuration Register. When disabled, it remains Low.
4. Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L.

Figure 14. Synchronous Burst Read Suspend ac waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. The CLOCK signal can be held high or low
3. Address latched and data output on the rising clock edge.
4. The BINV signal has the shown waveform only if it has been enabled with the Configuration Register. When disabled, it remains Low.
5. Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L.

Figure 15. Clock input ac waveform

1. Sampled only, not 100% tested. For other timings please refer to Table 24: Asynchronous Read ac

Table 25. Synchronous Read ac characteristics

Figure 16. Write ac waveforms, Write Enable controlled Note 1: Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L.

1. Sampled only, not 100% tested.

Table 26. Write ac characteristics, Write Enable controlled

1. t WHEL and tWHLL have this value when reading from the targeted bank or when reading from any address

to the Configuration Register have been issued, tWHEL and tWHLL are 0 ns.

Figure 17. Write ac waveforms, Chip Enable controlled Note 1: Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L.

1. Sampled only, not 100% tested.
2. t WHEL has this value when reading from the targeted bank or when reading from any address after a Set

Configuration Register have been issued, tWHEL is 0 ns. Table 27. Write ac characteristics, Chip Enable controlled

Figure 18. Reset and Power-up ac waveforms Table 28. Reset and Power-up ac characteristics

1. The device Reset is possible but not guaranteed if t PLPH < 50 ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 19. VFBGA44 7.5 × 5 mm, 10 × 4 ball array, 0.50 mm pitch, bottom view

Table 29. VFBGA44 7.5 × 5 mm, 10 × 4 ball array, 0.50 mm pitch, package

16 Part numbering

Devices are shipped from the factory with the memory content bits erased to ’1’. Table 30. Ordering information scheme

Table 31. Top boot block addresses, M58WR016KU

1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;

Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 32. Bottom boot block addresses, M58WR016KL Table 31. Top boot block addresses, M58WR016KU (continued)

1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only;

Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 32. Bottom boot block addresses, M58WR016KL (continued)

Table 33. Top boot block addresses, M58WR032KU

1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;

Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 33. Top boot block addresses, M58WR032KU (continued)

Table 34. Bottom boot block addresses, M58WR032KL

Table 34. Bottom boot block addresses, M58WR032KL (continued)

1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only;

Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank).

Table 35. Top boot block addresses, M58WR064KU

Table 35. Top boot block addresses, M58WR064KU (continued)

1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;

Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 36. Bottom boot block addresses, M58WR064KL

Table 36. Bottom boot block addresses, M58WR064KL (continued)

1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only;

Bank Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank).

software to upgrade itself when necessary. lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0. been written by Numonyx. Issue a Read Array command to return to Read mode. Table 37. Query structure overview (1)

1. The Flash memory display the CFI data structure w hen CFI Query command is issued. In this table are

Table 38. CFI query identification string

Table 39. CFI query system interface information

Table 40. Device geometry definition

Table 41. Primary algorithm-specific extended query table (1) field of optional features follows at the end of the bit-30 field.

1. The variable P is a pointer that is defined at CFI offset 15h.

Common Flash Interface M58WRxxxKU, M58WRxxxKL 1. The variable P is a pointer that is defined at CFI offset 15h. 2. Bank Regions. There are tw o Bank Regions, see Tables 31, 32, 33, 34, 35 and 36. Table 42. Protection Register information (1)

1. The variable P is a pointer that is defined at CFI offset 15h.

Table 43. Burst Read Information (1)

8 Bytes

width to determine the burst data output width. (P+18)h = 51h 0007h Synchronous mode read capability configuration 4 Cont.

1. The variable P is a pointer that is defined at CFI offset 15h.

Table 44. Bank and Erase block region information

Description

(P+19)h = 52h 02h (P+19)h = 52h 02h Number of Bank Regions within the device

Table 45. Bank and Erase block region 1 information (1)

1. The variable P is a pointer that is defined at CFI offset 15h.
2. Bank Regions. There are tw o Bank Regions, see Tables 31, 32, 33, 34, 35 and 36.

Table 45. Bank and Erase block region 1 information (1) (continued)

Table 46. Bank and Erase block region 2 information (1)

1. The variable P is a pointer that is defined at CFI offset 15h.
2. Bank Regions. There are tw o Bank Regions, see Tables 31, 32, 33, 34, 35 and 36.

Table 46. Bank and Erase block region 2 information (1) (continued)

Figure 20. Program flowchart and pseudocode

1. Status check of SR1 (Protected Block), SR3 (V PP Invalid) and SR4 (Program Error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cl eared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 21. Double Word Program flowchart and pseudocode

1. Status check of b1 (Protected Block), b3 (V PP Invalid) and b4 (Program Error) can be made after each program operation
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 mu st be consecutive addresses differing only for bit A0.
4. Any address within the bank can equally be used.

Figure 22. Quadruple Word Program flowchart and pseudocode

1. Status check of SR1 (Protected Block), SR3 (V PP Invalid) and SR4 (Program Error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
3. Any address within the bank can equally be used.

Figure 23. Program Suspend & Resume flowchart and pseudocode

1. The Read Status Register command (Write 70h) can be issu ed just before or just after the Program Resume command.

Figure 24. Block Erase flowchart and pseudocode

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.
3. Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L.

Figure 25. Erase Suspend & Resume flowchart and pseudocode

1. The Read Status Register command (Write 70h) can be is sued just before or just after the Erase Resume command.

Figure 26. Locking operations flowchart and pseudocode

1. Any address within the bank can equally be used.

Figure 27. Protection Register Program flowchart and pseudocode

1. Status check of SR1 (Protected Block), SR3 (V PP Invalid) and SR4 (Program Error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cl eared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 28. Enhanced Factory Program flowchart

1. Address can remain Starting Address WA1 or be incremented.

Flowcharts and pseudocodes M58WRxxxKU, M58WRxxxKL

16.1 Enhanced Factory Program pseudocode

efp_command(addressFlow,dataFlow,n) /* n is the number of data to be programmed */ /* setup phase */ writeToFlash(addressFlow[0],0x30); writeToFlash(addressFlow[0],0xD0); status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); else{ /*Program Phase*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1) /*Ready for first data*/ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ writeToFlash(another_block_address,FFFFh); /* Verify Phase */ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ writeToFlash(another_block_address,FFFFh); /* exit program phase */ /* Exit Phase */ /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR4==1) /*program failure error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler();

Figure 29. Quadruple enhanced factory program flowchart

1. Address can remain Starting Address WA1 (in which case the next Page is programmed) or can be any address in the
2. The address is only checked for the first word of each Page as the order to program the words is fixed, so subsequent

words in each Page can be written to any address.

Flowcharts and pseudocodes M58WRxxxKU, M58WRxxxKL

16.2 Quadruple enhanced factory program pseudocode

quad_efp_command(addressFlow,dataFlow,n) /* n is the number of pages to be programmed.*/ /* Setup phase */ writeToFlash(addressFlow[0],0x75); for (i=0; i++; i< n){ /*Data Load Phase*/ /*First Data*/ writeToFlash(addressFlow[i],dataFlow[i,0]); /*at the first data of the first page, Quad-EFP may be aborted*/ if (First_Page) { status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); /*2nd data*/ writeToFlash(addressFlow[i],dataFlow[i,1]); /*3rd data*/ writeToFlash(addressFlow[i],dataFlow[i,2]); /*4th data*/ writeToFlash(addressFlow[i],dataFlow[i,3]); /* Program&Verify Phase */ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ }while (status_register.SR0==1) /* Exit Phase */ writeToFlash(another_block_address,FFFFh); /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR1==1) /*program to protected block error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR4==1) /*program failure error*/ error_handler();

Table 47. Command interface states - modify table, next state (1)

1. CI = Command Interface, CR = Configuration Register , EFP = Enhanced Factory Program, Quad EFP = Quadruple

Controller, PS = program suspend, ES = erase suspend, IS = Illegal state.

1. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined
2. The two cycle command should be issued to the same bank address.
3. If the P/E.C. is active , both cycles are ignored.
4. The Clear Status Register command clears the Status Regist er error bits except when the P/E.C. is busy or suspended.
5. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’.EFP and Quad EFP are busy if Block

Address is first EFP Address. Any other commands are treated as data. Table 47. Command interface states - modify table, next state (1) (continued)

Table 48. Command interface states - Modify table, next output (1)

1. CI = Command Interface, CR = Configuration Register , EFP = Enhanced Factory Program, Quad EFP = Quadruple

Controller, IS = Illegal State, ES = Erase suspend, PS = Program suspend.

1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command

state does not depend on the bank’s output state.

1. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined
2. The two cycle command should be issued to the same bank address.
3. If the P/E.C. is active , both cycles are ignored.
4. The Clear Status Register command clears the Status Regist er error bits except when the P/E.C. is busy or suspended.

Table 49. Command interface states - Lock table, next state (1)

1. CI = Command Interface, CR = Configuration Register , EFP = Enhanced Factory Program, Quad EFP = Quadruple
2. If the P/E.C. is active , both cycles are ignored.
3. EFP and Quad EFP exit when Block Address is diffe rent from first Block Address and data is FFFFh.
4. Illegal commands are those not defined in the command set.
5. EFP and Quad EFP are allowed only when Status Register bi t SR0 is set to ‘0’. EFP and Quad EFP are busy if Block

Address is first EFP Address. Any other commands are treated as data.

Table 50. Command interface states - Lock table, next output (1)

1. CI = Command Interface, CR = Configuration Register , EFP = Enhanced Factory Program, Quad EFP = Quadruple

Enhanced Factory Program, P/E. C. = Program/Erase Controller.

1. If the P/E.C. is active , both cycles are ignored.
2. EFP and Quad EFP exit when Block Address is diffe rent from first Block Address and data is FFFFh.
3. Illegal commands are those not defined in the command set.

Revision history M58WRxxxKU, M58WRxxxKL

Revision history

Table 51. Document revision history M58WR016KL part numbers added. Document status promoted from Target Specification to Preliminary Data. 60 ns speed class and 86 MHz frequency added. Program Suspend & Resume flowchart and pseudocode). VDDQ max modified in Table 19: Absolute maximum ratings. VPPLK max modified in Table 23: DC characteristics - voltages. (P+31)h = 6Ah in Table 46: Bank and Erase block region 2 information. Appendix D: Command interface state tables updated. VPP = VPPH in Table 18: Program, erase times and endurance cycles. Table 24: Asynchronous Read ac characteristics. algorithm-specific extended query table. Small text changes. Suspend & Resume flowchart and pseudocode) updated. Write ac characteristics, Chip Enable controlled. Document status promoted from Preliminary Data to full Datasheet. IDD1, IDD5 and IDD6 changed in Table 22.: DC characteristics - currents. Data modified in Table 46.: Bank and Erase block region 2 information. 3-Dec-2007 2 Applied Numonyx branding.