M58PR001LE

M58PR512LE NUMONYX | Alldatasheet

Document overview

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• PDF pages: 123

Technical content

Datasheet sections

• 1 Description
• 2 Signal descriptions
• 2.1 Address inputs (A0-Amax)
• 2.2 Data inputs/outputs (DQ0-DQ15)
• 2.3 Chip Enable (E )
• 2.4 Output Enable (G )
• 2.5 Write Enable (W )
• 2.6 Write Protect (WP )
• 2.7 Reset (RP )
• 2.8 Deep power-down (DPD)
• 2.9 Latch Enable (L )
• 2.10 Clock (K)
• 2.11 Wait (WAIT)
• 2.12 V DD supply voltage
• 2.13 V DDQ supply voltage
• 2.14 V PP program supply voltage
• 2.15 V SS ground
• 2.16 V SSQ ground
• 3 Bus operations
• 3.1 Bus Read
• 3.2 Bus Write
• 3.3 Address Latch
• 3.4 Output Disable
• 3.5 Standby
• 3.6 Reset
• 3.7 Deep power-down (DPD)
• 4 Command interface
• 4.1 Read Array command
• 4.2 Read Status Register command

Datasheet sections

• 5.3.1 Single word program method
• 5.3.2 Buffer program method
• 5.3.3 Buffer enhanced factory program method
• 6 Status register
• 6.1 Control program mode status bit (SR9)
• 6.2 Object program mode status bit (SR8)
• 6.3 Program/Erase Controller status bit (SR7)
• 6.4 Erase suspend status bit (SR6)
• 6.5 Erase status bit (SR5)
• 6.6 Program status bit (SR4)
• 6.8 Program Suspend Status bit (SR2)
• 6.9 Block protection status bit (SR1)
• 6.10 Bank write/multiple word program status bit (SR0)
• 7 Configuration register
• 7.1 Read select bit (CR15)
• 7.2 X latency bits (CR14-CR11)
• 7.3 Wait polarity bit (CR10)
• 7.4 Wait configuration bit (CR8)
• 7.5 Burst length bits (CR2-CR0)
• 8 Enhanced configuration register
• 8.1 Deep power-down mode bit (ECR15)
• 8.2 Deep power-down polarity bit (ECR14)
• 8.3 Output driver control bits (ECR2-ECR0)
• 9 Extended flash array (EFA)
• 10 Read modes
• 10.1 Asynchronous read mode
• 10.2 Synchronous burst read mode
• 10.3 Single synchronous read mode

Features

■ Supply voltage –V DD = 1.7 V to 2.0 V for program, erase and read –V DDQ = 1.7 V to 2.0 V for I/O buffers –V PP = 9 V for fast program ■ Synchronous/asynchronous read – Synchronous burst read mode:

108 MHz, 66 MHz

– Asynchronous page read mode – Random access: 96 ns ■ Programming time – 4.2 µs typical word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple bank memory array:

64 Mbit banks (512 Mb devices)

128 Mbit banks (1 Gb devices)

– Four EFA (extended flash array) blocks of

64 Kbits

■ Dual operations – Program/erase in one bank while read in others – No delay between read and write operations ■ Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency –W P for block lock-down – Absolute Write protection with V PP = VSS ■ Security – 64 bit unique device number – 2112 bit user programmable OTP cells ■ CFI (common flash interface) ■ 100 000 program/erase cycles per block ■ Electronic signature – Manufacturer code: 20h – 512 Mbit device: 8819 – 1 Gbit device: 880F ■ ECOPACK® package available. FBGA TFBGA105 (ZAD) 9 x 11 mm TFBGA107 (ZAC) 8 x 11 mm www.numonyx.com

M58PR512LE, M58PR001LE Contents

M58PR512LE, M58PR001LE Contents

Table 35. Stacked TFBGA107 8 × 11 mm - 9 × 12 active ball array, 0.8 mm pitch,

M58PR512LE, M58PR001LE Description

1 Description

The M58PR512LE and M58PR001LE are 512 Mbit (32 Mbit x 16) and 1 Gbit (64 Mbit x 16) non-volatile flash memories. They are collectively referred to as the M58PRxxxLE in the rest of the document, unless otherwise specified. The M58PRxxxLE may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to speed up factory programming. The M58PRxxxLE has a uniform block architecture and is based on a multilevel cell technology:

• The M58PR512LE has an array of 256 blocks, and is divided into 64 Mbit banks. There are 8 banks each containing 32 blocks of 128 KWords.
• The M58PR001LE has an array of 512 blocks, and is divided into 128 Mbit banks. There are 8 banks each containing 64 blocks of 128 KWords. Each block contains 256 program regions of 1 Kbyte each, that are divided into 32 segments of 16 words. Each segment is split into two halves (A and B), according by the value on address input A3. The memory map is illustrated in Figure 4 and the main array architecture in Figure 5. The multiple bank architecture allows dual operations. While programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architectures are summarized in Table 2 and Table 3, and the memory maps are shown in Figure 4 and . Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage V DD. There is a buffer enhanced factory programming command available to speed up programming. Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the status register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 108 MHz. The device features an automatic standby mode and deep power-down mode. When the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. In this state the power consumption is reduced to the standby value and the outputs are still driven. The DPD (deep power-down) mode starts when the device is properly configured (ECR bit 15 is set) and the DPD signal is asserted. In DPD mode the device has the lowest power consumption.

program or erase. All blocks are locked at power-up. (EFA) divided into 4 blocks of 64 Kbits each. simultaneous operations allowed in the EFA blocks and the main memory array. the Protection Register memory map. Figure 1. Logic diagram

1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE.

Table 1. Signal names

1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE.

Figure 2. TFBGA105 connections (top view through package)

1. Ball A8 is A25 in the M58PR0001LE and it is not connected internally (NC) in the M58PR512LE.

Figure 3. TFBGA107 connections (top view through package)

1. Ball E4 is A25 in the M58PR0001LE and is not connected internally (NC) in the M58PR512LE.

Table 2. M58PR512LE bank architecture Table 3. M58PR001LE bank architecture

Figure 4. Memory map Table 4. EFA memory map

128 Kword0000000h

128 Kword03E0000h

128 Kword1C00000h

128 Kword1FE0000h

128 Kword07E0000h

128 Kword3800000h

128 Kword3FE0000h

Figure 5. Main array architecture

128 Kword block

512 Mbits

M58PR512LE, M58PR001LE Signal descriptions

2 Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals connected to this device.

2.1 Address inputs (A0-Amax)

Amax is the highest order address input. Amax is A24 in the M58PR512LE and A25 in the M58PR001LE. The address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the Program/Erase Controller.

2.2 Data inputs/outputs (DQ0-DQ15)

The data I/O output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation.

2.3 Chip Enable (E )

The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V ILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.

2.4 Output Enable (G )

The Output Enable input controls data outputs during the bus read operation of the memory.

2.5 Write Enable (W )

The Write Enable input controls the bus write operation of the memory’s command interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable, whichever occurs first.

2.6 Write Protect (WP )

Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V IL, the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. When Write Protect is at VIH, the lock-down is disabled and the locked-down blocks can be locked or unlocked (refer to Table 21: Lock status).

Signal descriptions M58PR512LE, M58PR001LE

2.7 Reset (RP )

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode, this means the outputs are high impedance and the current consumption is reduced to the reset supply current I DD2. Refer to Table 26: DC characteristics - currents for the value of IDD2. After Reset, all blocks are in the locked state and the configuration register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3 V logic without any additional circuitry, and can be tied to V RPH (refer to Table 27: DC characteristics - voltages).

2.8 Deep power-down (DPD)

The deep power-down input is used to put the device in deep power-down mode. When the device is in standby mode and the enhanced configuration register bit ECR15 is set, asserting the deep power-down input will cause the memory to enter the deep power- down mode. When the device is in the deep power-down mode, the memory cannot be modified and the data is protected. The polarity of the DPD pin is determined by ECR14. The deep power-down input is active Low by default.

2.9 Latch Enable (L )

Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at V IL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.

2.10 Clock (K)

The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge when Latch Enable is at V IL. Clock is ignored during asynchronous read and in write operations.

2.11 Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at V IH, Output Enable is at VIH, or Reset is at VIL. It can be configured to be active during the wait cycle or one data cycle in advance.

M58PR512LE, M58PR001LE Signal descriptions

2.12 V DD supply voltage

VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase).

2.13 V DDQ supply voltage

VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently of VDD. VDDQ can be tied to VDD or can use a separate supply. VDDQ is sampled at the beginning of program/erase operations. If VDDQ is lower than VLKOQ, the device is reset.

2.14 V PP program supply voltage

VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0 V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Tables 26 and 27, DC characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If V PP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the program/erase algorithm is completed.

2.15 V SS ground

VSS ground is the reference for the core supply. It must be connected to the system ground.

2.16 V SSQ ground

VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS. Note: Each device in a system should have V DD, VDDQ and VPP decoupled with a 0.1 µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 11: AC measurement load circuit. The PCB track widths should be sufficient to carry the required V PP program and erase currents.

Bus operations M58PR512LE, M58PR001LE

3 Bus operations

There are seven standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby, Reset and deep power-down. See Table 5: Bus operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus write operations.

3.1 Bus Read

Bus Read operations are used to output the contents of the memory array, the Electronic signature, the status register and the common flash interface. Both Chip Enable and Output Enable must be at V IL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Section 4: Command interface). See figures 12, 13, 14 and 15, Read AC waveforms, and tables 28 and 29, Read AC characteristics, for details of when the output becomes valid.

3.2 Bus Write

Bus Write operations write commands to the memory or latch input data to be programmed. A Bus Write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the Write operation by toggling Latch Enable. In this case the Latch Enable should be tied to V IH during the Bus Write operation. See figures 17 and 18, Write AC waveforms, and tables 30 and 31, Write AC characteristics, for details of the timing requirements.

3.3 Address Latch

Address Latch operations input valid addresses. Both Chip Enable and Latch Enable must be at V IL during Address Latch operations. The addresses are latched on the rising edge of Latch Enable.

3.4 Output Disable

The outputs are high impedance when the Output Enable is at VIH.

M58PR512LE, M58PR001LE Bus operations

3.5 Standby

Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power consumption is reduced to the standby level IDD3 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished.

3.6 Reset

During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at V IL. The power consumption is reduced to the reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to V SS during a Program or Erase, this operation is aborted and the memory content is no longer valid.

3.7 Deep power-down (DPD)

The memory enters the deep power-down mode from the Standby mode (RP and E are de- asserted, VIH) by setting ECR15 High (set to ‘1’) and asserting the DPD pin (these two events can be done in any order). The DPD pin polarity is determined by the value of ECR14 when:

• ECR14 is cleared (‘0’) the DPD pin is active Low. The DPD pin is active Low by default.
• ECR14 is set (‘1’), the DPD pin is active High. While in DPD mode, the:
• Values of the configuration register, enhanced configuration register, block lock bits, and bank states are preserved.
• Status register is reset to 80h. If the status register contains errors before entering the DPD mode, the error bits are lost after exiting DPD mode. The device should not be put in deep power-down mode while a program, erase or suspend operation is in progress, otherwise the operation aborts, and the memory contents are no longer valid. The deep power-down mode is exited t DPHEL after de-asserting the DPD pin. Upon exiting the deep power-down mode, the memory reverts to standby mode. If the RP pin is asserted while in DPD mode, the device exits DPD mode after tPHEL and ECR15 is reset to 0.

Table 5. Bus operations (1)

1. The DPD signal polarity depends on the value of the ECR14 bit.
2. WAIT signal polarity is configured us ing the Set Configuration Register command.
3. L can be tied to VIH if the valid address has been previously latched.
4. If ECR15 is set to '0', the device cannot enter the deep power-down mode, even if DPD is asserted.
5. ECR15 has to be set to ‘1’ for the device to enter deep power-down.

4 Command interface

All bus write operations to the memory are interpreted by the command interface. whose output may be read at any time to monitor the progress or the result of the operation. precisely. Any invalid combination of commands are ignored. command for a summary of the command interface. Table 6. Command codes

Command interface M58PR512LE, M58PR001LE

4.1 Read Array command

The Read Array command returns the addressed bank to read array mode. One bus write cycle is required to issue the Read Array command. Once a bank is in read array mode, subsequent read operations output the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank returns to read array mode but the program or erase operation continues. However, the data output from the bank is not guaranteed until the program or erase operation has finished. The read modes of other banks are not affected.

4.2 Read Status Register command

The device contains a status register that monitors program or erase operations. The Read Status Register command reads the contents of the status register for the addressed bank. One bus write cycle is required to issue the Read Status Register command. Once a bank is in read status register mode, subsequent read operations output the contents of the status register. The status register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the status register data. The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read the status register. A Read Array command is required to return the bank to read array mode. See Table 13 for the description of the status register bits.

M58PR512LE, M58PR001LE Command interface

4.3 Read Electronic Signature command

The Read Electronic Signature command reads the manufacturer and device codes, the lock status of the addressed bank, the Protection Register, the configuration register, and the enhanced configuration register. One bus write cycle is required to issue the Read Electronic Signature command. Once a bank is in read electronic signature mode, subsequent read operations in the same bank output the manufacturer code, the device code, the lock status of the addressed bank, the Protection Register, the configuration register, or the enhanced configuration register (see Table 9). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during protection register program operations. Dual operations between the EFA and the electronic signature locations are not allowed (see Table 20: Dual operation limitations for details). If a Read Electronic Signature command is issued to a bank that is executing a program or erase operation the bank goes into read electronic signature mode. Subsequent bus read cycles output the electronic signature data and the Program/Erase Controller continues to program or erase in the background. The Read Electronic Signature command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read the electronic signature. A Read Array command is required to return the bank to read array mode.

4.4 Read CFI Query command

The Read CFI Query command is used to read data from the CFI (common flash interface). One bus write cycle is required to issue the Read CFI Query command. Once a bank is in read CFI query mode, subsequent bus read operations in the same bank output the contents of the CFI. The Read CFI Query command can be issued at any time, even during program or erase operations. If a Read CFI Query command is issued to a bank that is executing a program or erase operation the bank goes into read CFI query mode. Subsequent bus read cycles output the CFI data and the Program/Erase Controller continues to program or erase in the background. The Read CFI Query command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read from the CFI. A Read Array command is required to return the bank to read array mode. Dual operations between the EFA and the CFI memory space are not allowed (see Table 20: Dual operation limitations for details).

Command interface M58PR512LE, M58PR001LE

4.5 Clear Status Register command

The Clear Status Register command can be used to reset (set to ‘0’) all error bits (SR1, SR3, SR4, SR5, SR8 and SR9) in the status register. One bus write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the read mode of the bank. The error bits in the status register do not automatically return to ‘0’ when a new command is issued. The error bits in the status register should be cleared before attempting a new program or erase command.

4.6 Block Erase command

The Block Erase command erases a block. It sets all the bits within the selected block to ’1’, and all previous data in the block is lost. If the block is protected then the erase operation aborts, the data in the block is not changed, and the status register outputs the error. Two bus write cycles are required to issue the command.

• The first bus cycle sets up the Block Erase command.
• The second latches the block address and starts the Program/Erase Controller. If the second bus cycle is not the block erase confirm code, status register bits SR4 and SR5 are set and the command is aborted. Once the command is issued, the bank enters read status register mode and any read operation within the addressed bank outputs the contents of the status register. A Read Array command is required to return the bank to read array mode. During block erase operations the bank containing the block being erased only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command; all other commands are ignored. The block erase operation aborts if Reset, RP , goes to VIL. As data integrity cannot be guaranteed when the block erase operation is aborted, the block must be erased again. Refer to Chapter 11 for detailed information about simultaneous operations allowed in banks not being erased. Typical erase times are provided in Table 22: Program/erase times and endurance cycles. See Appendix C, Figure 27: Block erase and EFA block erase flowchart and pseudocode for a suggested flowchart for using the Block Erase command.

M58PR512LE, M58PR001LE Command interface

4.7 Program command

The Program command programs a single word to the memory array. It is supported only by program regions configured in control program mode. If a Program command is issued to a program region configured in object program mode, the program operation is aborted and the SR4 and SR8 status register bits are set (see Section 5: Program operations). Two bus write cycles are required to issue the Program command.

• The first bus cycle sets up the Program command.
• The second latches the address and data to be programmed and starts the P/EC (Program/Erase Controller). The Program command has to be written to the ’A’ segment halves (address bit A3 = 0) in the 1 Kbyte program region, whereas the data to be programmed is written to the specific address of the bank to be programmed. Once the programming has started, read operations in the bank being programmed output the status register contents. Programming can be performed in one bank at a time, meanwhile the other banks must be in Read or Erase Suspend mode. The status register P/EC bit, SR7, indicates the progress of the program operation. It should be read to check whether the operation has completed or not. After completion of the program operation (SR7 = 1), one of the error bits (SR4, SR3 and SR1) going High means that an error was detecte. Either a failure occurred during programming, V PP is outside the allowed voltage range, or an attempt to program a locked block was made. See Section 6: Status register for detailed information. During a program operation, the bank containing the word being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command; all other commands are ignored. A Read Array command is required to return the bank to read array mode. Refer to Chapter 11 for detailed information about simultaneous operations allowed in banks not being programmed. Typical program times are given in Table 22: Program/erase times and endurance cycles. The program operation aborts if Reset, RP , goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the word must be reprogrammed. See Appendix C, Figure 24: Program and EFA block program flowchart and pseudocode for the flowchart for using the Program command.

Command interface M58PR512LE, M58PR001LE

4.8 Buffer Program command

The Buffer Program command uses the device’s 1 Kbyte write buffer to speed up programming. Up to 1 Kbyte can be loaded into the write buffer and programmed into the specified 1 Kb aligned location in the main array. The Buffer Program command dramatically reduces in-system programming time compared to the standard non-buffered program command. The Buffer Program command is supported in both object program mode and control program mode. When using the Buffer Program command in a region configured in object mode, the start programming address must be aligned to the 1 Kb buffer. When using the Buffer Program command in a region configured in control program mode, the programmed address must be within the ’A’ segment halves of the program region (addresses with A3 = 0) and the ’B’ segment halves of the program region (addresses with A3 = 1) must be filled only with FFFFh data. Before issuing the Buffer Program Setup command, the status register bit SR7 at the bank address should be read to ensure that the buffer is available (SR7=1). Four successive steps are required to issue the Buffer Program command: 1. The first bus write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. 2. The second bus write cycle sets up the number of words to be programmed. Value n is written to the same block address, where n+1 is the number of words to be programmed. The maximum buffer count is 1FF (512 words). 3. Use n+1 bus write cycles to load the address and data for each word into the write buffer. Addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. The start address must be aligned to a 1 Kb boundary. 4. The final bus write cycle confirms the Buffer Program command and starts the program operation. All the addresses used in the buffer program operation must lie within the same block. The buffer program operation does not change the read status of the banks until the Buffer Program Confirm command is issued. The Buffer Program Confirm command changes the read status of the bank to read status register, therefore, after the Buffer Program Confirm command, read operations in the bank output the contents of the status register. Invalid address combinations or failure to follow the correct sequence of bus write cycles sets an error in the status register and aborts the operation without affecting the data in the memory array. If the block being programmed is protected, an error is set in the status register and the operation aborts without affecting the data in the memory array. During buffer program operations the bank being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend commands; all other commands are ignored. Refer to Chapter 11 for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 25: Buffer program flowchart and pseudocode for a suggested flowchart on using the Buffer Program command.

M58PR512LE, M58PR001LE Command interface

4.9 Buffer Enhanced Factory Program command

The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where programming time is critical. This command programs one or more write buffer(s) of 1 Kb to an aligned 1 Kb program region. Once the device enters buffer enhanced factory program mode, the write buffer can be reloaded any number of times as long as the address remains within the same main array block. Only one block can be programmed at a time. When programming a program region configured in control program mode with the Buffer Enhanced Factory Program command, the ’B’ half segment addresses (A3 = 1) should not contain ’0’ values. When writing to a program region configured in object program mode, the B half may contain some ’0’ values. If the number of bytes to program is less than 1 Kbyte, the remaining addresses must be filled with FFFFh. The use of the Buffer Enhanced Factory Program command requires the following operating conditions:

• VPP must be set to VPPH
• VDD must be within operating range
• Ambient temperature TA must be 30 °C ± 10 °C
• The targeted block must be unlocked
• The start address must be aligned with the start of a 1 Kb buffer boundary
• The address must remain the start address throughout programming. Dual operations are not supported during the Buffer Enhanced Factory Program operation, and the command cannot be suspended. The Buffer Enhanced Factory command programs one block at a time. All data to be programmed must be contained in a single block. If the internal address counter is incremented beyond the highest block address, addressing wraps around to the beginning of the block. The Buffer Enhanced Factory Program command consists of three phases: the setup phase, the program and verify phase, and the exit phase (please refer to Table 8: Factor y Program command for detailed information).

4.9.1 Setup phase

The Buffer Enhanced Factory Program command requires two bus write cycles to initiate the command.

• The first bus write cycle sets up the Buffer Enhanced Factory Program command.
• The second bus write cycle confirms the command. After the confirm command is issued, read operations output the contents of the status register. The Read Status Register command must not be issued or it is interpreted as data to program. The status register P/EC bit SR7 should be read to check that the P/EC is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to ‘1’) and the buffer enhanced factory program operation is terminated. See Chapter 6: Status register for details on the error.

Command interface M58PR512LE, M58PR001LE

4.9.2 Program an d verify phase

The program and verify phase requires 512 cycles to program the 512 words to the write buffer. The data is stored sequentially, starting at the first address of the write buffer, until the write buffer is full (512 words). To program less than 512 words, the remaining words should be programmed with FFFFh. Three successive steps are required to issue and execute the program and verify phase of the command. 1. Use one bus write operation to latch the start address and the first word to be programmed. The status register bank write status bit SR0 should be read to check that the P/EC is ready for the next word. 2. Each subsequent word to be programmed is latched with a new bus write operation. The address must remain the start address as the P/EC increments the address location. If any address is given that is not in the same block as the start address, the program and verify phase terminates. status register bit SR0 should be read between each bus write cycle to check the P/EC is ready for the next word. 3. Once the write buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary. The program and verify phase can be repeated, without re-issuing the command, to program additional 512 word locations as long as the address remains in the same block. 4. Finally, after all words, or the entire block have been programmed, write FFFFh to any address outside the block containing the start address to terminate the program and verify phase. Status register bit SR0 must be checked to determine whether the program operation is finished. The status register may be checked for errors at any time but it must be checked after the entire block has been programmed.

4.9.3 Exit phase

When status register P/EC bit SR7 is set to ‘1’ this indicates that the device has exited the buffer enhanced factory program operation. Upon exiting the buffered enhanced factory program algorithm by writing FFFFh to an address outside the block containing the start address, the Read mode of the programmed and addressed banks remains unchanged. A full status register check should be done to ensure that the block has been successfully programmed. See Chapter 6: Status register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm continues to work properly but some degradation in performance is possible. Typical program times are provided in Table 22. See Appendix C, Figure 32: Buffer enhanced factory program flowchart and pseudocode for a suggested flowchart on using the Buffer Enhanced Factory Program command.

M58PR512LE, M58PR001LE Command interface

4.10 Program/Erase Suspend command

The Program/Erase Suspend command pauses a program or block erase operation. The command can be addressed to any bank and is required to restart a suspended operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused, bits SR7, SR6 and/ or SR2 of the status register are set to ‘1’. The following commands are accepted during Program/Erase Suspend: – Program/Erase Resume – Read Array (data from erase-suspended block or program-suspended word is not valid) – Read Status Register – Read Electronic Signature – Read CFI Query – Read EFA – Clear Status Register Additionally, if the suspended operation is a block erase then the following commands are also accepted: – Set Configuration Register – Program (except in erase-suspended block) – Buffer Program (except in erase-suspended blocks) – Block Lock – Block Lock-Down – Block Unlock –P r o g r a m E F A During an erase suspend the block being erased can be protected by issuing the Block Lock or Block Lock-down commands. When the Program/Erase Resume command is issued the operation completes. It is possible to accumulate multiple suspend operations. For example, it is possible to suspend an erase operation, start a program operation, suspend the program operation, and then read the array. If a program command is issued during a block erase suspend, the erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in Read EFA, Read Status Register, Read Electronic Signature or Read CFI Query mode, the bank remains in that mode and outputs the corresponding data. Refer to Chapter 11 for detailed information about simultaneous operations allowed during program/erase suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to V IH. Program/Erase is aborted if Reset, RP, goes to VIL. See Appendix C, Figure 26: Program suspend and resume flowchart and pseudocode for flowcharts for using the Program/Erase Suspend command.

Command interface M58PR512LE, M58PR001LE

4.11 Program/Erase Resume command

The Program/Erase Resume command restarts the program or erase operation suspended by the Program/Erase Suspend command. One bus write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in read status register, read electronic signature or read CFI query mode, the bank remains in that mode and outputs the corresponding data. If a program command is issued during a block erase suspend, then the erase cannot be resumed until the program operation is complete. See Appendix C, Figure 26: Program suspend and resume flowchart and pseudocode and Figure 28: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Program/Erase Resume command.

4.12 Protection Register Program command

The Protection Register Program command programs the user OTP area of the Protection Register and the two Protection Register Locks. The device features 16 OTP areas of 128 bits and one OTP area of 64 bits, as shown in Figure 6: Protection Register memory map. The areas are programmed one word at a time. When shipped, all bits in the area are set to ‘1’. Only the user can program the bits to ‘0’. Two bus write cycles are required to issue the Protection Register Program command.

• The first bus cycle sets up the Protection Register Program command.
• The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller. Read operations to the bank being programmed output the status register content after the program operation has started. Attempting to program a previously-protected Protection Register results in a status register error. The Protection Register Program cannot be suspended. Dual operations between the EFA and the Protection Register memory space are not allowed (see Table 20: Dual operation limitations for details). The two Protection Register locks are used to protect the OTP areas from further modification. The protection of the OTP areas is not reversible. Refer to Figure 6: Protection Register memory map for details on the lock bits. See Appendix C, Figure 31: Protection Register program flowchart and pseudocode for a flowchart for using the Protection Register Program command.

M58PR512LE, M58PR001LE Command interface

4.13 Set Configuration Register command

The Set Configuration Register command writes a new value to the configuration register. Two bus write cycles are required to issue the Set Configuration Register command.

• The first cycle sets up the Set Configuration Register command and the address corresponding to the configuration register content.
• The second cycle writes the configuration register data and the confirm command. The configuration register data must be written as an address during the bus write cycles, such as A0 = CR0, A1 = CR1, …, A15 = CR15. Addresses A16-Amax are ignored. Read operations output the array content after the Set Configuration Register command is issued. The Read Electronic Signature command is required to read the updated contents of the configuration register.

4.14 Block Lock command

The Block Lock command is used to lock a block and prevent program or erase operations from changing the data in it. All blocks are locked after power-up or reset. Two bus write cycles are required to issue the Block Lock command.

• The first bus cycle sets up the Block Lock command.
• The second bus write cycle latches the block address and locks the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 21 shows the lock status after issuing a Block Lock command. Once set, the block lock bits remain set even after a hardware reset or power-down/power- up. They are cleared by a Block Unlock command. Refer to Section 12: Block locking for a detailed explanation. See Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Lock command.

4.15 Block Unlock command

The Block Unlock command unlocks a block, allowing the block to be programmed or erased. Two bus write cycles are required to issue the Block Unlock command.

• The first bus cycle sets up the Block Unlock command.
• The second bus write cycle latches the block address and unlocks the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 21 shows the protection status after issuing a Block Unlock command. Refer to Section 12: Block locking for a detailed explanation and Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Block Unlock command.

Command interface M58PR512LE, M58PR001LE

4.16 Block Lock-down command

The Block Lock-down command locks down a locked or unlocked block. A locked-down block cannot be programmed or erased. The lock status of a locked-down block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two bus write cycles are required to issue the Block Lock-down command.

• The first bus cycle sets up the Block Lock-down command.
• The second bus write cycle latches the block address and locks-down the block. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 21 shows the Lock Status after issuing a Block Lock-down command. Refer to Section 12: Block locking for a detailed explanation and Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Lock-down command.

4.17 Blank Check command

The Blank Check command checks whether a main array block has been completely erased. Only one block at a time can be checked. Two bus cycles are required to issue the Blank Check command:

• The first bus cycle writes the Blank Check command to any address in the block to be checked.
• The second bus cycle writes the Blank Check Confirm command (D0h) to any address in the block to be checked and starts the blank check operation. If the second bus cycle is not Blank Check Confirm, status register bits SR4 and SR5 are set to ‘1’ and the command aborts. Once the command is issued the addressed bank automatically enters the status register mode and further reads within the bank output the status register contents. The only operation permitted during blank check is read status register. Dual operations are not supported while a blank check operation is in progress. Blank check operations cannot be suspended and are not allowed while the device is in program/erase suspend. The SR7 status register bit indicates the status of the blank check operation in progress: SR7 = ‘0’ means that the blank check operation is still ongoing. SR7 = ‘1’ means that the operation is complete. The SR5 status register bit goes High (SR5 = ‘1’) to indicate that a blank check operation has failed. At the end of the operation the bank remains in the Read status register mode until another command is written to the command interface. See Appendix C, Figure 30: Blank check flowchart and pseudocode for a suggested flowchart for using the Blank Check command. Typical Blank Check times are provided in Table 22: Program/erase times and endurance cycles.

M58PR512LE, M58PR001LE Command interface

4.18 Set Enhanced Configur ation Register command

The Set Enhanced Configuration Register command is used to write a new value to the enhanced configuration register. Two bus write cycles are required to issue the Set Enhanced Configuration Register command.

• The first cycle sets up the Set Enhanced Configuration Register command and the address corresponding to the enhanced configuration register contents.
• The second cycle writes the enhanced configuration register data and the Confirm command. The enhanced configuration register data must be written as an address during the bus write cycle, such as A0 = ECR0, A1 = ECR1, …, A15 = ECR15. If the Set Enhanced Configuration Register setup write cycle is not followed by the Set Enhanced Configuration Register Confirm command (04h), status register bits SR4 and SR5 are set. After successfully executing this command, the bank addressed returns to read array state.

4.19 Read EFA Block command

The Read EFA Block command places the addressed bank in the read EFA mode, where all addresses in the addressed bank are remapped to EFA block addresses. When the device is in read EFA mode, the main array blocks in the addressed bank can no longer be accessed until a Read Array command is issued to the bank. One bus write cycle is required to issue the Read EFA Block command. Once a bank is in read EFA mode, subsequent read operations from any address within the EFA block output the EFA data from the EFA block. See Table 4: EFA memory map for details. EFA blocks can be read through asynchronous or single synchronous read operations only. The Asynchronous page read mode cannot be used to read the EFA blocks. If a Read EFA command is issued in a bank that is programming or erasing, the read mode of the bank changes to Read EFA mode.

Command interface M58PR512LE, M58PR001LE

4.20 Program EFA Block command

The Program EFA Block command programs a single word to an EFA block. Two bus write cycles are required to issue the Program EFA Block command.

• The first bus cycle sets up the Program EFA Block command.
• The second cycle latches the address and data to be programmed and starts the Program/Erase Controller. Once the programming has started, read operations in the bank being programmed output the status register contents. Issuing the Program EFA Block command to an address outside the EFA block address range generates a Program Error in the status register (SR4=1). A Read EFA Block command is required to return the bank to Read EFA mode. Refer to Section 11 for detailed information about simultaneous operations allowed in the banks not being programmed. Typical EFA Program times are given in Table 22: Program/erase times and endurance cycles. The program operation aborts if Reset, RP, is at VIL. As data integrity cannot be guaranteed when a program EFA block operation is aborted, the word must be reprogrammed. See Appendix C, Figure 24: Program and EFA block program flowchart and pseudocode for the flowchart for using the Program EFA Block command.

4.21 Erase EFA Block command

The Erase EFA Block command erases an EFA block. It sets all the bits within the selected block to '1', and all previous data in the block is lost. If the EFA block is protected, then the erase operation aborts, the data in the EFA block is not changed, and the status register outputs the error. Two bus write cycles are required to issue the command.

• The first bus cycle sets up the Erase EFA Block command.
• The second latches the EFA block address and starts the Program/Erase Controller. The first cycle brings the EFA plane to the foreground and latches the address of the EFA block to be erased. Reading from the bank when the EFA plane is in the foreground returns the status register. Once the Erase operation has started, read operations in the bank being erased output the status register contents. If the Erase EFA Block Confirm command code is not issued in the second bus cycle, status register bits SR4 and SR5 are set, the command is aborted, and the addressed bank remains in the read status register mode. Issuing the Erase EFA Block command outside the EFA block address range generates an error in the status register (SR5=1). The erase EFA block operation aborts if Reset, RP, is at VIL. As data integrity cannot be guaranteed when the erase EFA block operation is aborted, the block must be erased again. Refer to Section 11: Dual operations and multiple bank architecture section for detailed information about simultaneous operations allowed with array and non-array blocks. Typical erase times are provided in Table 22: Program/erase times and endurance cycles. See Appendix C, Figure 27: Block erase and EFA block erase flowchart and pseudocode for a suggested flowchart for using the Erase EFA Block command.

M58PR512LE, M58PR001LE Command interface

4.22 Suspend EFA Block command

The Suspend EFA Block command pauses a program or erase EFA block operation. The command can be addressed to any bank. The Resume EFA Block command is required to restart the suspended operation. One bus write cycle is required to issue the Suspend EFA Block command. Once the Program/Erase Controller has paused, bits SR7, SR6 and/ or SR2 of the status register are set to '1'. The following commands are accepted during Suspend EFA Block: – Resume EFA Block – Read Array – Read EFA Block (data from erase-suspended blocks or program-suspended words is not valid) – Read Status Register – Read Electronic Signature – Read CFI Query. – Clear Status Register Additionally, if the suspended operation was an erase EFA block operation then the following commands are also accepted: – Set Configuration Register – Program EFA Block (except in the erase-suspended block) – Program and Buffer Program in the main array – Block Lock – Block Lock-down – Block Unlock – EFA Block Lock – EFA Block Lock-down – EFA Block Unlock During Suspend EFA Block the EFA block being erased can be protected by issuing the EFA Block Lock or EFA Block Lock-down commands. When the Resume EFA Block command is issued, the operation is resumed and completes. The suspend EFA block operation can be repeated. For example, it is possible to suspend an erase EFA block operation, to start a program EFA block operation, to suspend the program operation, and then read EFA locations. If a Program EFA Block command is issued during a suspend EFA block operation, the erase EFA block operation cannot be resumed until the program operation has completed. The state of the bank where the command was issued do not change. Refer to Section 11 for detailed information about simultaneous operations allowed during a suspend EFA block operation.

Command interface M58PR512LE, M58PR001LE During a suspend EFA block operation, the device can be placed in standby mode by taking Chip Enable to VIH. Program/erase is aborted if Reset, RP, is VIL. See Appendix C, Figure 26: Program suspend and resume flowchart and pseudocode and Figure 28: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Suspend EFA Block command.

4.23 Resume EFA Block command

The Resume EFA Block command restarts the program or erase EFA block operation suspended by the Suspend EFA Block command. One bus write cycle is required to issue the command. The command can be issued to any address. The Resume EFA Block command does not change the read mode of the banks. If a Program EFA Block command is issued while an erase EFA block operation has been suspended, then the erase operation cannot be resumed until the program operation has completed. See Appendix C, Figure 26: Program suspend and resume flowchart and pseudocode and Figure 28: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Resume EFA Block command.

4.24 Lock EFA Block command

The Lock EFA Block command is used to lock an EFA block and prevent program or erase operations from changing the data in it. All EFA blocks are locked after power-up or reset. Two bus write cycles are required to issue the Lock EFA Block command.

• The first bus cycle sets up the Lock EFA Block command.
• The second bus cycle latches the Block address and locks the block. The lock status can be monitored for each EFA block using the Read Electronic Signature command. Once set, the block lock bits remain set even after a hardware reset or a power-down/ power-up sequence. They are cleared by an Unlock EFA Block command. Program or erase operations to a locked EFA block generates an error in the status register (SR1=1). Refer to Section 12: Block locking for a detailed explanation. See Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Lock EFA Block command.

M58PR512LE, M58PR001LE Command interface

4.25 Unlock EFA Block command

The Unlock EFA Block command unlocks an EFA block, allowing the EFA block to be programmed or erased. Two bus write cycles are required to issue the Unlock EFA Block command.

• The first bus cycle sets up the Unlock EFA Block command.
• The second bus write cycle latches the block address and unlocks the block. The lock status can be monitored for each EFA block using the Read Electronic Signature command. Refer to Section 12: Block locking for a detailed explanation and to Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Unlock EFA Block command.

4.26 Lock-down EFA Block command

The Lock-down EFA Block command locks down a locked or unlocked EFA block. A locked-down EFA block cannot be programmed or erased. The lock status of a locked- down EFA block cannot be changed when WP is Low, VIL. When WP is High, VIH, the lock- down function is disabled and the locked EFA blocks can be individually unlocked by issuing the Unlock EFA Block command. Two bus write cycles are required to issue the Lock-down EFA Block command.

• The first bus cycle sets up the Lock-down EFA Block command.
• The second bus write cycle latches the block address and locks down the block. The lock status can be monitored for each EFA block using the Read Electronic Signature command. Locked-down EFA blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 21 shows the lock status after issuing a Lock-down EFA Block command. Refer to Section 12: Block locking for a detailed explanation and to Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Lock-down EFA Block command.

Table 7. Standard commands

1. X = Don't care, WA = Word Address in targeted bank, RD = Read Data, SRD = Status Register Data, ESD = Electronic

enhanced configuration register Data.

1. Must be same bank as in the first cy cle. The signature addresses are listed in Table 9.
2. Any address within the bank can be used.
3. n+1 is the number of words to be programmed.

Table 8. Factory Program command (1)

1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address, X = Don’t care.
2. Any address within the bank can be used.
3. The program/verify phase can be executed any number of times as long as the data is programmed to the same block.
4. WA 1 is the start address, NOT BA1 = Not Block Address of WA1.

Table 9. Electronic signature codes

512 Mbit

1 Gbit 880F

1. CR = configuration regist er, ECR = enhanced configuration register, PRLD = Protection Register Lock Data.

Command interface M58PR512LE, M58PR001LE Figure 6. Protection Register memory map Table 10. Protection Register locks

Description

Bit 0 Preprogrammed to protect unique device number, address 81h to 84h in PR0 Bit 1 Protects 64 bits of OTP area, address 85h to 88h in PR0 Bits 2 to 15 Reserved Lock 2 89h Bit 0 Protects 128 bits of OTP area PR1 Bit 1 Protects 128 bits of OTP area PR2 Bit 2 Protects 128 bits of OTP area PR3 ---- ---- Bit 13 Protects 128 bits of OTP area PR14 Bit 14 Protects 128 bits of OTP area PR15 Bit 15 Protects 128 bits of OTP area PR16 AI07563 User Programmable OTP Unique device number Protection Register Lock 1 0 88h88h 85h 84h 81h 80h User Programmable OTP PROTECTION REGISTERS User Programmable OTP 1043297513 12 1011 8 61415 PR1 PR16 PR0 89h 8Ah 91h 102h 109h

M58PR512LE, M58PR001LE Program operations

5 Program operations

The M58PR512LE and M58PR001LE have innovative features specially developed to improve the storage flexibility and efficiency of NOR flash memory arrays. Data and code can be stored more efficiently by using the right combination of program methods and program modes. There are two types of program methods that use commands that consist of one or more sequential bus write operations interpreted by the command interface:

• Single word program method, which uses the Program command.
• Buffered program method, which uses either the Buffer Program command or the Buffer Enhanced Factory Program command. There are two program modes:
• Control program mode
• Object program mode. The control program mode supports the two program methods, whereas the object program mode only supports the buffered program method. This new logical organization of program operations is made possible by the device architecture, and, in particular, by the new concept of program regions.

5.1 Program regions

Each flash memory block is divided into 256 program regions (see Figure 7: Program regions configured in control or object program mode). Erase operations have a block granularity, whereas program operations have a program region granularity. The user can configure each program region to be programmed either in the control program mode or in the object program mode. A given block can contain program regions configured in the control program mode and others configured in the object program mode. Special care should be taken when selecting the programming mode for the program regions because once the program regions are configured, their program mode cannot be changed until the entire block is erased. Each program region is split into 32 segments of 32 bytes and each segment is subdivided into two halves, ’A’ and ’B’. Address bit A3 determines whether a bit belongs to the ’A’ half (A3 = 0) or to the ’B’ half (A3 = 1).

Program operations M58PR512LE, M58PR001LE

5.2 Program modes

There are two program modes, which allow the flash memory to store different types of data: control program mode and object program mode.

5.2.1 Control program mode

The control program mode is best suited to the storage of small, dynamic information. Typically such data is contained within one program region and it is frequently updated and/or new data is added to it. Program regions are configured in the control program mode by programming data only to the ’A’ halves (bit A3= 0) of the segments they contain. The ’B’ halves of the segments must remain erased, meaning that they should not contain any zeros (see Figure 7: Program regions configured in control or object program mode). In a program region of 1 Kbyte configured in the control program mode, only 512 bytes of data can be stored. When the program regions are configured in the control program mode, any program method can be used: the single word or the buffered program methods. Once a program region has been configured in the control program mode, if a zero is written to a ’B’ half of one of its segments, the program operation is terminated and an error is generated. The status register bits SR4 and SR9 are set to ‘1’. (Refer to Status register and to Table 12: Relationships between program methods and program modes for details.) The program mode of a program region configured in the control program mode can only be changed by first erasing the block that contains the program region.

5.2.2 Object program mode

The object program mode is best suited to the storage of large amounts of static information. In a program region of 1 Kbyte configured in the object program mode, 1 Kbyte of data can be stored. When a program region is configured in the object program mode, it cannot be re- programmed or have new data added without first erasing the entire block that contains the program region. Program regions are configured in the object program mode simply by programming at least one bit in the ’B’ half (A3 = 1) of one of the segments they contain. If the programmed data is smaller than 1 Kbyte, the unused space remains in the erased state (all the bits set to FFFFh), but can no longer be used to program data. See Figure 7: Program regions configured in control or object program mode. When the program regions are configured in the object program mode, only the buffered program methods can be used. If an attempt is made to use the single word program method, the program operation is aborted and status register error bits SR4 and SR8 are set to ‘1’. (Refer to Status register and to Table 12: Relationships between program methods and program modes, for details.)

Figure 7. Program regions configured in control or object program mode

5.3 Program methods

• Single word program method, which is used to program a single word to a specific address of the memory array.
• Buffered program methods, which can be split into two different methods: – Buffer program method, which uses the device's write buffer to speed up programming. The data is written into the write buffer and then programmed to the specified block address. – Buffer enhanced factory program method, which is developed to speed up programming in manufacturing environments where the programming time is critical. The data is written in the write buffer and then programmed to the specified block. The following sections describe the relationship between program commands and program methods in detail. See Table 12: Relationships between program methods and program modes and Table 11: Program methods available with each program mode. Program region 0

1 Kbyte (512 byte programmable)

1 Kbyte

Program operations M58PR512LE, M58PR001LE

5.3.1 Single word program method

The single word program method is based on the Program command. It is only supported by program regions configured in the control program mode. If the single word program method is attempted in a program region configured in the object program mode, the program operation is aborted and status register bits SR4 and SR8 are set. See Section 4: Command interface for a detailed description of the Program command. In program regions configured in the control program mode, the Program command can be issued several times. Using the single word program method to program one or more bits to '0' in the ’B’ halves of the segments (A3 = 1) of an erased or already programmed program region generates an error:

• In the case of an erased program region, this is considered an illegal operation that sets status register bits SR4 and SR9.
• In the case of an already programmed program region, an error is always generated because: – To be able to write to a program region configured in the object program mode, the entire block that contains the program region must be erased first. – It is not allowed to write to the ’B’ halves of the segments of a program region configured in the control program mode.

5.3.2 Buffer program method

The buffer program method is based on the Buffer Program command and uses a 1 Kbyte write buffer to speed up programming. The data is written to the write buffer and then programmed to the specified main array location. The buffer program method is supported regardless of the program mode of the program regions. When using the buffer program method in a program region configured in the object program mode, the start address must be aligned to the 1 Kbyte write buffer. When using the buffer program method in a program region configured in the control program mode, the address to be programmed must be located inside the ’A’ halves of the program region’s segments (addresses with A3 = 0) and the ’B’ halves of the segments (addresses with A3= 1) must be filled only with FFFFh data. The Buffer Program command can be issued several times to program regions configured in the control program mode. The Buffer Program command can only be issued once in program regions configured in the object program mode. Attempts to program the same program regions by re-issuing the Buffer Program command leads to data corruption. See Section 4: Command interface for a detailed description of the Buffer Program command.

5.3.3 Buffer enhanced factory program method

regardless of the program mode in which they are configured. remaining addresses in the program region must be filled with FFFFh. Table 11. Program methods available with each program mode Table 12. Relationships between program methods and program modes A3 = 1 (’B’ half) Not allowed. A3 = 0 (’A’ half) Subsequent program not allowed.

Status register M58PR512LE, M58PR001LE

6 Status register

The status register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the status register (refer to Section 4.2 for more details on the command itself). To output the contents, the status register is latched and updated on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to V IH. The status register can only be read using single asynchronous or single synchronous reads. Bus read operations from any address within the bank always read the status register during program and erase operations if no Read Array command has been issued. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR9, SR8, SR5, SR4, SR3 and SR1 give information on errors. They are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the status register should be reset before issuing another command. The bits in the status register are summarized in Table 13: Status register bits. Refer to Table 13 in conjunction with the following text descriptions.

6.1 Control program mode status bit (SR9)

The control program mode status bit, SR9, indicates whether an error occurred while writing to a program region that is configured in control program mode. The SR9 bit should be read once the Program/Erase Controller status bit SR7 is set to ‘1’ (Program/Erase Controller inactive). SR9 is set to 1 when the user attempts to program object data in a control mode region. When:

• SR9 = 0, the program operation completed successfully.
• SR9 = 1, the program operation failed. Once set to ‘1’, SR9 can only be cleared by issuing a Clear Status Register command or through a hardware reset. SR9 should be cleared before a new program command is issued, otherwise the new command appears to fail.

M58PR512LE, M58PR001LE Status register

6.2 Object program mo de status bit (SR8)

The object program mode status bit, SR8, indicates whether an error occurred while writing to a program region that was configured in the object program mode. The SR8 bit should be read once the Program/Erase Controller status bit SR7 is set to ‘1’ (Program/Erase Controller inactive). SR8 is set to 1 when the user attempts to rewrite an object mode region. When:

• SR8 = 0, the program operation completed successfully.
• SR8 = 1, the program operation failed. Once set, SR8 can only be cleared by issuing a Clear Status Register command or through a hardware reset. SR8 should be cleared before a new program command is issued, otherwise the new command appears to fail.

6.3 Program/Erase Controller status bit (SR7)

The Program/Erase Controller status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When:

• SR7 = 0, the Program/Erase Controller is active.
• SR7 = 1, the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller status bit is set to ’0’ immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses, the bit is set to ’1’.

6.4 Erase suspend status bit (SR6)

The erase suspend status bit indicates that an erase operation has been suspended in the addressed block. When:

• SR6 = 0, no Program/Erase Suspend command has been issued.
• SR6 = 1, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The erase suspend status bit should only be considered valid when the Program/Erase Controller status bit is set to ’1’ (Program/Erase Controller inactive). SR6 is set within the erase suspend latency time of the Program/Erase Suspend command being issued, therefore, the memory may still complete the operation rather than entering suspend mode. When a Program/Erase Resume command is issued, the erase suspend status bit is reset to ’0’.

Status register M58PR512LE, M58PR001LE

6.5 Erase status bit (SR5)

The erase status bit identifies if there is an error during a block erase operation. When:

• SR5 = 0, no error occurred.
• SR5 = 1, the Program/Erase Controller applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. The erase status bit should be read once the Program/Erase Controller Status bit is set to ’1’ (Program/Erase Controller inactive). Once set, the erase status bit must be cleared by a Clear Status Register command or a hardware reset. This must be done before a new erase command is issued, otherwise the new command appears to fail.

6.6 Program status bit (SR4)

The program status bit identifies if there is an error during a program operation. The program status bit should be read once the Program/Erase Controller status bit is set to ‘1’ (Program/Erase Controller inactive). When:

• SR4 = 0, no error occurred.
• SR4 = 1, the Program/Erase Controller applied the maximum number of pulses to the word and still failed to verify that it programmed correctly. Attempting to program a '1' to an already programmed bit while VPP = VPPH also sets the program status bit to ’1’. If VPP is different from VPPH, SR4 remains set to '0' and the attempt is not shown. Once set to '1', the program status bit must be cleared by a Clear Status Register command or a hardware reset. This must be done before a new program command is issued, otherwise the new command appears to fail.

6.7 V PP status bit (SR3)

The VPP status bit identifies an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an operation. When:

• SR3 = 0, the voltage on the VPP pin is sampled at a valid voltage.
• SR3 = 1, the VPP pin has a voltage that is below the VPP lockout voltage, VPPLK, the memory is protected, and program and erase operations cannot be performed. Once set to ‘1’, the VPP status bit must be cleared by a Clear Status Register command or a hardware reset. This must be done before a new program or erase command is issued, otherwise the new command appears to fail.

M58PR512LE, M58PR001LE Status register

6.8 Program Suspend Status bit (SR2)

The program suspend status bit indicates that a program operation has been suspended in the addressed block. The program suspend status bit is onlyconsidered valid when the Program/Erase Controller status bit is set to ‘1’ (Program/Erase Controller inactive). When:

• SR2 = 0, no Program/Erase Suspend command has been issued.
• SR2 = 1, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. SR2 is set within the program suspend latency time of the Program/Erase Suspend command being issued, therefore, the memory may still complete the operation rather than entering suspend mode. When a Program/Erase Resume command is issued, the program suspend status bit is reset to ‘0’.

6.9 Block protection status bit (SR1)

The block protection status bit dentifies if a program or block erase operation has tried to modify the contents of a locked block. When:

• SR1 = 0, no program or erase operation has been attempted on a locked block.
• SR1 = 1, a program or erase operation has been attempted on a locked block. Once set to ‘1’, the block protection status bit must be cleared by a Clear Status Register command or a hardware reset. This must be done before a new program or erase command is issued, otherwise the new command appears to fail.

6.10 Bank write/multiple word program status bit (SR0)

The bank write status bit indicates if the addressed bank is programming or erasing. The bank write status bit is only considered valid when the Program/Erase Controller status bit SR7 is set to ‘0’. When:

• SR0 = 0 and SR7 = 0, the addressed bank is executing a program or erase operation.
• SR0 = 1 and SR7 = 0, a program or erase operation is being executed in a bank other than the one being addressed. During buffer enhanced factory program operations the multiple word program bit, SR0, shows if the device is ready to accept a new word to be programmed to the memory array. When:
• SR0 = 0, the device is ready for the next word.
• SR0 = 1, the device is not ready for the next word. For further details on how to use the status register, see the flowcharts and pseudocodes provided in Appendix C.

Table 13. Status register bits

1. Logic level '1' is High, '0' is Low.
2. Reserved bits should always be reset to ‘0’.

1 Program error in program region configured in control

0 Program successful

1 Program error in program region configured in object

1 Ready

1 Erase suspended

0 Erase in progress or completed

1 Erase error

0 Erase success

1 Program error

0 Program success

1 Program suspended

0 Program in progress or completed

1 Program/erase on protected block, abort

0 No operation to protected blocks

M58PR512LE, M58PR001LE Configuration register

7 Configuration register

The configuration register configures the type of bus access that the memory performs. Refer to Section 10: Read modes for details on read operations. The configuration register is set through the command interface using the Set Configuration Register command. The configuration register is volatile: after a reset or a power- down/power-up sequence, the register is set for asynchronous read (CR15=1) and all bits return to their default value. The configuration register bits are described in Table 15. They specify the selection of the burst length, burst X latency and the read operation. Refer to Figure 8 and Figure 9 for examples of synchronous burst configurations.

7.1 Read select bit (CR15)

The read select bit, CR15, switches between asynchronous and synchronous read operations. When:

• CR15 = 0: – Read operations in the main array are performed in synchronous burst mode, – Operations to read the status register, electronic signature, CFI and EFA are performed in single synchronous mode (See Section 10.3: Single synchronous read mode for details).
• CR15 = 1: – Read operations in the main array are performed in Asynchronous page mode, – Operations to read the status register, electronic signature, CFI and EFA are performed in asynchronous random access mode. Synchronous burst read can be performed across banks. On reset or power-up the read select bit is set to ’1’ for asynchronous access.

7.2 X latency bits (CR14-CR11)

The X latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X latency bits can only assume the values in Table 15: Configuration register. Table 14 shows how to set the X latency parameter, taking into account the frequency used to read the flash memory in synchronous mode. Refer to Figure 8: X latency and data output configuration example for an example waveform.

7.3 Wait polarity bit (CR10)

• CR10 = 0, the Wait signal is active Low.
• CR10 = 1, the Wait signal is active High. During synchronous burst read mode the Wait signal indicates whether the data output is valid or a Wait state must be inserted.

7.4 Wait configuration bit (CR8)

synchronous burst read mode.

• CR8 = 0, the Wait output pin is asserted during the wait state.
• CR8 = 1, the Wait output pin is asserted one data cycle before the wait state. When WAIT is asserted, data is not valid and when WAIT is de-asserted, data is valid.

7.5 Burst length bits (CR2-CR0)

operation as result of a single address latch cycle. sequentially. In continuous burst mode the burst sequence can cross bank boundaries. necessary before the data is output. indicates that the device needs an internal delay to read the successive words in the array. Table 14. X latency settings

40 MHz 25 ns 4

54 MHz 19 ns 5

66 MHz 15 ns 6

108 MHz 9 ns 10

CR9, CR7, CR6, CR5, CR4 and CR3 are reserved for future use. Table 15. Configuration register

0 Synchronous read

1 Asynchronous read (default at power-on)

0 WAIT is active Low (default)

1 WAIT is active High

1. Reserved bits should be cleared to ‘0’.

0 WAIT is active during wait state

1 WAIT is active one data cycl e before wait state (default)1

111 Continuous (default, no wrap only)

Figure 8. X latency and data output configuration example

1. The settings shown are X latency = 4. t QVK_CPU is the data setup time required by the system CPU.

Table 16. Burst type definition

Figure 9. Wait configuration example

Enhanced configuration register M58PR512LE, M58PR001LE

8 Enhanced configuration register

The ECR (enhanced configuration register) enables the deep power-down mode and configures the output driver strength. It is set through the command interface using the Set Enhanced Configuration Register command. The contents of the ECR can be read by issuing the Read Electronic Signature command, and then by reading from the bank base address + 06h. The ECR is volatile: after a reset or a power-down/power-up sequence the register is set to the default value. The configuration register bits are described in Table 17.

8.1 Deep power-down mode bit (ECR15)

The deep power-down mode bit, ECR15, enable the deep power-down mode. The device can only enter the deep power-down mode from standby, by, in any order, asserting the DPD pin and setting ECR15 to ‘1’. When the device is in the deep power-down mode, de-asserting the DPD pin and/or resetting ECR15 causes the device to revert to standby mode.

8.2 Deep power-down polarity bit (ECR14)

The deep power-down polarity bit sets the polarity of the DPD signal. When:

• ECR14 = 0, the DPD signal is active Low (default).
• ECR14 = 1, the DPD signal is active High.

8.3 Output driver cont rol bits (ECR2-ECR0)

The output driver control bits, ECR0, ECR1, and ECR2 select the output driver impedance best suited to the system requirements. After reset or power-up the output driver control bits are set to the enhanced configuration register default value (ECR2-ECR0 = 100, that is 30 Ω (30 pF) (default)). Optimum performance is only achieved if the output driver impedance is properly configured. Once a configuration has been selected, all data and wait output drivers are set to the same setting. Table 17 lists the output driver impedances at VDDQ/2 and the loads that correspond for each ECR2-ECR0 bit configuration.

Table 17. Enhanced configuration register

0 DPD mode disabled (default)

1 DPD mode enabled

0 DPD is active Low (default)

1 DPD is active High

1. Reserved bits should be cleared to ‘0’.

Extended flash array (EFA) M58PR512LE, M58PR001LE

9 Extended flash array (EFA)

In addition to its main array, the M58PRxxxLE features an EFA that is divided into 4 blocks of 4 KWords each. See Table 4: EFA memory map. The EFA blocks are accessed through a separate set of commands (see Section 4: Command interface for details). The operations available on the EFA blocks are asynchronous random access read, single synchronous read, (single word) program, erase, block lock, block unlock, and block lock- down. The EFA blocks support program/erase suspend and dual operations with the main array. Dual operations between the EFA and the OTP area are not supported. See Table 20: Dual operation limitations for details.

M58PR512LE, M58PR001LE Read modes

10 Read modes

Read operations can be performed in two different ways depending on the settings in the configuration register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchronous. If the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the configuration register. (See Section 7: Configuration register for details). All banks support both asynchronous and synchronous read operations.

10.1 Asynchronous read mode

In asynchronous read operations the clock signal is ‘don’t care’. The device outputs the data corresponding to the address latched, such as the memory array, status register, common flash interface or electronic signature, depending on the command issued. CR15 in the configuration register must be set to ‘1’ for asynchronous operations. Asynchronous read operations can be performed in two different ways, asynchronous random access read and asynchronous page read. Only asynchronous page read takes full advantage of the internal page storage, therefore, different timings are applied. In asynchronous read mode a page of data is internally read and stored in a page buffer. The page has a size of 16 words and is addressed by address inputs A0, A1, A2 and A3. During the page access, Amax-A4 and L must remain stable. The first read operation within the page has a longer access time (tAVQV, Random access time); subsequent reads within the same page have much shorter access times (tAVQV1, page access time). If the page changes then the normal, longer timings apply again. Read operations to read non-array data (status register, electronic signature, CFI) should be performed in asynchronous single word mode. If the asynchronous page mode is used to read non-array data, only the first output data is valid and all subsequent data is not accurately determined. The asynchronous page read mode is not available in the EFA. The device features an automatic standby mode. During asynchronous read operations, after a bus inactivity of 150 ns, the device automatically switches to automatic standby mode. In this state the power consumption is reduced to the standby value and the outputs are still driven. In asynchronous read mode, the Wait signal is always de-asserted. See Table 28: Asynchronous read AC characteristics, Figure 12: Asynchronous random access read AC waveforms and Figure 13: Asynchronous page read AC waveforms for details.

Read modes M58PR512LE, M58PR001LE

10.2 Synchronous burst read mode

In synchronous burst read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous burst read mode can only be used to read the memory array. For other read operations, such as read status register, read CFI, read electronic signature and read EFA, single synchronous read or asynchronous random access read must be used. In synchronous burst read mode, the flow of the data output depends on parameters that are configured in the configuration register. A burst sequence starts at the first clock edge after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR14-CR11 of the configuration register. The number of words to be output during a synchronous burst read operation can be configured as 8 words, 16 words, or continuous (burst length bits CR2-CR0). The Wait signal may be asserted to indicate to the system that an output delay will occur. This delay depends on the starting address of the burst sequence and on the burst configuration. Wait is asserted during the X latency, the wait state, and at the end of an 8- and 16-word burst. It is only de-asserted when output data is valid. In continuous burst read mode, a wait state occurs when crossing the first 16-word boundary if the start address is not 16-word aligned. The Wait signal can be configured to be active Low or active High by setting CR10 in the configuration register. See Table 29: Synchronous read AC characteristics and Figure 14: Synchronous burst read AC waveforms for details.

10.3 Single synchronous read mode

Single synchronous read operations are similar to synchronous burst read operations except that the memory outputs the same data until the burst length requirements are satisfied (according to configuration register bits CR2-CR0). Single synchronous read operations are used to read the EFA, electronic signature, status register, CFI, block protection status, configuration register status or Protection Register. When the addressed bank is in read CFI, read status register or read electronic signature mode, the Wait signal is asserted during the X latency, the wait state and at the end of a 4-, 8- and 16-word burst. It is only de-asserted when the output data is valid. See Table 29: Synchronous read AC characteristics and Figure 14: Synchronous burst read AC waveforms for details.

11 Dual operations and multiple bank architecture

from one bank while another bank is being programmed or erased. to be in program or erase mode). erase operation can be suspended. programming and other banks in read mode. program or erase operations. between the CFI, the OTP , the electronic signature locations and the memory array. Table 18. Dual operations allowed in other banks

Table 19. Dual operations allowed in same bank

1. The Read Array command is accepted but the data ou tput is not guaranteed until the program or erase has
2. Not allowed in the block that is being erased or in the program region that is being programmed.

Table 20. Dual operation limitations CFI data and EFA blocks may be read from any other bank.

M58PR512LE, M58PR001LE Block locking

12 Block locking

The M58PRxxxLE features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection.

• Lock/unlock - this first level allows software only control of block locking.
• Lock-down - this second level requires hardware interaction before locking can be changed.
• VPP ≤ VPPLK - the third level offers a complete hardware protection against program and erase on all blocks. The protection status of each block can be set to locked, unlocked, and locked-down. Table 21 defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 29 shows a flowchart for the locking operations.

12.1 Reading a block’s lock status

The lock status of every block can be read in the read electronic signature mode of the device. To enter this mode issue the Read Electronic Signature command. Subsequent reads at the address specified in Table 9 output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the block lock/unlock status and is set by the Lock command and cleared by the Unlock command. DQ0 is automatically set when entering lock-down. DQ1 indicates the lock-down status and is set by the lock- down command. DQ1 cannot be cleared by software, only by a hardware reset or power- down. The following sections explain the operation of the locking system.

12.2 Locked state

The default status of all blocks on power-up or after a hardware reset is locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any program or erase operations attempted on a locked block returns an error in the status register. The status of a locked block can be changed to unlocked or locked-down using the appropriate software commands. An unlocked block can be locked by issuing the Lock command.

12.3 Unlocked state

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)) can be programmed or erased. All unlocked blocks return to the locked state after a hardware reset or when the device is powered- down. The status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. A locked block can be unlocked by issuing the unlock command.

Block locking M58PR512LE, M58PR001LE

12.4 Lock-down state

Blocks that are locked-down (state (0,1,x)) are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by issuing the Lock-down command. Locked-down blocks revert to the locked state when the device is reset or powered-down. The lock-down function is dependent on the Write Protect, WP , input pin. When WP = 0 (VIL), the blocks in the lock-down state (0,1,x) are protected from program, erase and protection status changes. When WP = 1 (VIH) the lock-down function is disabled (1,1,x) and locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. When the lock-down function is disabled (WP =1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. When WP = 0 blocks that were previously locked-down return to the Lock-down state (0,1,x) regardless of any changes that were made while WP = 1. Device reset or power-down resets all blocks, including those in lock-down, to the locked state.

12.5 Locking operations during erase suspend

Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next, write the desired lock command sequence to a block and the lock status is changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an Erase Suspend of the same block, the locking status bits are changed immediately, but when the erase is resumed, the erase operation completes. Locking operations cannot be performed during a program suspend.

Table 21. Lock status

1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for

a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL.

1. All blocks are locked at power -up, so the default configuration is 001 or 101 according to WP status.
2. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

13 Program and erase times and endurance cycles

condition. The best scenario is when all the bits in the block are at ‘0’ (pre-programmed). Table 22. Program/erase times and endurance cycles (1) (2)

1. Values are liable to change with the external system-level overhead (command sequence and status

register polling execution).

1. Excludes the time needed to execute the command sequence.
2. This is an average value on the entire device.
3. The first Word Program in a program region will take 115 µs, the subsequent words will take 50 µs to

Table 22. Program/erase times and endurance cycles (1) (2) (continued)

14 Maximum ratings

program and other relevant quality documents. Table 23. Absolute maximum ratings

15 DC and AC parameters

Figure 10. AC measurement I/O waveform Table 24. Operating and AC measurement conditions

Figure 11. AC measurement load circuit Table 25. Capacitance (1)

1. Sampled only, not 100% tested.

Table 26. DC characteristics - currents

512 Mbit 50 160

1 Gbit 70 255

1. The DPD current is measured 40 µs after entering the deep power-down mode.
2. Sampled only, not 100% tested.
3. V DD dual operation current is the sum of read and program or erase currents.

Table 27. DC characteristics - voltages Table 26. DC characteristics - currents (continued)

Figure 12. Asynchronous random access read AC waveforms Notes: 1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE.

1. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported.

Figure 13. Asynchronous page read AC waveforms Notes: 1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE. VALID ADD. VALID ADD.VALID ADD.VALID ADD.

Table 28. Asynchronous read AC characteristics

1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.

Figure 14. Synchronous burst read AC waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.

1. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge.
3. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE.

1. Sampled only, not 100% tested.
2. For other timings please refer to Table 28: Asynchronous read AC characteristics.

Table 29. Synchronous read AC characteristics

Figure 17. Write AC waveforms, write enable controlled

Table 30. Write AC characteristics, write enable controlled (1)

1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept Low.
3. t WHELand tWHLL have this value when reading in the targeted bank or when reading after a Set

Figure 18. Write AC waveforms, Chip Enable controlled Note: 1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE.

Table 31. Write AC characteristics, Chip Enable controlled (1)

1. Sampled only, not 100% tested.
2. t WHEL has this value when reading in the targeted bank or when reading after a Set Configuration Register

operation in a different bank and no changes to the configuration register have been issued, tWHEL is 0 ns.

Figure 19. Reset and power-up AC waveforms Table 32. Reset and power-up AC characteristics

1. The device reset is possible but not guaranteed if t PLPH < 50 ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP to allow proper CPU initialization during power-up or reset.

package and on the inner box label. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK specifications are available at: www.numonyx.com. Figure 22. TFBGA105 9 × 11 mm - 9 × 12 active ball array, 0.8 mm pitch, package

Figure 23. TFBGA107 8 × 11 mm - 9 × 12 active ball array, 0.8 mm pitch, package Table 34. TFBGA105 9 × 11 mm - 9 × 12 active ball array, 0.8 mm pitch, mechanical

17 Part numbering

Devices are shipped from the factory with the memory content bits erased to ’1’. of this device, please contact the Numonyx sales office nearest to you. Table 36. Ordering information scheme ZAD = stacked TFBGA105 D stacked footprint. ZAC= stacked TFBGA107 C stacked footprint.

using the information contained in tables 37, 38, 39 and 40. Table 37. M58PR512LE - bank base addresses

Table 38. M58PR001LE - bank base addresses

Table 39. M58PR512LE - block addresses

Table 40. M58PR001LE - block addresses

Table 40. M58PR001LE - block addresses (continued)

software to upgrade itself when necessary. lowest order data outputs (DQ0-DQ7), and the other outputs (DQ8-DQ15) are set to 0. been written by ST. Issue a Read Array command to return to read mode. Table 41. Query structure overview (1)

1. The flash memory display the CFI data structure w hen CFI Query command is issued. In this table are

Table 42. CFI query identification string

Table 43. CFI query system interface information

Table 44. Device geometry definition

Table 45. Primary algorithm-specific extended query table bit 11 to 29 reserved; undefined bits are ‘0’. optional features follows at the end of the bit-30 field.

Table 46. Protection Register information (P+E)h = 118h 0002h Number of protection register fields in JEDEC ID space. Table 47. Burst Read information page-mode data output width. 0028h for word width to determine the burst data output width. (P-21)h = 12Bh 0007h Synchronous mode read capability configuration 3 Cont.

Table 48. Bank and erase block region information

1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There is one bank region, see tables 37, 38, 39 and 40 in Appendix A.

Table 49. Bank and erase block region 1 information (1)

1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There is one bank region, see tables 37, 38, 39 and 40 in Appendix A.

Table 50. Extended flash array bank and erase block region information

1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There is one EFA bank region.

Table 49. Bank and erase block region 1 information (1) (continued)

Table 51. Extended flash array bank and erase block region 1 information Symmetrically blocked banks have one blocking region(2).

1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There is one EFA bank region.

Figure 24. Program and EFA block program flowchart and pseudocode

1. Any address within the 'A' segment halves (A3=0) in a 1 K byte program region configured in control program mode.

If a Program command is issued to a program region configured in the Object Program mode, SR4 and SR8 are set.

1. Status check of SR1 (protected block), SR3 (V PP invalid) and SR4 (program error) can be made after each program

operation or after a sequence.

1. If an error is found, the status register must be cl eared before further Program/Erase controller operations.

Figure 25. Buffer program flowchart and pseudocode

1. n + 1 is the number of data being programmed. The maximum buffer count is 1FF (512 words).
2. Next Program data is an element belonging to buffer_Progr am[].data; Next Program address is an element belonging to
3. Routine for error check by reading SR3, SR4 and SR1.

Figure 26. Program suspend and resume flowchart and pseudocode

1. The Read Status Register command (Write 70h) can be issu ed just before or just after the Program Resume command.

Figure 27. Block erase and EFA block erase flowchart and pseudocode

1. Any address within the bank can equally be used.
2. If an error is found, the status register must be cleared before further program/erase operations.

Figure 28. Erase suspend and resume flowchart and pseudocode

1. The Read Status Register command (Write 70h) can be is sued just before or just after the Erase Resume command.

Figure 29. Main array and EFA locking operations flowchart and pseudocode

1. Any address within the bank can equally be used.

Figure 30. Blank check flowchart and pseudocode

1. Any address within the bank can equally be used.
2. If an error is found, the status register must be cleared before further program/erase operations.

Figure 31. Protection Register program flowchart and pseudocode

1. Status check of SR1 (protected block), SR3 (V PP invalid) and SR4 (program error) can be made after each program

operation or after a sequence.

1. If an error is found, the status register must be cl eared before further Program/Erase controller operations.

Figure 32. Buffer enhanced factory program flowchart and pseudocode

1. When programming a program region config ured in Control Program mode, ’B’ half segment addresses (A3 = 1) should not
2. BA1 = block containing start address WA1.

Table 52. Command interface states - modify table, next state 1

Table 52. Command interface states - modify table, next state 1 (continued)

Table 53. Command interface states - modify table, next state 2

BEFP Busy BEFP program and verify busy (in block address given matches on BEFP setup command). Table 53. Command interface states - modify table, next state 2 (continued)

Table 54. Command interface states - modify table, next output 1

ECR = enhanced configuration register.

2 The output state shows the type of data that appears at the outputs if the bank address is

register, Read Electronic Signature or Read CFI mode, depending on the command issued. next state does not depend on the bank output state. bank results in undetermined data output.

4 The Clear Status Register command clears the status register error bits except when the

address is the first BEFP address. Any other commands are treated as data. Table 55. Command interface states - modify table, next output 2

M58PR512LE, M58PR001LE Command interface state tables

6 BEFP aborts when the block address is different from the first block address and data are

FFFFh. 7 BEFP Exit when block address is different from first block address and data are FFFFh.

8 During BP setup, while entering the number of words to be programmed and filling the

buffer, the read status of the partition does not change. 9 The BP confirm command changes the read status of the partition to Status Read. 10 Illegal commands are commands not defined in the command set.

Table 56. Document revision history 28-Apr-2006 0.1 Initial release. 1Gb density (M58PR001LE part number) added. Operating and AC measurement conditions. IPP1 unit changed in Table 26: DC characteristics - currents. ratings. Small text changes. command and Section 4.22: Suspend EFA Block command. Table 30: Write AC characteristics, write enable controlled. and Figure 15: Single synchronous read AC waveforms. Document status promoted from Preliminary Data to Datasheet. bank, asynchronous read in another bank” from 80 to 85. IDD2, IDD3, IDD4, IDD6, and IDD8 maximum values inTable 26.