M58LW032D STMICROELECTRONICS | Alldatasheet
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Technical content
32 Mbit (4Mb x8, 2Mb x16, Uniform Block)
Figure 1. Packages
The M58LW032D is a 32 Mbit (4Mb x 8 or 2Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be per- formed using a single low voltage (2.7V to 3.6V) core supply. The memory is divided into 32 blocks of 1Mbit that can be erased independently so it is possible to preserve valid data while old data is erased. Pro- gram and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re- quired to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Regis- ter. The command set required to control the memory is consistent with JEDEC standards. The Write Buffer allows the microprocessor to pro- gram from 1 to 16 Words in parallel, both speeding up the programming and freeing up the micropro- cessor to perform other work. A Word Program command is available to program a single word. Erase can be suspended in order to perform either Read or Program in any other block and then re- sumed. Program can be suspended to Read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cy- cles. The M58LW032D has several security features to increase data protection. ■ Block Protection, where each block can be individually protected against program or erase operations. All blocks are protected during power-up. The protection of the blocks is non- volatile; after power-up the protection status of each block is restored to the state when power was last removed. ■ Program Erase Enable input VPEN , program or erase operations are not possible when the Program Erase Enable input VPEN is low. ■ 128 bit Protection Register, divided into two 64 bit segments: the first contains a unique device number written by ST, the second is user programmable. The user programmable segment can be protected. The Reset/Power-Down pin is used to apply a Hardware Reset to the enabled memory and to set the device in power-down mode. The device features an Auto Low Power mode. If the bus becomes inactive during read operations, the device automatically enters Auto Low Power mode. In this mode the power consumption is re- duced to the Auto Low Power supply current. The STS signal is an open drain output that can be used to identify the Program/Erase Controller sta- tus. It can be configured in two modes: Ready/ Busy mode where a static signal indicates the sta- tus of the P/E.C, and Status mode where a pulsing signal indicates the end of a Program or Block Erase operation. In Status mode it can be used as a system interrupt signal, useful for saving CPU time. The memory is available in TSOP56 (14 x 20 mm) and TBGA64 (10x13mm , 1mm pitch) packages.
Figure 2. Logic Diagram Table 1. Signal Names
Figure 3. TSOP56 Connections
Figure 4. TBGA64 Connections (Top view through package)
Figure 5. Block Addresses
1 Mbit or
128 KBytes
1 Mbit Blocks
64 KWords
See Figure 2, Logic Diagram and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Input (A0).The A0 address input is used to select the higher or lower Byte in X8 mode. It is not used in X16 mode (where A1 is the Lowest Significant bit). Address Inputs (A1-A21).The Address Inputs are used to select the cells to access in the mem- ory array during Bus Read operations either to read or to program data to. During Bus Write oper- ations they control the commands sent to the Command Interface of the Program/Erase Con- troller. The device must be enabled (refer to Table 2, De- vice Enable) when selecting the addresses. The address inputs are latched on the rising edge of Write Enable or on the first edge of Chip Enables E0, E1 or E2 that disable the device, whichever occurs first. Data Inputs/Outputs (DQ0-DQ15).The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. Dur- ing Bus Write operations they represent the com- mands sent to the Command Interface of the Program/Erase Controller. When used to input data or Write commands they are latched on the rising edge of Write Enable or the first edge of Chip Enables E0, E1 or E2 that disable the device, whichever occurs first. When the device is enabled and Output Enable is low, V IL (refer to Table 2, Device Enable), the data bus outputs data from the memory array, the Elec- tronic Signature, the Block Protection status, the CFI Information or the contents of the Status Reg- ister. The data bus is high impedance when the device is deselected, Output Enable is high, V IH, or the Reset/Power-Down signal is low, VIL. When the Program/Erase Controller is active the Ready/ Busy status is given on DQ7. Chip Enables (E0, E1, E2).The Chip Enable in- puts E0, E1 and E2 activate the memory control logic, input buffers, decoders and sense amplifi- ers. The device is selected at the first edge of Chip Enables E0, E1 or E2 that enable the device and deselected at the first edge of Chip Enables E0, E1 or E2 that disable the device. Refer to Table 2, Device Enable for more details. When the Chip Enable inputs deselect the memo- ry, power consumption is reduced to the Standby level, I DD1 . Output Enable (G).The Output Enable, G, gates the outputs through the data output buffers during a read operation. When Output Enable, G, is at VIH the outputs are high impedance. Write Enable (W).The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data can be latched on the rising edge of Write En- able. Reset/Power-Down (RP ).The Reset/Power- Down pin can be used to apply a Hardware Reset to the memory. A Hardware Reset is achieved by holding Reset/ Power-Down Low, VIL, for at least tPLPH . When Reset/Power-Down is Low, VIL, the Status Regis- ter information is cleared and the power consump- tion is reduced to power-down level. The device is deselected and outputs are high impedance. If Re- set/Power-Down goes low, V IL,during a Block Erase, a Write to Buffer and Program or a Block Protect/Unprotect the operation is aborted and the data may be corrupted. In this case the STS pin stays low, V IL, for a maximum timing of tPLPH + tPH- BH, until the completion of the Reset/Power-Down pulse. After Reset/Power-Down goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHQV . Note that STS does not fall during a reset, see Ready/Busy Output section. In an application, it is recommended to associate Reset/Power-Down pin, RP, with the reset signal of the microprocessor. Otherwise, if a reset opera- tion occurs while the memory is performing an Erase or Program operation, the memory may out- put the Status Register information instead of be- ing initialized to the default Asynchronous Random Read. Byte/Word Organization Select (BYTE ).The Byte/Word Organization Select pin is used to switch between the x8 and x16 bus widths of the memory. When Byte/Word Organization Select is Low, V IL, the memory is in x8 mode, when it is High, VIH, the memory is in x16 mode. Status/(Ready/Busy) (STS).The STS signal is an open drain output that can be used to identify the Program/Erase Controller status. It can be configured in two modes: ■ Ready/Busy - the pin is Low, VOL , during Program and Erase operations and high impedance when the memory is ready for any Read, Program or Erase operation. ■ Status - the pin gives a pulsing signal to indicate the end of a Program or Block Erase operation. After power-up or reset the STS pin is configured in Ready/Busy mode. The pin can be configured for Status mode using the Configure STS com- mand. When the Program/Erase Controller is idle, or sus- pended, STS can float High through a pull-up re-
one, or more, of the memories is busy). and data may become corrupt. supply to the internal core of the memory device. tied to VDD or can use a separate supply. would result in data corruption. ure 8, AC Measurement Load Circuit. Table 2. Device Enable Note: For single device operations, E2 and E1 can be connected to VSS .
ory defaults to Read Array mode (Page Read). Flash Interface and the Block Protection Status. when the output becomes valid. abling the device (refer to Chip Enable section). (refer to Table 2, Device Enable). IH, during the Bus Write operation. of the Output Enable or Write Enable inputs. Table 3. Bus Operations Note: 1. DQ8-DQ15 are High Z in x8 mode.
- X = Don’t Care VIL or VIH.
Read operations in the M58LW032D are asyn- chronous. The device outputs the data corre- sponding to the address latched, that is the memory array, Status Register, Common Flash In- terface, Electronic Signature or Block Protection Status depending on the command issued. During read operations, if the bus is inactive for a time equivalent to t AVQV , the device automatically enters Auto Low Power mode. In this mode the in- ternal supply current is reduced to the Auto Low Power supply current, IDD5 . The Data Inputs/Out- puts will still output data if a Bus Read operation is in progress. Read operations can be performed in two different ways, Random Read (where each Bus Read oper- ation accesses a different Page) and Page Read. In Page Read mode a Page of data is internally read and stored in a Page Buffer. Each memory page is a 4 Words or 8 Bytes and has the same A3-A21. In x8 mode only A0, A1 and A2 may change, in x16 mode only A1 and A2 may change. The first read operation within the Page has the normal access time (t AVQV ), subsequent reads within the same Page have much shorter access times (t AVQV1 ). If the Page changes then the nor- mal, longer timings apply again. See Figure 10, Page Read AC Waveforms and Table 16, Page Read AC Characteristics for de- tails on when the outputs become valid.
All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. The Commands are summarized in Table 4, Commands. Refer to Table 4 in conjunction with the text descriptions below. After power-up or a Reset operation the memory enters Read mode. Read Memory Array Command. The Read Mem- ory Array command is used to return the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and re- turn the memory to Read mode. Once the com- mand is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory array. After power-up or a reset the mem- ory defaults to Read Array mode (Page Read). While the Program/Erase Controller is executing a Program, Erase, Block Protect, Blocks Unprotect or Protection Register Program operation the memory will not accept the Read Memory Array command until the operation completes. Read Electronic Signature Command.The Read Electronic Signature command is used to read the Manufacturer Code, the Device Code, the Block Protection Status and the Protection Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the com- mand is issued subsequent Bus Read operations read the Manufacturer Code, the Device Code, the Block Protection Status or the Protection Register until another command is issued. Refer to Table 6, Read Electronic Signature, Tables 7 and 8, Word and Byte-wide Read Protection Register and Fig- ure 6, Protection Register Memory Map for infor- mation on the addresses. Read Query Command. The Read Query Com- mand is used to read data from the Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash In- terface Memory Area. See Appendix B, Tables 24, 25, 26, 27, 28 and 29 for details on the information contained in the Common Flash Interface (CFI) memory area. Read Status Register Command.The Read Sta- tus Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read opera- tions read the Status Register until another com- mand is issued. The Status Register information is present on the output data bus (DQ1-DQ7) when the device is en- abled and Output Enable is Low, V IL. See the section on the Status Register and Table 10 for details on the definitions of the Status Reg- ister bits Clear Status Register Command.The Clear Sta- tus Register command can be used to reset bits SR1, SR3, SR4 and SR5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new Write to Buffer and Program, Erase, Block Protect, Block Unprotect or Protection Register Program com- mand is issued. If any error occurs then it is essen- tial to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command. Block Erase Command. The Block Erase com- mand can be used to erase a block. It sets all of the bits in the block to ‘1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address and starts the Program/Erase Con- troller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Erase times are given in Table 9. See Appendix C, Figure 18, Block Erase Flow- chart and Pseudo Code, for a suggested flowchart on using the Block Erase command. Word/Byte Program Command. The Word/ Byte Program command is used to program a sin- gle Word or Byte in the memory array. Two Bus Write operations are required to issue the com- mand; the first write cycle sets up the Word Pro- gram command, the second write cycle latches the address and data to be programmed, and starts the Program/Erase Controller. If the block being programmed is protected an er- ror will be set in the Status Register and the oper- ation will abort without affecting the data in the memory array. The block must be unprotected us- ing the Blocks Unprotect command or by using the
Blocks Temporary Unprotect feature of the Reset/ Power-Down pin, RP. Write to Buffer and Program Command.The Write to Buffer and Program command is used to program the memory array. Up to 16 Words/32 Bytes can be loaded into the Write Buffer and programmed into the memory. Each Write Buffer has the same A5-A21 address- es. In Byte-wide mode only A0-A4 may change in Word-wide mode only A1-A4 may change, in . Four successive steps are required to issue the command. 1. One Bus Write operation is required to set up the Write to Buffer and Program Command. Is- sue the set up command with the selected memory Block Address where the program op- eration should occur (any address in the block where the values will be programmed can be used). Any Bus Read operations will start to out- put the Status Register after the 1st cycle. 2. Use one Bus Write operation to write the same block address along with the value N on the Data Inputs/Output, where N+1 is the number of Words/Bytes to be programmed. 3. Use N+1 Bus Write operations to load the ad- dress and data for each Word into the Write Buffer. See the constraints on the address com- binations listed below. The addresses must have the same A5-A21. 4. Finally, use one Bus Write operation to issue the final cycle to confirm the command and start the Program operation. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the oper- ation without affecting the data in the memory ar- ray. The Status Register should be cleared before re-issuing the command. If the block being programmed is protected an er- ror will be set in the Status Register and the oper- ation will abort without affecting the data in the memory array. The block must be unprotected us- ing the Blocks Unprotect command. See Appendix C, Figure 16, Write to Buffer and Program Flowchart and Pseudo Code, for a sug- gested flowchart on using the Write to Buffer and Program command. Program/Erase Suspend Command. The Pro- gram/Erase Suspend command is used to pause a Word/Byte Program, Write to Buffer and Program or Erase operation. The command will only be ac- cepted during a Program or an Erase operation. It can be issued at any time during an Erase opera- tion but will only be accepted during a Word Pro- gram or Write to Buffer and Program command if the Program/Erase Controller is running. One Bus Write cycle is required to issue the Pro- gram/Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit (SR7) to find out when the Program/Erase Controller has paused; no other commands will be accepted until the Program/ Erase Controller has paused. After the Program/ Erase Controller has paused, the memory will con- tinue to output the Status Register until another command is issued. During the polling period between issuing the Pro- gram/Erase Suspend command and the Program/ Erase Controller pausing it is possible for the op- eration to complete. Once the Program/Erase Controller Status bit (SR7) indicates that the Pro- gram/Erase Controller is no longer active, the Pro- gram Suspend Status bit (SR2) or the Erase Suspend Status bit (SR6) can be used to deter- mine if the operation has completed or is suspend- ed. For timing on the delay between issuing the Program/Erase Suspend command and the Pro- gram/Erase Controller pausing see Table 9. During Program/Erase Suspend the Read Memo- ry Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Re- sume commands will be accepted by the Com- mand Interface. Additionally, if the suspended operation was Erase then the Write to Buffer and Program, and the Program Suspend commands will also be accepted. When a program operation is completed inside a Block Erase Suspend the Read Memory Array command must be issued to reset the device in Read mode, then the Erase Re- sume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. See Appendix C, Figure 17, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 19, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command. Program/Erase Resume Command. The Pro- gram/Erase Resume command can be used to re- start the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the Pro- gram/Erase Resume command. Once the com- mand is issued subsequent Bus Read operations read the Status Register. Block Protect Command. The Block Protect command is used to protect a block and prevent Program or Erase operations from changing the data in it. Two Bus Write cycles are required to is- sue the Block Protect command; the second Bus Write cycle latches the block address and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read
the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Block Protect operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Block Protection times are given in Table 9. The Block Protection bits are non-volatile, once set they remain set through reset and power- down/power-up. They are cleared by a Blocks Un- protect command. See Appendix C, Figure 20, Block Protect Flow- chart and Pseudo Code, for a suggested flowchart on using the Block Protect command. Blocks Unprotect Command. The Blocks Un- protect command is used to unprotect all of the blocks. Two Bus Write cycles are required to issue the Blocks Unprotect command; the second Bus Write cycle starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Block Unprotect operation the memory will only accept the Read Status Register com- mand. All other commands will be ignored. Typical Block Protection times are given in Table 9. See Appendix C, Figure 21, Block Unprotect Flow- chart and Pseudo Code, for a suggested flowchart on using the Block Unprotect command. Protection Register Program Command.The Protection Register Program command is used to Program the 64 bit user segment of the Protection Register. Two write cycles are required to issue the Protection Register Program command. ■ The first bus cycle sets up the Protection Register Program command. ■ The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. The user-programmable segment can be locked by programming bit 1 of the Protection Register Lock location to ‘0’ (see Table 7 and x for Word- wide and Byte-wide protection addressing). Bit 0 of the Protection Register Lock location locks the factory programmed segment and is programmed to ‘0’ in the factory. The locking of the Protection Register is not reversible, once the lock bits are programmed no further changes can be made to the values stored in the Protection Register, see Figure 6, Protection Register Memory Map. At- tempting to program a previously protected Pro- tection Register will result in a Status Register error. The Protection Register Program cannot be sus- pended. See Appendix C, Figure 22, Protection Register Program Flowchart and Pseudo Code, for the flowchart for using the Protection Register Program command. Configure STS Command. The Configure STS command is used to configure the Status/(Ready/Busy) pin. After power-up or re- set the STS pin is configured in Ready/Busy mode. The pin can be configured in Status mode using the Configure STS command (refer to Sta- tus/(Ready/Busy) section for more details. Two write cycles are required to issue the Config- ure STS command. ■ The first bus cycle sets up the Configure STS command. ■ The second specifies one of the four possible configurations (refer to Table 5, Configuration Codes): – Ready/Busy mode – Pulse on Erase complete mode – Pulse on Program complete mode – Pulse on Erase or Program complete mode The device will not accept the Configure STS com- mand while the Program/Erase controller is busy or during Program/Erase Suspend. When STS pin is pulsing it remains Low for a typical time of 250ns. Any invalid Configuration Code will set an error in the Status Register.
Table 4. Commands PRD Protection Register Data, CC Configuration Code.
- For Identifier addresses and data refer to Table 6, Read Electronic Signature.
- For Query Address and Data refer to Appendix B, CFI.
Table 5. Configuration Codes
- When STS pin is pulsing it remains Low for a typical time of 250ns.
of a Block Erase or Program operation.
Table 6. Read Electronic Signature Note: 1. SBA is the Start Base Address of each block, PRD is Protection Register Data.
- Base Address, refer to Figure 6 and Tables 7 and 8 for more information.
- A0 is not used in Read Electronic Signature in either x8 or x16 mode. The data is always presented on the lower byte in x16 mode.
Figure 6. Protection Register Memory Map Table 7. Word-Wide Read Protection Register
0 Factory (Unique ID) 10000001
1 Factory (Unique ID) 10000010
2 Factory (Unique ID) 10000011
3 Factory (Unique ID) 10000100
4 U s e r 10000101
5 U s e r 10000110
6 U s e r 10000111
7 U s e r 10001000
Table 8. Byte-Wide Read Protection Register
1 Factory (Unique ID) 10000001
2 Factory (Unique ID) 10000010
3 Factory (Unique ID) 10000010
4 Factory (Unique ID) 10000011
5 Factory (Unique ID) 10000011
6 Factory (Unique ID) 10000100
7 Factory (Unique ID) 10000100
8 U s e r 10000101
9 U s e r 10000101
Table 9. Program, Erase Times and Program Erase Endurance Cycles Note: 1. Typical values measured at room temperature and nominal voltages.
- Sampled, but not 100% tested.
- Effective byte programming time 6µs, effective word programming time 12µs.
- Maximum value measured at worst case conditions for both temperature and VDD after 100,000 program/erase cycles.
- Maximum value measured at worst case conditions for both temperature and VDD .
The Status Register provides information on the current or previous Program, Erase, Block Protect or Blocks Unprotect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Reg- ister command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Blocks Unprotect and Program/Erase Re- sume commands. The Status Register can be read from any address. The contents of the Status Register can be updat- ed during an Erase or Program operation by tog- gling the Output Enable pin or by dis-activating and then reactivating the device (refer to Table 2, Device Enable). Status Register bits SR5, SR4, SR3 and SR1 are associated with various error conditions and can only be reset with the Clear Status Register com- mand. The Status Register bits are summarized in Table 10, Status Register Bits. Refer to Table 10 in conjunction with the following text descriptions. Program/Erase Controller Status (SR7).The Pro- gram/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low, V OL , the Program/Erase Controller is active and all other Status Register bits are High Imped- ance; when the bit is High, V OH , the Program/ Erase Controller is inactive. The Program/Erase Controller Status is Low im- mediately after a Program/Erase Suspend com- mand is issued until the Program/Erase Controller pauses. After the Program/Erase Controller paus- es the bit is High. During Program, Erase, Block Protect and Blocks Unprotect operations the Program/Erase Control- ler Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Con- troller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status and Block Protection Status bits should be tested for errors. Erase Suspend Status (SR6).The Erase Sus- pend Status bit indicates that an Erase operation has been suspended and is waiting to be re- sumed. The Erase Suspend Status should only be considered valid when the Program/Erase Con- troller Status bit is High (Program/Erase Controller inactive); after a Program/Erase Suspend com- mand is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is Low, V OL , the Program/Erase Controller is active or has com- pleted its operation; when the bit is High, VOH , a Program/Erase Suspend command has been is- sued and the memory is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status (SR5).The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive). When the Erase Status bit is Low, V OL , the mem- ory has successfully verified that the block has erased correctly or all blocks have been unprotect- ed successfully. When the Erase Status bit is High, V OH , the erase operation has failed. De- pending on the cause of the failure other Status Register bits may also be set to High, VOH . ■ If only the Erase Status bit (SR5) is set High, V OH , then the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly or that all the blocks have been unprotected successfully. ■ If the failure is due to an erase or blocks unprotect with VPEN low, VOL , then VPEN Status bit (SR3) is also set High, VOH . ■ If the failure is due to an erase on a protected block then Block Protection Status bit (SR1) is also set High, V OH . ■ If the failure is due to a program or erase incorrect command sequence then Program Status bit (SR4) is also set High, V OH . Once set High, the Erase Status bit can only be re- set Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (SR4).The Program Status bit is used to identify a Program or Block Protect fail- ure. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is Low, V OL , the memory has successfully verified that the Write Buffer has programmed correctly or the block is protected. When the Program Status bit is High, V OH , the program or block protect operation has failed. Depending on the cause of the failure other Status Register bits may also be set to High, V OH . ■ If only the Program Status bit (SR4) is set High, VOH , then the Program/Erase Controller has applied the maximum number of pulses to the
byte and still failed to verify that the Write Buffer has programmed correctly or that the Block is protected. ■ If the failure is due to a program or block protect with VPEN low, VOL , then VPEN Status bit (SR3) is also set High, VOH . ■ If the failure is due to a program on a protected block then Block Protection Status bit (SR1) is also set High, VOH . ■ If the failure is due to a program or erase incorrect command sequence then Erase Status bit (SR5) is also set High, V OH . Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. V PEN Status (SR3).The VPEN Status bit can be used to identify if a Program, Erase, Block Protec- tion or Block Unprotection operation has been at- tempted when V PEN is Low, VIL. When the VPEN Status bit is Low, VOL , no Pro- gram, Erase, Block Protection or Block Unprotec- tion operations have been attempted with V PEN Low, VIL, since the last Clear Status Register com- mand, or hardware reset. When the VPEN Status bit is High, VOH , a Program, Erase, Block Protec- tion or Block Unprotection operation has been at- tempted with VPEN Low, VIL. Once set High, the VPEN Status bit can only be re- set by a Clear Status Register command or a hard- ware reset. If set High it should be reset before a new Program, Erase, Block Protection or Block Unprotection command is issued, otherwise the new command will appear to fail. Program Suspend Status (SR2).The Program Suspend Status bit indicates that a Program oper- ation has been suspended and is waiting to be re- sumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is Low, V OL , the Program/Erase Controller is active or has completed its operation; when the bit is High, VOH , a Program/Erase Suspend command has been is- sued and the memory is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is is- sued the Program Suspend Status bit returns Low. Block Protection Status (SR1).The Block Pro- tection Status bit can be used to identify if a Pro- gram or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is Low, V OL , no Program or Erase operations have been at- tempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is High, V OH , a Program (Program Status bit SR4 set High) or Erase (Erase Status bit SR5 set High) operation has been attempted on a protected block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register com- mand or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Reserved (SR0).Bit SR0 of the Status Register is reserved. Its value should be masked.
Table 10. Status Register Bits
Table 11. Absolute Maximum Ratings Note: 1. Maximum one output short-circuited at a time and for no longer than 1 second.
when relying on the quoted parameters. Table 12. Operating and AC Measurement Conditions Figure 7. AC Measurement Input Output Figure 8. AC Measurement Load Circuit Table 13. Capacitance
- Sampled only, not 100% tested.
0.5 VDDQ
Table 14. DC Characteristics
Figure 9. Bus Read AC Waveforms Table 15. Bus Read AC Characteristics.
Figure 10. Page Read AC Waveforms Table 16. Page Read AC Characteristics Note: For other timings see Table 15, Bus Read AC Characteristics.
Figure 11. Write AC Waveform, Write Enable Controlled Table 17. Write AC Characteristics, Write Enable Controlled
Figure 12. Write AC Waveforms, Chip Enable Controlled Table 18. Write AC Characteristics, Chip Enable Controlled.
Figure 13. Reset, Power-Down and Power-Up AC Waveform Table 19. Reset, Power-Down and Power-Up AC Characteristics
Figure 14. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline Note: Drawing is not to scale. Table 20. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data
Figure 15. TBGA64 - 10x13mm, 8 x 8 ball array 1mm pitch, Package Outline Note: Drawing is not to scale. Table 21. TBGA64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, Package Mechanical Data
Table 22. Ordering Information Scheme Note: Devices are shipped from the factory with the memory content bits erased to ’1’. please contact the ST Sales Office nearest to you.
Table 23. Block Addresses
Table 24. Query Structure Overview Note: 1. Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table.
- Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
- SBA is the Start Base Address for each block.
- In x8 mode, A0 must be set to VIL, otherwise 00h will be output.
Table 25. CFI - Query Address and Data Output Note: 1. Query Data are always presented on DQ7-DQ0. DQ15-DQ8 are set to '0'.
- Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
- In x8 mode, A0 must be set to VIL, otherwise 00h will be output.
Table 26. CFI - Device Voltage and Timing Specification Note: 1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.
- Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV.
- In x8 mode, A0 must be set to VIL, otherwise 00h will be output.
Table 27. Device Geometry Definition Note: 1. In x8 mode, A0 must be set to VIL, otherwise 00h will be output. 0029h 52h 00h Organization Sync./Async.
Table 28. Block Status Register Note: 1. BA specifies the block address location, A21-A17.
- In x8 mode, A0 must be set to VIL, otherwise 00h will be output.
0 Block Unprotected
1 Block Protected
0 Last erase operation ended successfully (3)
1 Last erase operation not ended successfully (3)
Table 29. Extended Query information Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.
- In x8 mode, A0 must be set to VIL, otherwise 00h will be output.
Figure 16. Write to Buffer and Program Flowchart and Pseudo Code
Figure 17. Program Suspend & Resume Flowchart and Pseudo Code
Figure 18. Erase Flowchart and Pseudo Code
Figure 19. Erase Suspend & Resume Flowchart and Pseudo Code
Figure 20. Block Protect Flowchart and Pseudo Code
Figure 21. Block Unprotect Flowchart and Pseudo Code
Figure 22. Protection Register Program Flowchart and Pseudo Code
Figure 23. Command Interface and Program Erase Controller Flowchart (a) Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.
Figure 24. Command Interface and Program Erase Controller Flowchart (b)
Figure 25. Command Interface and Program Erase Controller Flowchart (c).
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