M58LW032C STMICROELECTRONICS | Alldatasheet
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32 Mbit (2Mb x16, Uniform Block, Burst)
Figure 1. Packages
M58LW032C is a 32 Mbit (2Mb x16) non-volatile memory that can be read, erased and repro- grammed. These operations can be performed us- ing a single low voltage (2.7V to 3.6V) core supply. On power-up the memory defaults to Read mode with an asynchronous bus where it can be read in the same way as a non-burst Flash memory. The memory is divided into 32 blocks of 1Mbit that can be erased independently so it is possible to preserve valid data while old data is erased. Pro- gram and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re- quired to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Regis- ter. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In asynchronous mode an Address Latch input can be used to latch address- es in Latch Controlled mode. In synchronous burst mode, data is output on each clock cycle at fre- quencies of up to 56MHz. The Write Buffer allows the microprocessor to pro- gram from 1 to 16 Words in parallel, both speeding up the programming and freeing up the micropro- cessor to perform other work. A Word Program command is available to program a single Word. Erase can be suspended in order to perform either Read or Program in any other block and then re- sumed. Program can be suspended to Read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cy- cles. The M58LW032C has several security features to increase data protection. ■ Block Protection, where each block can be individually protected against program or erase operations. All blocks are protected during power-up. The protection of the blocks is non- volatile; after power-up the protection status of each block is restored to the state when power was last removed. ■ Program Erase Enable input VPEN , program or erase operations are not possible when the Program Erase Enable input V PEN is low. ■ Smart Protection, which allows protected blocks to be permanently locked. This feature is not described in the datasheet for security reasons. Please contact STMicroelectronics for further details. ■ 128 bit Protection Register, divided into two 64 bit segments: the first contains a unique device number written by ST, the second is user programmable. The user programmable segment can be protected. The Reset/Power-Down pin is used to apply a Hardware Reset to the memory and to set the de- vice in power-down mode. The device features an Auto Low Power mode. If the bus becomes inactive during Asynchronous Read operations, the device automatically enters Auto Low Power mode. In this mode the power consumption is reduced to the Auto Low Power supply current. The STS signal is an open drain output that can be used to identify the Program/Erase Controller sta- tus. It can be configured in two modes: Ready/ Busy mode where a static signal indicates the sta- tus of the P/E.C, and Status mode where a pulsing signal indicates the end of a Program or Block Erase operation. In Status mode it can be used as a system interrupt signal, useful for saving CPU time. The memory is available in TSOP56 (14 x 20 mm) and TBGA64 (10 x 13mm, 1mm pitch) packages.
Figure 2. Logic Diagram Table 1. Signal Names
Figure 3. TSOP56 Connections
Figure 4. TBGA64 Connections (Top view through package)
Figure 5. Block Addresses Note: Also see Appendix A, Table 25 for a full listing of the Block Addresses.
1 Mbit Blocks
1 Mbit or
64 KWords
See Figure 2, Logic Diagram and Table 11, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A1-A21).The Address Inputs are used to select the cells to access in the mem- ory array during Bus Read operations either to read or to program data to. During Bus Write oper- ations they control the commands sent to the Command Interface of the internal state machine. Chip Enable and Latch Enable must be low when selecting the addresses. The address inputs are latched on the rising edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write operation. The address latch is transparent when Latch Enable is low, V IL. The address is internally latched in an Erase or Program operation. Data Inputs/Outputs (DQ0-DQ15).The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. Dur- ing Bus Write operations they represent the com- mands sent to the Command Interface of the internal state machine. When used to input data or Write commands they are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. When Chip Enable and Output Enable are both low, V IL, the data bus outputs data from the mem- ory array, the Electronic Signature, the Block Pro- tection status, the CFI Information or the contents of the Status Register. The data bus is high imped- ance when the chip is deselected, Output Enable is high, V IH, or the Reset/Power-Down signal is low, VIL. When the Program/Erase Controller is active the Ready/Busy status is given on DQ7. Chip Enable (E).The Chip Enable, E, input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. Chip Enable, E , at VIH deselects the memory and reduces the power consumption to the Standby level, IDD1 . Output Enable (G).The Output Enable, G, gates the outputs through the data output buffers during a read operation. When Output Enable, G , is at VIH the outputs are high impedance. Output Enable, G , can be used to inhibit the data output during a burst read operation. Write Enable (W).The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data can be latched on the rising edge of Write En- able (also see Latch Enable, L Reset/Power-Down (RP).The Reset/Power- Down pin can be used to apply a Hardware Reset to the memory. A Hardware Reset is achieved by holding Reset/ Power-Down Low, VIL, for at least tPLPH . When Reset/Power-Down is Low, VIL, the Status Regis- ter information is cleared and the power consump- tion is reduced to power-down level. The device is deselected and outputs are high impedance. If Re- set/Power-Down goes low, V IL,during a Block Erase, a Write to Buffer and Program or a Block Protect/Unprotect the operation is aborted and the data may be corrupted. In this case the Ready/ Busy pin stays low, V IL, for a maximum timing of tPLPH + tPHRH, until the completion of the Reset/ Power-Down pulse. After Reset/Power-Down goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHQV . Note that Ready/Busy does not fall during a reset, see Ready/Busy Out- put section. In an application, it is recommended to associate Reset/Power-Down pin, RP , with the reset signal of the microprocessor. Otherwise, if a reset opera- tion occurs while the memory is performing an Erase or Program operation, the memory may out- put the Status Register information instead of be- ing initialized to the default Asynchronous Random Read. Latch Enable (L ).The Bus Interface is config- ured to latch the Address Inputs on the rising edge of Latch Enable, L. In synchronous bus operations the address is latched on the active edge of the Clock when Latch Enable is Low, V IL or on the ris- ing of Latch Enable, whichever occurs first. Once latched, the addresses may change without affect- ing the address used by the memory. When Latch Enable is Low, V IL, the latch is transparent. Clock (K).The Clock, K, is used to synchronize the memory with the external bus during Synchro- nous Bus Read operations. The Clock can be con- figured to have an active rising or falling edge. Bus signals are latched on the active edge of the Clock during synchronous bus operations. In Synchro- nous Burst Read mode the address is latched on the first active clock edge when Latch Enable is low, V IL, or on the rising edge of Latch Enable, whichever occurs first. During asynchronous bus operations the Clock is not used. Valid Data Ready (R).The Valid Data Ready output, R, is an open drain output that can be used to identify if the memory is ready to output data or not. The Valid Data Ready output is only active during Synchronous Burst Read operations when the Burst Length is set to Continuous. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready Low, V OL , in-
dicates that the data is not, or will not be valid. Val- id Data Ready in a high-impedance state indicates that valid data is or will be available. Unless Synchronous Burst Read has been select- ed, Valid Data Ready is high-impedance. It may be tied to other components with the same Valid Data Ready signal to create a unique System Ready signal. The Valid Data Ready, R, output has an internal pull-up resistor of approximately 1 MΩ powered from V DDQ , designers should use an external pull- up resistor of the correct value to meet the external timing requirements for Valid Data Ready rising. Refer to Figure 19. Status/(Ready/Busy) (STS).The STS signal is an open drain output that can be used to identify the Program/Erase Controller status. It can be configured in two modes: ■ Ready/Busy - the pin is Low, VOL , during Program and Erase operations and high impedance when the memory is ready for any Read, Program or Erase operation. ■ Status - the pin gives a pulsing signal to indicate the end of a Program or Block Erase operation. After power-up or reset the STS pin is configured in Ready/Busy mode. The pin can be configured for Status mode using the Configure STS com- mand. When the Program/Erase Controller is idle, or sus- pended, STS can float High through a pull-up re- sistor. The use of an open-drain output allows the STS pins from several memories to be connected to a single pull-up resistor (a Low will indicate that one, or more, of the memories is busy). STS is not Low during a reset unless the reset was applied when the Program/Erase controller was active. Ready/Busy can rise before Reset/Power- Down rises. Program/Erase Enable (V PEN ).The Program/ Erase Enable input, VPEN, is used to protect all blocks, preventing Program and Erase operations from affecting their data. Program/Erase Enable must be kept High during all Program/Erase Controller operations, other- wise the operations is not guaranteed to succeed and data may become corrupt. V DD Supply Voltage.VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). V DDQ Supply Voltage.VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD . VDDQ can be tied to VDD or can use a separate supply. It is recommended to power-up and power-down VDD and VDDQ together to avoid any condition that would result in data corruption. VSS Ground. Ground, VSS, is the reference for the core power supply. It must be connected to the system ground. V SSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by VDDQ . VSSQ must be connected to VSS . Note: Each device in a system should have VDD and VDDQ decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, in- herently low inductance capacitors should be as close as possible to the package). See Fig- ure 10, AC Measurement Load Circuit.
not affect Bus Write operations. Flash Interface and the Block Protection Status. Latch Enable and keeping Write Enable High, VIH. istics, for details of the timing requirements. from the Output Enable or Write Enable inputs. Table 2. Bus Operations Note: 1.X = Don’t Care VIL or VIH.
Read operations can be performed in two different ways depending on the settings in the Configura- tion Register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchro- nous; if the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the Configuration Register. (See Configuration Register section for details). On Power-up or after a Hardware Reset the mem- ory defaults to Asynchronous Read mode. Asynchronous Read Modes In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data corre- sponding to the address latched, that is the mem- ory array, Status Register, Common Flash Interface, Electronic Signature or Block Protection Status depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for asynchronous operations. During Asynchronous Read operations, if the bus is inactive for a time equivalent to t AVQV , the de- vice automatically enters Auto Low Power mode. In this mode the internal supply current is reduced to the Auto Low Power supply current, I DD5 . The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Automatic Low Power is only available in Asyn- chronous Read modes. Asynchronous Read operations can be performed in three different ways, Asynchronous Latch Con- trolled Read, Asynchronous Random Read and Asynchronous Page Read. Asynchronous Latch Controlled Read. In Asynchronous Latch Controlled Read opera- tions read the address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without af- fecting the address that the memory uses. A valid bus operation involves setting the desired address on the Address Inputs, setting Chip En- able and Latch Enable Low, V IL and keeping Write Enable High, VIH; the address is latched on the ris- ing edge of Address Latch. Once latched, the Ad- dress Inputs can change. Set Output Enable Low, V IL, to read the data on the Data Inputs/Outputs; see Figure 12, Asynchronous Latch Controlled Read AC Waveforms and Table 16, Asynchro- nous Latch Controlled Read AC Characteristics for details on when the output becomes valid. See Figures 12, Asynchronous Latch Controlled Read AC Waveforms, and Table 16, Asynchro- nous Latch Controlled Read AC Characteristics, for details. Asynchronous Random Read. As the Latch En- able input is transparent when set Low, V IL, Asyn- chronous Random Read operations can be performed by holding Latch Enable Low, VIL throughout the bus operation. See Figures 11, Asynchronous Random Read AC Waveforms, and Table 15, Asynchronous Ran- dom Read AC Characteristics, for details. Asynchronous Page Read. In Asynchronous Page Read mode a Page of data is internally read and stored in a Page Buffer. Each memory page is
4 Words and has the same A3-A22, only A1 and
A2 may change. The first read operation within the Page has the normal access time (t AVQV ), subsequent reads within the same Page have much shorter access times (tAVQV1 ). If the Page changes then the nor- mal, longer timings apply again. See Figures 13, Asynchronous Page Read AC Waveforms, and Table 17, Asynchronous Page Read AC Characteristics, for details. Synchronous Read Modes In Synchronous Read mode the data output is syn- chronized with the clock. CR15 in the Configura- tion Register must be set to ‘0’ for synchronous operations. Synchronous Burst Read. In Synchronous Burst Read mode the data is output in bursts syn- chronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read opera- tions, such as Read Status Register, Read CFI, Read Electronic Signature and Block Protection Status, Single Synchronous Read or Asynchro- nous Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are con- figured in the Configuration Register. A valid Synchronous Burst Read operation begins when the address is set on the Address Inputs, Write Enable is High, V IH, and Chip Enable and Latch Enable are Low, VIL, during the active edge of the Clock. The address is latched on the first ac- tive clock edge when Latch Enable is low, or on the rising edge of Latch Enable, whichever occurs first. The data becomes available for output after the X-latency specified in the Burst Control Regis- ter has expired. The output buffers are activated by setting Output Enable Low, V IL. See Figures 6 and 7 for examples of Synchronous Burst Read operations. The number of Words to be output during a Syn- chronous Burst Read operation can be configured as 4 Words, 8 Words or Continuous (Burst Length
bits CR2-CR0). In Synchronous Continuous Burst Read mode one Burst Read operation can access the entire memory sequentially. If the starting ad- dress is not associated with a page (4 Word) boundary the Valid Data Ready, R, output goes Low, V IL, to indicate that the data will not be ready in time and additional wait-states are required. The Valid Data Ready output timing (bit CR8) can be changed in the Configuration Register. The order of the data output can be modified through the Burst Type bit in the Configuration Register. The burst sequence can be sequential or interleaved. See Table 20, Synchronous Read AC Character- istics and Figure 18 and 19, Synchronous Burst Read AC Waveform for details. Single Synchronous Read.Single Synchro- nous Read operations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Single Syn- chronous Reads are used to read the Status Reg- ister, CFI, Electronic Signature and Block Protection Status.
The Configuration Register is used to configure the type of bus access that the memory will per- form. The Configuration Register bits are de- scribed in Table 3. They specify the selection of the burst length, burst type, burst X and Y laten- cies and the Read operation. See figures 6 and 7 for examples of Synchronous Burst Read configu- rations. The Configuration Register is set through the Command Interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Power-Down mode. The Configuration Register is read using the Read Electronic Signature Command at address 05h. Read Select Bit (CR15).The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to ’1’, Bus Read operations are asynchronous; when the Read Select but is set to ’0’, Bus Read operations are synchronous. On reset or power-up the Read Select bit is set to ’1’ for asynchronous access. X-Latency Bits (CR13-CR11).The X-Latency bits are used during Synchronous Bus Read oper- ations to set the number of clock cycles between the address being latched and the first data be- coming available. For correct operation the X-La- tency bits can only assume the values in Table 3, Configuration Register. Internal Clock Divider Bit (CR10).The Internal Clock Divider Bit is used to divide the internal clock by two. When CR10 is set to ‘1’ the internal clock is divided by two, which effectively means that the X and Y-Latency values are multiplied by two, that is the number of clock cycles between the address being latched and the first data becoming avail- able will be twice the value set in CR13-CR11, and the number of clock cycles between consecutive reads will be twice the value set in CR9. For exam- ple 8-1-1-1 will become 16-2-2-2. When CR10 is set to ‘0’ the internal clock runs normally and the X and Y-Latency values are those set in CR13-CR11 and CR9. Y-Latency Bit (CR9).The Y-Latency bit is used during Synchronous Bus Read operations to set the number of clock cycles between consecutive reads. The Y-Latency value depends on both the X-Latency value and the setting in CR9. When the Y-Latency is 1 the data changes each clock cycle; when the Y-Latency is 2 the data changes every second clock cycle. See Table 3, Configuration Register for valid combinations of the Y-Latency, the X-Latency and the Clock fre- quency. Valid Data Ready Bit (CR8).The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When the Valid Data Ready bit is ’0’ the Valid Data Ready output pin is driven Low for the active clock edge when invalid data is output on the bus. When the Valid Data Ready bit is ’1’ the Valid Data Ready output pin is driven Low one clock cycle prior to invalid data being output on the bus. Burst Type Bit (CR7).The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved ad- dresses; when the Burst Type bit is ’1’ the memory outputs from sequential addresses. See Tables 4, Burst Type Definition, for the sequence of ad- dresses output from a given starting address in each mode. Valid Clock Edge Bit (CR6).The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock is active. Burst Length Bit (CR2-CR0).The Burst Length bits set the maximum number of Words that can be output during a Synchronous Burst Read oper- ation. Table 3, Configuration Register gives the valid combinations of the Burst Length bits that the memory accepts; Tables 4, Burst Type Definition, give the sequence of addresses output from a giv- en starting address for each length. CR5 CR4 and CR3 are reserved for future use.
Table 3. Configuration Register Note: 1. 4 - 2 - 2 - 2 (represents X-Y-Y-Y) is not allowed.
- X latencies can be calculated as: (tAVQV – tLLKH + tQVKH ) + tSYSTEM MARGIN < (X -1) tK. (X is an integer number from 4 to 8 and tK
- Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK.
- tSYSTEM MARGIN is the time margin required for the calculation.
16 CR15 Read Select 1
0 Synchronous Burst Read
1 Asynchronous Bus Read (default at power-up)
15 CR14 Reserved
001 Reserved
010 X-Latency = 4, 4-1-1-1 (use only with Y-Latency = 1)(1)
11 CR10 Internal
0 X and Y -Latencies remains as set in CR13-CR11 and
1 Divides internal clock, X and Y -Latencies multiplied by 2
10 CR9 Y -Latency(3) X
0 Y-Latency = 1
1 Y-Latency = 2
0 R valid Low during valid Clock edge
1 R valid Low one cycle before valid Clock edge
8 CR7 Burst Type X
0 Interleaved
1 Sequential
0 Falling Clock edge
1 Rising Clock edge
111 Continuous
Table 4. Burst Type Definition Figure 6. Burst Configuration X-1-1-1
Figure 7. Burst Configuration X-2-2-2
All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. The Commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the text descriptions below. After power-up or a Reset operation the memory enters Read mode. Synchronous Read operations and Latch Con- trolled Bus Read operations can only be used to read the memory array. The Electronic Signature, CFI or Status Register will be read in asynchro- nous mode or single synchronous burst mode. Once the memory returns to Read Memory Array mode the bus will resume the setting in the Config- uration Register automatically. Read Memory Array Command. The Read Mem- ory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is is- sued the memory remains in Read mode until an- other command is issued. From Read mode Bus Read commands will access the memory array. While the Program/Erase Controller is executing a Program, Erase, Block Protect, Blocks Unprotect or Protection Register Program operation the memory will not accept the Read Memory Array command until the operation completes. Read Electronic Signature Command.The Read Electronic Signature command is used to read the Manufacturer Code, the Device Code, the Block Protection Status, the Configuration Register and the Protection Register. One Bus Write cycle is re- quired to issue the Read Electronic Signature command. Once the command is issued subse- quent Bus Read operations read the Manufacturer Code, the Device Code, the Block Protection Sta- tus, the Configuration Register or the Protection Register until another command is issued. Refer to Table 7, Read Electronic Signature, Table 8, Read Protection Register and Figure 8, Protection Reg- ister Memory Map for information on the address- es. Read Query Command. The Read Query Com- mand is used to read data from the Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash In- terface Memory Area. See Appendix B, Tables 26, 27, 28, 29, 30 and 31 for details on the information contained in the Common Flash Interface (CFI) memory area. Read Status Register Command.The Read Sta- tus Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read opera- tions read the Status Register until another com- mand is issued. The Status Register information is present on the output data bus (DQ1-DQ7) when both Chip En- able and Output Enable are low, V IL. See the section on the Status Register and Table 10 for details on the definitions of the Status Reg- ister bits Clear Status Register Command.The Clear Sta- tus Register command can be used to reset bits SR1, SR3, SR4 and SR5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new Write to Buffer and Program, Erase, Block Protect, Block Unprotect or Protection Register Program com- mand is issued. If any error occurs then it is essen- tial to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command. Block Erase Command. The Block Erase com- mand can be used to erase a block. It sets all of the bits in the block to ‘1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read opera- tions read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Erase times are given in Table 9. See Appendix C, Figure 25, Block Erase Flow- chart and Pseudo Code, for a suggested flowchart on using the Block Erase command. Word Program Command. The Word Program command is used to program a single word in the memory array. Two Bus Write operations are re- quired to issue the command; the first write cycle sets up the Word Program command, the second write cycle latches the address and data to be pro- grammed in the internal state machine and starts the Program/Erase Controller.
If the block being programmed is protected an er- ror will be set in the Status Register and the oper- ation will abort without affecting the data in the memory array. The block must be unprotected us- ing the Blocks Unprotect command. Write to Buffer and Program Command.The Write to Buffer and Program command is used to program the memory array. Up to 16 Words can be loaded into the Write Buffer and programmed into the memory. Each Write Buffer has the same A5-A21 addresses. Four successive steps are required to issue the command. 1. One Bus Write operation is required to set up the Write to Buffer and Program Command. Is- sue the set up command with the selected memory Block Address where the program op- eration should occur (any address in the block where the values will be programmed can be used). Any Bus Read operations will start to out- put the Status Register after the 1st cycle. 2. Use one Bus Write operation to write the same block address along with the value N on the Data Inputs/Output, where N+1 is the number of Words to be programmed. 3. Use N+1 Bus Write operations to load the ad- dress and data for each Word into the Write Buffer. See the constraints on the address com- binations listed below. The addresses must have the same A5-A21. 4. Finally, use one Bus Write operation to issue the final cycle to confirm the command and start the Program operation. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the oper- ation without affecting the data in the memory ar- ray. The Status Register should be cleared before re-issuing the command. If the block being programmed is protected an er- ror will be set in the Status Register and the oper- ation will abort without affecting the data in the memory array. The block must be unprotected us- ing the Blocks Unprotect command. See Appendix C, Figure 23, Write to Buffer and Program Flowchart and Pseudo Code, for a sug- gested flowchart on using the Write to Buffer and Program command. Program/Erase Suspend Command. The Pro- gram/Erase Suspend command is used to pause a Word Program, Write to Buffer and Program or Erase operation. The command will only be ac- cepted during a Program or an Erase operation. It can be issued at any time during an Erase opera- tion but will only be accepted during a Word Pro- gram or Write to Buffer and Program command if the Program/Erase Controller is running. One Bus Write cycle is required to issue the Pro- gram/Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit (SR7) to find out when the Program/Erase Controller has paused; no other commands will be accepted until the Program/ Erase Controller has paused. After the Program/ Erase Controller has paused, the memory will con- tinue to output the Status Register until another command is issued. During the polling period between issuing the Pro- gram/Erase Suspend command and the Program/ Erase Controller pausing it is possible for the op- eration to complete. Once the Program/Erase Controller Status bit (SR7) indicates that the Pro- gram/Erase Controller is no longer active, the Pro- gram Suspend Status bit (SR2) or the Erase Suspend Status bit (SR6) can be used to deter- mine if the operation has completed or is suspend- ed. For timing on the delay between issuing the Program/Erase Suspend command and the Pro- gram/Erase Controller pausing see Table 9. During Program/Erase Suspend the Read Memo- ry Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Re- sume commands will be accepted by the Com- mand Interface. Additionally, if the suspended operation was Erase then the Write to Buffer and Program, and the Program Suspend commands will also be accepted. When a program operation is completed inside a Block Erase Suspend the Read Memory Array command must be issued to reset the device in Read mode, then the Erase Re- sume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. See Appendix C, Figure 24, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 26, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command. Program/Erase Resume Command. The Pro- gram/Erase Resume command can be used to re- start the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the Pro- gram/Erase Resume command. Once the com- mand is issued subsequent Bus Read operations read the Status Register. Set Configuration Register Command.The Set Configuration Register command is used to write a new value to the Burst Configuration Con- trol Register which defines the burst length, type, X and Y latencies, Synchronous/Asynchronous
Read mode and the valid Clock edge configura- tion. Two Bus Write cycles are required to issue the Set Configuration Register command. Once the com- mand is issued the memory returns to Read mode as if a Read Memory Array command had been is- sued. The value for the Configuration Register is pre- sented on A1-A16. CR0 is on A1, CR1 on A2, etc.; the other address bits are ignored. Block Protect Command. The Block Protect command is used to protect a block and prevent Program or Erase operations from changing the data in it. Two Bus Write cycles are required to is- sue the Block Protect command; the second Bus Write cycle latches the block address in the inter- nal state machine and starts the Program/Erase Controller. Once the command is issued subse- quent Bus Read operations read the Status Reg- ister. See the section on the Status Register for details on the definitions of the Status Register bits. During the Block Protect operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Block Protection times are given in Table 9. The Block Protection bits are non-volatile, once set they remain set through reset and power- down/power-up. They are cleared by a Blocks Un- protect command. See Appendix C, Figure 27, Block Protect Flow- chart and Pseudo Code, for a suggested flowchart on using the Block Protect command. Blocks Unprotect Command. The Blocks Un- protect command is used to unprotect all of the blocks. Two Bus Write cycles are required to issue the Blocks Unprotect command; the second Bus Write cycle starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Block Unprotect operation the memory will only accept the Read Status Register com- mand. All other commands will be ignored. Typical Block Protection times are given in Table 9. See Appendix C, Figure 28, Block Unprotect Flow- chart and Pseudo Code, for a suggested flowchart on using the Block Unprotect command. Protection Register Program Command.The Protection Register Program command is used to Program the 64 bit user segment of the Protection Register. The segment is programmed 16 bits at a time. Two write cycles are required to issue the Protection Register Program command. ■ The first bus cycle sets up the Protection Register Program command. ■ The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. The user-programmable segment can be locked by programming bit 1 of the Protection Register Lock location to ‘0’ (see Table 8). Bit 0 of the Pro- tection Register Lock location locks the factory programmed segment and is programmed to ‘0’ in the factory. The locking of the Protection Register is not reversible, once the lock bits are pro- grammed no further changes can be made to the values stored in the Protection Register, see Fig- ure 8, Protection Register Memory Map. Attempt- ing to program a previously protected Protection Register will result in a Status Register error. The Protection Register Program cannot be sus- pended. See Appendix C, Figure 29, Protection Register Program Flowchart and Pseudo Code, for the flowchart for using the Protection Register Program command. Configure STS Command. The Configure STS command is used to configure the Status/(Ready/Busy) pin. After power-up or re- set the STS pin is configured in Ready/Busy mode. The pin can be configured in Status mode using the Configure STS command (refer to Sta- tus/(Ready/Busy) section for more details. Two write cycles are required to issue the Config- ure STS command. ■ The first bus cycle sets up the Configure STS command. ■ The second specifies one of the four possible configurations (refer to Table 6, Configuration Codes): – Ready/Busy mode – Pulse on Erase complete mode – Pulse on Program complete mode – Pulse on Erase or Program complete mode The device will not accept the Configure STS com- mand while the Program/Erase controller is busy or during Program/Erase Suspend. When STS pin is pulsing it remains Low for a typical time of 250ns. Any invalid Configuration Code will set an error in the Status Register.
Table 5. Commands
- Base Address, refer to Figure 8 and Table 8 for more information.
- For Identifier addresses and data refer to table 7, Read Electronic Signature.
- For Query Address and Data refer to Appendix B, CFI.
Table 6. Configuration Codes
- When STS pin is pulsing it remains Low for a typical time of 250ns.
Table 7. Read Electronic Signature Note: 1. SBA is the Start Base Address of each block, BCR is Configuration Register data, PRD is Protection Register Data.
- Base Address, refer to Figure 8 and Table 8 for more information.
Table 8. Read Protection Register of a Block Erase or Program operation.
0 Factory (Unique ID) 1 0 000001
1 Factory (Unique ID) 1 0 000010
2 Factory (Unique ID) 1 0 000011
3 Factory (Unique ID) 1 0 000100
4 U s e r 10000101
5 U s e r 10000110
6 U s e r 10000111
7 U s e r 10001000
Figure 8. Protection Register Memory Map Table 9. Program, Erase Times and Program Erase Endurance Cycles Note: 1. Typical values measured at room temperature and nominal voltages.
- Sampled, but not 100% tested.
- Effective byte programming time 6µs, effective word programming time 12µs.
- Maximum value measured at worst case conditions for both temperature and VDD after 100,000 program/erase cycles.
- Maximum value measured at worst case conditions for both temperature and VDD .
The Status Register provides information on the current or previous Program, Erase, Block Protect or Blocks Unprotect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Reg- ister command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Blocks Unprotect and Program/Erase Re- sume commands. The Status Register can be read from any address. The Status Register can only be read using Asyn- chronous Bus Read or Single Synchronous Read operations. Once the memory returns to Read Memory Array mode the bus will resume the set- ting in the Configuration Register automatically. The contents of the Status Register can be updat- ed during an Erase or Program operation by tog- gling the Output Enable pin or by dis-activating (Chip Enable, V IH) and then reactivating (Chip En- able and Output Enable, VIL) the device. Status Register bits SR5, SR4, SR3 and SR1 are associated with various error conditions and can only be reset with the Clear Status Register com- mand. The Status Register bits are summarized in Table 10, Status Register Bits. Refer to Table 10 in conjunction with the following text descriptions. Program/Erase Controller Status Bit (SR7).The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Sta- tus bit is Low, V OL , the Program/Erase Controller is active and all other Status Register bits are High Impedance; when the bit is High, VOH , the Pro- gram/Erase Controller is inactive. The Program/Erase Controller Status is Low im- mediately after a Program/Erase Suspend com- mand is issued until the Program/Erase Controller pauses. After the Program/Erase Controller paus- es the bit is High. During Program, Erase, Block Protect and Blocks Unprotect operations the Program/Erase Control- ler Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Con- troller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status and Block Protection Status bits should be tested for errors. Erase Suspend Status Bit ( SR6).The Erase Suspend Status bit indicates that an Erase opera- tion has been suspended and is waiting to be re- sumed. The Erase Suspend Status should only be considered valid when the Program/Erase Con- troller Status bit is High (Program/Erase Controller inactive); after a Program/Erase Suspend com- mand is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is Low, V OL , the Program/Erase Controller is active or has com- pleted its operation; when the bit is High, VOH , a Program/Erase Suspend command has been is- sued and the memory is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status Bit (SR5).The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive). When the Erase Status bit is Low, V OL , the mem- ory has successfully verified that the block has erased correctly or all blocks have been unprotect- ed successfully. When the Erase Status bit is High, V OH , the erase operation has failed. De- pending on the cause of the failure other Status Register bits may also be set to High, VOH . ■ If only the Erase Status bit (SR5) is set High, VOH , then the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly or that all the blocks have been unprotected successfully. ■ If the failure is due to an erase or blocks unprotect with V PEN low, VOL , then VPEN Status bit (SR3) is also set High, VOH . ■ If the failure is due to an erase on a protected block then Block Protection Status bit (SR1) is also set High, V OH . ■ If the failure is due to a program or erase incorrect command sequence then Program Status bit (SR4) is also set High, VOH . Once set High, the Erase Status bit can only be re- set Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status Bit (SR4).The Program Status bit is used to identify a Program or Block Protect failure. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is Low, V OL , the memory has successfully verified that the Write Buffer has programmed correctly or the block is protected. When the Program Status bit is High, V OH , the program or block protect operation has
failed. Depending on the cause of the failure other Status Register bits may also be set to High, VOH . ■ If only the Program Status bit (SR4) is set High, V OH , then the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that the Write Buffer has programmed correctly or that the Block is protected. ■ If the failure is due to a program or block protect with V PEN low, VOL , then VPEN Status bit (SR3) is also set High, VOH . ■ If the failure is due to a program on a protected block then Block Protection Status bit (SR1) is also set High, V OH . ■ If the failure is due to a program or erase incorrect command sequence then Erase Status bit (SR5) is also set High, V OH . Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. V PEN Status Bit (SR3).The VPEN Status bit can be used to identify if a Program, Erase, Block Pro- tection or Block Unprotection operation has been attempted when V PEN is Low, VIL. When the VPEN Status bit is Low, VOL , no Pro- gram, Erase, Block Protection or Block Unprotec- tion operations have been attempted with VPEN Low, VIL, since the last Clear Status Register com- mand, or hardware reset. When the VPEN Status bit is High, VOH , a Program, Erase, Block Protec- tion or Block Unprotection operation has been at- tempted with V PEN Low, VIL. Once set High, the VPEN Status bit can only be re- set by a Clear Status Register command or a hard- ware reset. If set High it should be reset before a new Program, Erase, Block Protection or Block Unprotection command is issued, otherwise the new command will appear to fail. Program Suspend Status Bit (SR2).The Pro- gram Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is Low, V OL , the Program/Erase Controller is active or has completed its operation; when the bit is High, VOH , a Program/Erase Suspend command has been is- sued and the memory is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is is- sued the Program Suspend Status bit returns Low. Block Protection Status Bit (SR1).The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is Low, V OL , no Program or Erase operations have been at- tempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is High, V OH , a Program (Program Status bit SR4 set High) or Erase (Erase Status bit SR5 set High) operation has been attempted on a protected block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register com- mand or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Reserved (SR0).SR0 of the Status Register is reserved. Its value should be masked.
Table 10. Status Register Bits
Table 11. Absolute Maximum Ratings
when relying on the quoted parameters. Table 12. Operating and AC Measurement Conditions Figure 9. AC Measurement Input Output Figure 10. AC Measurement Load Circuit Table 13. Capacitance
- Sampled only, not 100% tested.
0.5 VDDQ
Table 14. DC Characteristics
Figure 11. Asynchronous Bus Read AC Waveforms Table 15. Asynchronous Bus Read AC Characteristics.
Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.
Figure 13. Asynchronous Page Read AC Waveforms Table 17. Asynchronous Page Read AC Characteristics Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.
Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable
Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable
Figure 18. Synchronous Burst Read AC Waveform
Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output
- V= Valid output, NV= Not Valid output.
- R is an open drain output with an internal pull up resistor of 1MΩ. Depending on the Valid Data Ready pin capacitance load an
external pull up resistor must be chosen according to the system clock period. Table 20. Synchronous Burst Read AC Characteristics Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.
Figure 20. Reset, Power-Down and Power-up AC Waveform Table 21. Reset, Power-Down and Power-up AC Characteristics
Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline Note: Drawing is not to scale. Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data
Figure 22. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Outline Note: Drawing is not to scale. Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data
Table 24. Ordering Information Scheme Note: Devices are shipped from the factory with the memory content bits erased to ’1’. vice, please contact the ST Sales Office nearest to you.
Table 25. Block Addresses
Table 26. Query Structure Overview Note: 1. Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table.
- Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
- SBA is the Start Base Address for each block.
Table 27. CFI - Query Address and Data Output Note: 1. Query Data are always presented on DQ7-DQ0. DQ15-DQ8 are set to '0'.
- Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
Table 28. CFI - Device Voltage and Timing Specification Note: 1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.
- Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV.
Table 29. Device Geometry Definition 29h 00h Organization Sync./Async.
Table 30. Block Status Register Note: 1. BA specifies the block address location, A21-A17.
0 Block UnProtected
1 Block Protected
0 Last erase operation ended successfully (2)
1 Last erase operation not ended successfully (2)
Table 31. Extended Query information Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.
Figure 23. Write to Buffer and Program Flowchart and Pseudo Code
Figure 24. Program Suspend & Resume Flowchart and Pseudo Code
Figure 25. Erase Flowchart and Pseudo Code
Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code
Figure 27. Block Protect Flowchart and Pseudo Code
Figure 28. Blocks Unprotect Flowchart and Pseudo Code
Figure 29. Protection Register Program Flowchart and Pseudo Code
Figure 30. Command Interface and Program Erase Controller Flowchart (a) Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.
Figure 31. Command Interface and Program Erase Controller Flowchart (b)
Figure 32. Command Interface and Program Erase Controller Flowchart (c).
REVISION HISTORY
Table 32. Document Revision History (revision version 02 equals 2.0). VSSQ signal descriptions modified. 02-Sep-2002 2.2 Figure 12, Asynchronous Latch Controlled Bus Read AC Waveforms, modified. Flowcharts. Lead-free packing options added to Ordering Information Scheme.
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