M58LT128HST

M58LT128HST NUMONYX | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Description
• 2 Signal descriptions
• 2.1 Address inputs (A0-A22)
• 2.2 Data inputs/outputs (DQ0-DQ15)
• 2.3 Chip Enable (E )
• 2.4 Output Enable (G )
• 2.5 Write Enable (W )
• 2.6 Reset (RP )
• 2.7 Latch Enable (L )
• 2.8 Clock (K)
• 2.9 Wait (WAIT)
• 2.11 V DDQ supply voltage
• 2.12 V PP program supply voltage
• 2.13 V SS ground
• 2.14 V SSQ ground
• 3 Bus operations
• 3.1 Bus Read
• 3.2 Bus Write
• 3.3 Address Latch
• 3.4 Output Disable
• 3.5 Standby
• 3.6 Reset
• 4 Command interface
• 4.1 Read Array command
• 4.2 Read Status Register command
• 4.3 Read Electronic Signature command
• 4.4 Read CFI Query command
• 4.5 Clear Status Register command

Datasheet sections

• 6.9 Burst length bits (CR2-CR0)
• 7 Read modes
• 7.1 Asynchronous Read mode
• 7.2 Synchronous Burst Read mode
• 7.2.1 Synchronous Burst Read Suspend
• 7.3 Single Synchronous Read mode
• 8 Dual operations and multiple bank architectu re
• 9 Block protection
• 9.1 Protection status
• 9.2 Protected state
• 9.3 Unprotected state
• 9.4 Protection operations during Erase Suspend
• 10 Program and erase times and endurance cycles
• 11 Maximum rating
• 12 DC and AC parameters
• 13 Package mechanical
• 14 Part numbering

Features

■ Supply voltage –V DD = 1.7 V to 2.0 V for Program, Erase and Read –V DDQ = 2.7 V to 3.6 V for I/O buffers –V PP = 9 V for fast program ■ Synchronous/Asynchronous Read – Synchronous Burst Read mode: 52 MHz – Asynchronous Page Read mode – Random access: 85 ns ■ Synchronous Burst Read Suspend ■ Programming time – 2.5 µs typical word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple bank memory array: 8-Mbit banks – Parameter blocks (top or bottom location) ■ Dual operations – program/erase in one bank while read in others – No delay between Read and Write operations ■ Block protection – All blocks protected at power-up – Any combination of blocks can be protected with zero latency – Absolute write protection with V PP = VSS ■ Security – Software security features – 64-bit unique device number – 2112-bit user programmable OTP Cells ■ Common flash interface (CFI) ■ 100 000 program/erase cycles per block ■ Electronic signature – Manufacturer code: 20h – Top device codes: M58LT128HST: 88D6h – Bottom device codes M58LT128HSB: 88D7h ■ TBGA64 package – ECOPACK® available TBGA64 (ZA) 10 × 13 mm BGA www.numonyx.com

M58LT128HST, M58LT128HSB Contents 5.5 V

Table 27. TBGA64 10 × 13 mm - 8 × 8 active ball array, 1 mm pitch, package

M58LT128HST, M58LT128HSB Description

1 Description

The M58LT128HST/B are 128 Mbit (8 Mbit x 16) non-volatile secure Flash memories. They may be erased electrically at block level and programmed in system on a word-by-word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 2.7 V to 3.6 V VDDQ supply for the Input/Output pins. An optional 9 V VPP power supply is provided to accelerate factory programming. The devices feature an asymmetrical block architecture, with an array of 131 blocks, divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 7 main blocks of 64 Kwords. The multiple bank architecture allows dual operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure 3. The parameter blocks are located at the top of the memory address space for the M58LT128HST, and at the bottom for the M58LT128HSB. Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage V DD. There is a buffer-enhanced factory programming command available to accelerate programming. Program And Erase Commands Are Written To The command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports Synchronous Burst Read and Asynchronous Read from all blocks of the memory array; at power-up the device is configured for Asynchronous Read. In Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to 52 MHz. The Synchronous Burst Read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. The M58LT128HST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency, enabling instant code and data protection. They can be protected individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V PP ≤ VPPLK all blocks are protected against program or erase. All blocks are protected at power- up.

Description M58LT128HST, M58LT128HSB The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 one-time-programmable (OTP) Protection Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment OTP by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register memory map. The M58LT128HST/B also has a full set of software security features that are not described in this datasheet, but are documented in a dedicated application note. For further information, please contact Numonyx. The M58LT128HST/B are offered in a TBGA64, 10 × 13 mm, 1 mm pitch package. They are supplied with all the bits erased (set to ’1’).

Figure 1. Logic diagram Table 1. Signal names

Figure 2. TBGA64 package connections (top view through package)

Figure 3. Memory map Table 2. Bank architecture

8 Main

64 KWord000000h

64 KWord070000h

64 KWord600000h

64 KWord670000h

64 KWord680000h

64 KWord6F0000h

64 KWord700000h

64 KWord770000h

64 KWord780000h

64 KWord7E0000h

16 KWord7F0000h

16 KWord7FC000h

4 Parameter

16 KWord000000h

16 KWord00C000h

64 KWord010000h

64 KWord080000h

64 KWord0F0000h

64 KWord100000h

64 KWord170000h

64 KWord180000h

64 KWord1F0000h

64 KWord7F0000h

7 Main

Signal descriptions M58LT128HST, M58LT128HSB

2 Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.

2.1 Address inputs (A0-A22)

The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the command interface of the Program/Erase Controller.

2.2 Data inputs/outputs (DQ0-DQ15)

The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation.

2.3 Chip Enable (E )

The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V ILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.

2.4 Output Enable (G )

The Output Enable input controls data outputs during the Bus Read operation of the memory.

2.5 Write Enable (W )

The Write Enable input controls the Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.

2.6 Reset (RP )

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current I DD2. Refer to Table 20: DC characteristics - currents, for the value of IDD2. After Reset, all blocks are in the protected state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. When exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs.

M58LT128HST, M58LT128HSB Signal descriptions

2.7 Latch Enable (L )

Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH.

2.8 Clock (K)

The Clock input synchronizes the memory to the microcontroller during Synchronous Read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at V IL. Clock is ignored during Asynchronous Read and in Write operations.

2.9 Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at V IH, Output Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance.

2.10 V DD supply voltage

VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program, and Erase).

2.11 V DDQ supply voltage

VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently from VDD.

2.12 V PP program supply voltage

VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives absolute protection against program or erase, while VPP in the VPP1 range enables these functions (see Tables 20 and 21, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If V PP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed.

Signal descriptions M58LT128HST, M58LT128HSB

2.13 V SS ground

VSS ground is the reference for the core supply. It must be connected to the system ground.

2.14 V SSQ ground

VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS Note: Each device in a system should have V DD, VDDQ and VPP decoupled with a 0.1µF ceramic capacitor close to the pin (high-frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 8: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.

M58LT128HST, M58LT128HSB Bus operations

3 Bus operations

There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 3: Bus operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations.

3.1 Bus Read

Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at V IL to perform a Read operation. The Chip Enable input is used to enable the device. Output Enable is used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 9, 10 and 11 Read AC Waveforms, and Tables 22 and 23 Read AC Characteristics, for details of when the output becomes valid.

3.2 Bus Write

Bus Write operations write commands to the memory or latch input data to be programmed. A Bus Write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the write operation by toggling Latch Enable (when Chip Enable is at V IL). The Latch Enable must be tied to VIH during the Bus Write operation. See Figures 15 and 16, Write AC waveforms, and Tables 24 and 25, Write AC characteristics, for details of the timing requirements.

3.3 Address Latch

Address Latch operations input valid addresses. Both Chip Enable and Latch Enable must be at V IL during Address Latch operations. The addresses are latched on the rising edge of Latch Enable.

3.4 Output Disable

The outputs are high impedance when the Output Enable is at VIH.

3.5 Standby

3.6 Reset

Table 3. Bus operations (1)

1. WAIT signal polarity is configured us ing the Set Configuration Register command.
2. L can be tied to VIH if the valid address has been previously latched.

4 Command interface

All Bus Write operations to the memory are interpreted by the Command Interface. whose output may be read at any time to monitor the progress or the result of the operation. exactly. Any invalid combination of commands is ignored. Table 4. Command codes

Command interface M58LT128HST, M58LT128HSB

4.1 Read Array command

The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read Array mode, subsequent read operations outputs the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank returns to Read Array mode, but the Program or Erase operation continues. However, the data output from the bank is not guaranteed until the Program or Erase operation is finished. The Read modes of other banks are not affected.

4.2 Read Status Register command

The device contains a Status Register that is used to monitor program or erase operations. The Read Status Register command is used to read the contents of the Status Register for the addressed bank. One Bus Write cycle is required to issue the Read Status Register command. Once a bank is in Read Status Register mode, subsequent Read operations output the contents of the Status Register. The Status Register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the Status Register data The Read Status Register command can be issued at any time, even during Program or Erase operations. The Read Status Register command only changes the Read mode of the addressed bank. The Read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Status Register. A Read Array command is required to return the bank to Read Array mode. See Table 9 for the description of the Status Register Bits.

M58LT128HST, M58LT128HSB Command interface

4.3 Read Electronic Signature command

The Read Electronic Signature command is used to read the manufacturer and device codes, the protection status of the addressed bank, the Protection Register, and the Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once a bank is in Read Electronic Signature mode, subsequent Read operations in the same bank output the manufacturer code, the device code, the protection status of the addressed bank, the Protection Register, or the Configuration Register (see Table 8). The Read Electronic Signature command can be issued at any time, even during Program or Erase operations, except during Protection Register Program operations. Dual operations between the parameter bank and the electronic signature location are not allowed (see Table 15: Dual operation limitations for details). If a Read Electronic Signature command is issued to a bank that is executing a Program or Erase operation the bank go into Read Electronic Signature mode. Subsequent Bus Read cycles output the Electronic Signature data and the Program/Erase Controller continues to program or erase in the background. The Read Electronic Signature command only changes the Read mode of the addressed bank. The Read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Electronic Signature. A Read Array command is required to return the bank to Read Array mode.

4.4 Read CFI Query command

The Read CFI Query command is used to read data from the Common Flash Interface (CFI). One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in Read CFI Query mode, subsequent Bus Read operations in the same bank read from the Common Flash Interface. The Read CFI Query command can be issued at any time, even during Program or Erase operations. If a Read CFI Query command is issued to a bank that is executing a Program or Erase operation the bank goes into Read CFI Query mode. Subsequent Bus Read cycles output the CFI data and the Program/Erase controller continues to Program or Erase in the background. The Read CFI Query command only changes the Read mode of the addressed bank. The Read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read from the CFI. A Read Array command is required to return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI memory space are not allowed (see Table 15: Dual operation limitations for details). See Appendix B: Common Flash Interface, Tables 31, 32, 33, 34, 35, 36, 37, 38, 39 and 40 for details on the information contained in the Common Flash Interface memory area.

Command interface M58LT128HST, M58LT128HSB

4.5 Clear Status Register command

The Clear Status Register command can be used to reset (set to ‘0’) all error bits (SR1, 3, 4 and 5) in the Status Register. One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the Read mode of the bank. The error bits in the Status Register do not automatically return to ‘0’ when a new command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command.

4.6 Block Erase command

The Block Erase command is used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the erase operation aborts, the data in the block is not changed, and the Status Register outputs the error. The following two Bus Write cycles are required to issue the command:

• The first bus cycle sets up the Block Erase command.
• The second latches the block address and starts the Program/Erase Controller. If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5 are set and the command is aborted. Once the command is issued, the bank enters Read Status Register mode and any Read operation within the addressed bank outputs the contents of the Status Register. A Read Array command is required to return the bank to Read Array mode. During Block Erase operations the bank containing the block being erased only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and the Program/Erase Suspend command; all other commands are ignored. The Block Erase operation aborts if Reset, RP , goes to VIL. As data integrity cannot be guaranteed when the Block Erase operation is aborted, the block must be erased again. Refer to Chapter 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being erased. Typical erase times are given in Table 16: Program/erase times and endurance cycles. See Appendix C, Figure 23: Block Erase flowchart and pseudo code for a suggested flowchart for using the Block Erase command.

M58LT128HST, M58LT128HSB Command interface

4.7 Blank Check command

The Blank Check command is used to check whether a block has been completely erased. Only one block at a time can be checked. To use the Blank Check command, VPP must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the command and no error is shown in the Status Register. The following two bus cycles are required to issue the Blank Check command:

• The first bus cycle writes the Blank Check command (BCh) to any address in the block to be checked.
• The second bus cycle writes the Blank Check Confirm command (CBh) to any address in the block to be checked and starts the Blank Check operation. If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are set to '1' and the command aborts. Once the command is issued the addressed bank automatically enters the Status Register mode and further reads the Status Register contents within the bank output. The only operation permitted during Blank Check is Read Status Register. Dual operations are not supported while a Blank Check operation is in progress. Blank Check operations cannot be suspended and are not allowed while the device is in Program/Erase Suspend. The SR7 Status Register bit indicates the status of the Blank Check operation in progress: SR7 = '0' means that the Blank Check operation is still ongoing, and SR7 = '1' means that the operation is complete. The SR5 Status Register bit goes High (SR5 = '1') to indicate if the Blank Check operation has failed. At the end of the operation the bank remains in the Read Status Register mode until another command is written to the Command Interface. See Appendix C, Figure 20: Blank Check flowchart and pseudo code for a suggested flowchart for using the Blank Check command. Typical Blank Check times are given in Table 16: Program/erase times and endurance cycles.

Command interface M58LT128HST, M58LT128HSB

4.8 Program command

The Program command is used to program a single word to the memory array. If the block being programmed is protected, then the Program operation aborts, the data in the block is not changed, and the Status Register outputs the error. The following two Bus Write cycles are required to issue the Program Command:

• The first bus cycle sets up the Program command.
• The second latches the address and data to be programmed and starts the Program/Erase Controller. Once the programming has started, Read operations in the bank being programmed output the Status Register content. During a Program operation, the bank containing the word being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend commands; all other commands are ignored. A Read Array command is required to return the bank to Read Array mode. Refer to Chapter 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 16: Program/erase times and endurance cycles. The Program operation aborts if Reset, RP , goes to VIL. As data integrity cannot be guaranteed when the Program operation is aborted, the word must be reprogrammed. See Appendix C, Figure 19: Program flowchart and pseudo code for the flowchart for using the Program command.

M58LT128HST, M58LT128HSB Command interface

4.9 Buffer Program command

The Buffer Program Command makes use of the device’s 32-word Write Buffer to accelerate programming. Up to 32 words can be loaded into the Write Buffer, which can dramatically reduce in-system programming time compared to the standard non-buffered Program command. Four successive steps are required to issue the Buffer Program command: 1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. After the first Bus Write cycle, Read operations in the bank output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = ‘1’). If the buffer is not available (SR7 = ‘0’), re-issue the Buffer Program command to update the Status Register contents. 2. The second Bus Write cycle sets up the number of words to be programmed. Value ”n” is written to the same block address, where n+1 is the number of words to be programmed. 3. Use n+1 Bus Write cycles to load the address and data for each word into the Write Buffer. Addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. Optimum performance is obtained when the start address corresponds to a 32-word boundary. 4. The final Bus Write cycle confirms the Buffer Program command and starts the program operation. All the addresses used in the Buffer Program operation must lie within the same block. Invalid address combinations or an incorrect sequence of Bus Write cycles sets an error in the Status Register and aborts the operation without affecting the data in the memory array. If the block being programmed is protected an error is set in the Status Register, and the operation aborts without affecting the data in the memory array. During Buffer Program operations the bank being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and the Program/Erase Suspend command; all other commands are ignored. Refer to Chapter 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 21: Buffer Program flowchart and pseudo code for a suggested flowchart on using the Buffer Program command.

Command interface M58LT128HST, M58LT128HSB

4.10 Buffer Enhanced Factory Program command

The Buffer Enhanced Factory Program command has been specially developed to accelerate programming in manufacturing environments where the programming time is critical. It is used to program one or more Write Buffer(s) of 32 words to a block. Once the device enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. If the block being programmed is protected, then the Program operation aborts, the data in the block is not changed and the Status Register outputs the error. The use of the Buffer Enhanced Factory Program command requires the following operating conditions:

• VPP must be set to VPPH
• VDD must be within operating range
• Ambient temperature TA must be 30°C ± 10°C
• The targeted block must be unprotected
• The start address must be aligned with the start of a 32-word buffer boundary
• The address must remain the Start Address throughout programming. Dual operations are not supported during the Buffer Enhanced Factory Program operation and the command cannot be suspended. The Buffer Enhanced Factory Program Command consists of three phases: the Setup Phase, the Program and Verify Phase, and the Exit Phase. Refer to Table 6: Factor y commands for detailed information.

4.10.1 Setup phase

The Buffer Enhanced Factory Program command requires the following two Bus Write cycles to initiate the command.

• The first Bus Write cycle sets up the Buffer Enhanced Factory Program command.
• The second Bus Write cycle confirms the command. After the Confirm command is issued, Read operations output the contents of the Status Register. The read Status Register command must not be issued, othewise it is interpreted as data to program. The Status Register Program/Erase Controller bit SR7 should be read to check that the Program/Erase Controller is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program operation is terminated. See Chapter 5: Status Register for details on the error.

M58LT128HST, M58LT128HSB Command interface

4.10.2 Program and verify phase

The program and verify phase requires 32 cycles to program the 32 words to the Write Buffer. The data is stored sequentially, starting at the first address of the Write Buffer, until the Write Buffer is full (32 words). To program less than 32 words, the remaining words should be programmed with FFFFh. The following three successive steps are required to issue and execute the program and verify phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first word to be programmed. The Status Register Bank Write status bit SR0 should be read to check that the Program/Erase Controller is ready for the next word. 2. Each subsequent word to be programmed is latched with a new Bus Write operation. The address must remain the start address as the Program/Erase Controller increments the address location. If any address is given that is not in the same block as the start address, the program and verify phase terminates. Status Register bit SR0 should be read between each Bus Write cycle to check that the Program/Erase Controller is ready for the next word. 3. Once the Write Buffer is full, the data is programmed sequentially to the memory array. After the Program operation, the device automatically verifies the data and reprograms, if necessary. The program and verify phase can be repeated, without re-issuing the command, to program additional 32 word locations as long as the address remains in the same block. 4. Finally, after all words, or the entire block has been programmed, write one Bus Write operation to any address outside the block containing the start address, to terminate program and verify phase. Status Register bit SR0 must be checked to determine whether the Program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed.

4.10.3 Exit phase

Status Register Program/Erase Controller bit SR7 set to ‘1’ indicates that the device has exited the Buffer Enhanced Factory Program operation and returned to Read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See Section Table 5: Status Register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded, the internal algorithm continues to work properly but some degradation in performance is possible. Typical program times are given in Table 16. See Appendix C, Figure 27: Buffer Enhanced Factory Program flowchart and pseudo code for a suggested flowchart on using the Buffer Enhanced Factory Program command.

Command interface M58LT128HST, M58LT128HSB

4.11 Program/Erase Suspend command

The Program/Erase Suspend command is used to pause a Program or Block Erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One Bus Write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused, bits SR7, SR6, and/or SR2 of the Status Register are set to ‘1’. The following commands are accepted during Program/Erase Suspend: – Program/Erase Resume – Read Array (data from erase-suspended blocks or program-suspended words is not valid) – Read Status Register – Read Electronic Signature – Read CFI Query In addition, if the suspended operation is a Block Erase, then the following commands are also accepted: – Clear Status Register – Program (except in erase-suspended blocks) – Buffer Program (except in erase suspended blocks) – Block Protect – Block Unprotect – Set Configuration Register During an Erase Suspend, the block being erased can be protected by issuing the Block Protect command. When the Program/Erase Resume command is issued, the operation completes. It is possible to accumulate multiple suspend operations. For example, suspend an Erase operation, start a Program operation, suspend the Program operation, and then read the array. If a Program command is issued during a Block Erase Suspend, the Erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature, or Read CFI Query mode, the bank remains in that mode and outputs the corresponding data. Refer to Section Table 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in Standby mode by driving Chip Enable to V IH. Program/Erase is aborted if Reset, RP, goes to VIL. See Appendix C, Figure 22: Program Suspend & Resume flowchart and pseudo code and Figure 24: Erase Suspend & Resume flowchart and pseudo code for flowcharts for using the Program/Erase Suspend command.

M58LT128HST, M58LT128HSB Command interface

4.12 Program/Erase Resume command

The Program/Erase Resume command is used to restart the Program or Erase operation suspended by the Program/Erase Suspend command. One Bus Write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the Read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature, or Read CFI Query mode, the bank remains in that mode and outputs the corresponding data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the program operation has completed. See Appendix C, Figure 22: Program Suspend & Resume flowchart and pseudo code and Figure 24: Erase Suspend & Resume flowchart and pseudo code for flowcharts for using the Program/Erase Resume command.

4.13 Protection Register Program command

The Protection Register Program command is used to program the user segments of the Protection Register and the two Protection Register Locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown in Figure 4: Protection Register memory map. The segments are programmed one word at a time. When shipped, all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. The following two Bus Write cycles are required to issue the Protection Register Program command:

• The first bus cycle sets up the Protection Register Program command.
• The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the Program operation has started. Attempting to program a previously protected Protection Register results in a Status Register error. The Protection Register Program cannot be suspended. Dual operations between the Parameter Bank and the Protection Register memory space are not allowed (see Table 15: Dual operation limitations for details). The two Protection Register Locks are used to protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 4: Protection Register memory map and Table 8: Protection Register locks for details on the Lock bits. See Appendix C, Figure 26: Protection Register Program flowchart and pseudo code for a flowchart for using the Protection Register Program command.

Command interface M58LT128HST, M58LT128HSB

4.14 Set Configuration Register command

The Set Configuration Register command is used to write a new value to the Configuration Register. The following two Bus Write cycles are required to issue the Set Configuration Register command.

• The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content.
• The second cycle writes the Configuration Register data and the Confirm command. The Configuration Register data must be written as an address during the bus write cycles, such as A0 = CR0, A1 = CR1, …, A15 = CR15. Addresses A16-A22 are ignored. Read operations output the array content after the Set Configuration Register command is issued. The Read Electronic Signature command is required to read the updated contents of the Configuration Register.

4.15 Block Protect command

The Block Protect command is used to protect a block and prevent Program or Erase operations from changing the data in it. All blocks are protected after power-up or reset. The following two Bus Write cycles are required to issue the Block Protect command:

• The first bus cycle sets up the Block Protect command.
• The second Bus Write cycle latches the block address and protects the block. Once the command has been issued, subsequent Bus Read operations read the Status Register. The protection status can be monitored for each block using the Read Electronic Signature command. Refer to Section 9: Block protection for a detailed explanation. See Appendix C, Figure 25: Protect/Unprotect operation flowchart and pseudo code for a flowchart for using the Block Protect command.

4.16 Block Unprotect command

The Block Unprotect command is used to unprotect a block, allowing the block to be programmed or erased. The following two Bus Write cycles are required to issue the Block Unprotect command:

• The first bus cycle sets up the Block Unprotect command.
• The second Bus Write cycle latches the block address and unprotects the block. Once the command has been issued, subsequent Bus Read operations read the Status Register. The protection status can be monitored for each block using the Read Electronic Signature command. Refer to Section 9: Block protection for a detailed explanation and Appendix C, Figure 25: Protect/Unprotect operation flowchart and pseudo code for a flowchart for using the Block Unprotect command.

Table 5. Standard commands (1)

1. X = ‘Don't Care’, WA = word Address in targeted bank, RD = Read Data, SRD = Status Register Data,
2. Must be same bank as in the first cyc le. The signature addresses are listed in Table 7.
3. Any address within the bank can be used.
4. n+1 is the number of words to be programmed.

Table 6. Factory commands

1. WA = word Address in targeted bank, BKA = Bank A ddress, PD = Program Data, BA = Block Address, X =
2. Any address within the bank can be used.
3. The Program/Verify phase can be executed any number of times as long as the data is to be programmed
4. WA 1 is the Start Address, NOT BA1 = Not Block Address of WA1.

Table 7. Electronic signature codes

1. CR = Configuration Register, PRLD = Protection Register Lock Data.

Figure 4. Protection Register memory map

Command interface M58LT128HST, M58LT128HSB Table 8. Protection Register locks

Description

Bit 0 Preprogrammed to protect unique device number, address 81h to 84h in PR0 Bit 1 Protects 64 bits of OTP segment, address 85h to 88h in PR0 Bits 2 to 15 reserved Lock 2 89h Bit 0 Protects 128 bits of OTP segment PR1 Bit 1 Protects 128 bits of OTP segment PR2 Bit 2 Protects 128 bits of OTP segment PR3 ---- ---- Bit 13 Protects 128 bits of OTP segment PR14 Bit 14 Protects 128 bits of OTP segment PR15 Bit 15 Protects 128 bits of OTP segment PR16

M58LT128HST, M58LT128HSB Status Register

5 Status Register

The Status Register provides information on the current or previous Program or Erase operations. The Read Status Register command reads the contents of the Status Register (refer to Section 4.2: Read Status Register command for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to V IH. The Status Register can only be read using single Asynchronous or Single Synchronous reads. If no Read Array command has been issued, Bus Read operations from any address within the bank always read the Status Register during Program and Erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2, and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3, and SR1 give information about any errors; they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to Table 9 in conjunction with the following text descriptions.

5.1 Program/Erase Controller status bit (SR7)

The Program/Erase Controller status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller status bit is Low (set to ‘0’), the Program/Erase Controller is active. When the bit is High (set to ‘1’), the Program/Erase Controller is inactive and the device is ready to process a new command. The Program/Erase Controller status bit is Low immediately after a Program/Erase Suspend command is issued, until the Program/Erase Controller pauses. After the Program/Erase Controller pauses, the bit is High.

5.2 Erase Suspend status bit (SR6)

The Erase Suspend status bit indicates that an erase operation has been suspended. When the Erase Suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend status bit should only be considered valid when the Program/Erase Controller status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase Suspend latency time of the Program/Erase Suspend command being issued; therefore, the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued, the Erase Suspend status bit returns Low.

Status Register M58LT128HST, M58LT128HSB

5.3 Erase/Blank Check status bit (SR5)

The Erase/Blank Check status bit is used to identify if there was an error during a Block Erase operation. When the Erase/Blank Check status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that it has erased correctly. The Erase/Blank Check status bit should be read once the Program/Erase Controller status bit is High (Program/Erase Controller inactive). The Erase/Blank Check status bit is also used to indicate whether an error occurred during the Blank Check operation. If the data at one or more locations in the block where the Blank Check command has been issued is different from FFFFh, SR5 is set to '1'. Once set High, the Erase/Blank Check status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is issued, otherwise the new command appears to fail.

5.4 Program status bit (SR4)

The Program status bit is used to identify if there was an error during a Program operation. The Program status bit should be read once the Program/Erase Controller status bit is High (Program/Erase Controller inactive). When the Program status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the word and still failed to verify that it has programmed correctly. Attempting to program a '1' to an already programmed bit while VPP = VPPH also sets the Program status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0') and the attempt is not shown. Once set High, the Program status bit must be set Low by a Clear Status Register command or a hardware reset before a new Program command is issued, otherwise the new command appears to fail.

5.5 V PP status bit (SR3)

The VPP status bit is used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Program and Erase operations are not guaranteed if VPP becomes invalid during an operation. When the VPP status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid voltage. When the VPP status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK. This means the memory is protected and Program and Erase operations cannot be performed. Once set High, the VPP status bit must be set Low by a Clear Status Register command or a hardware reset before a new Program or Erase command is issued, otherwise the new command appears to fail.

M58LT128HST, M58LT128HSB Status Register

5.6 Program Suspend status bit (SR2)

The Program Suspend status bit indicates that a Program operation has been suspended. The Program Suspend status bit should only be considered valid when the Program/Erase Controller status bit is High (Program/Erase Controller inactive). When the Program Suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. SR2 is set within the Program Suspend latency time of the Program/Erase Suspend command being issued; therefore,the memory may still complete the operation rather than entering Suspend mode. When a Program/Erase Resume command is issued, the Program Suspend status bit returns Low.

5.7 Block Protection status bit (SR1)

The Block Protection status bit is used to identify if a Program or Block Erase operation has tried to modify the contents of a protected block. When the Block Protection status bit is High (set to ‘1’), a Program or Erase operation has been attempted on a protected block. Once set High, the Block Protection status bit must be set Low by a Clear Status Register command or a hardware reset before a new Program or Erase command is issued, otherwise the new command appears to fail.

5.8 Bank Write/Multiple Word Program status bit (SR0)

The Bank Write status bit indicates whether the addressed bank is programming or erasing. In Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the device is ready to accept a new word to be programmed to the memory array. The Bank Write status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to ‘0’). When both the Program/Erase Controller status bit and the Bank Write status bit are Low (set to ‘0’), the addressed bank is executing a Program or Erase operation. When the Program/Erase Controller status bit is Low (set to ‘0’) and the Bank Write status bit is High (set to ‘1’), a program or erase operation is being executed in a bank other than the one being addressed. In Buffer Enhanced Factory Program mode, if Multiple Word Program status bit is Low (set to ‘0’), the device is ready for the next word. If the Multiple Word Program status bit is High (set to ‘1’), the device is not ready for the next word. For further details on how to use the Status Register, see the Flowcharts and Pseudocodes provided in Appendix C.

Table 9. Status Register bits

1. Logic level '1' is High, '0' is Low.

6 Configuration Register

performs. Refer to Chapter 7: Read modes for details on Read operations. operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations.

6.1 Read Select bit (CR15)

Select bit is set to ’0’, Read operations are synchronous. On reset or power-up the Read Select bit is set to ’1’ for asynchronous access.

6.2 X-Latency bits (CR13-CR11)

to Figure 5: X-latency and data output configuration example. the device and the frequency used to read the Flash memory in Synchronous mode. Table 10. X-Latency Settings

30 MHz 33 ns 3

40 MHz 25 ns 4

52 MHz 19 ns 5

Configuration Register M5 8LT128HST, M58LT128HSB

6.3 Wait Polarity bit (CR10)

The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst Read mode. During Synchronous Burst Read mode the Wait signal indicates whether the data output is valid or a WAIT state must be inserted. When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait Polarity bit is set to ‘1’ the Wait signal is active High.

6.4 Data Output Configuration bit (CR9)

The Data Output Configuration bit is used to configure the output to remain valid for either one or two clock cycles during Synchronous mode. When the Data Output Configuration bit is ’0’ the output data is valid for one clock cycle; when the Data Output Configuration bit is ’1’ the output data is valid for two clock cycles. The Data Output Configuration bit must be configured using the following condition:

• tK > tKQV + tQVK_CPU where:
• tK is the clock period
• tQVK_CPU is the data setup time required by the system CPU
• tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 5: X-latency and data output configuration example.

6.5 Wait Configuration bit (CR8)

The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in Synchronous Burst Read mode. When WAIT is asserted, Data is Not Valid and when WAIT is de-asserted, Data is Valid. When the Wait Configuration bit is Low (set to ’0’), the Wait output pin is asserted during the WAIT state. When the Wait Configuration bit is High (set to ’1’), the Wait output pin is asserted one data cycle before the WAIT state.

6.6 Burst Type bit (CR7)

The Burst Type bit determines the sequence of addresses read during Synchronous Burst Reads. The Burst Type bit is High (set to ’1’) because the memory only outputs from sequential addresses. See Table 12: Burst type definition for the sequence of addresses output from a given starting address in Sequential mode.

M58LT128HST, M58LT128HSB Configuration Register

6.7 Valid Clock Edge bit (CR6)

The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Read operations. When the Valid Clock Edge bit is Low (set to ’0’) the falling edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to ’1’) the rising edge of the Clock is the active edge.

6.8 Wrap Burst bit (CR3)

The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous Burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). When the Wrap Burst bit is Low (set to ‘0’) the Burst Read wraps. When it is High (set to ‘1’) the Burst Read does not wrap.

6.9 Burst length bits (CR2-CR0)

The Burst Length bits are used to set the number of words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In Continuous Burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is shifted by 1, 2 or 3 positions from the four-word boundary, WAIT is asserted for 1, 2 or 3 clock cycles, respectively, when the burst sequence crosses the first 16-word boundary. This indicates that the device needs an internal delay to read the successive words in the array. WAIT is only asserted once during a continuous burst access. See also Table 12: Burst type definition. CR14, CR5 and CR4 are reserved for future use.

Table 11. Configuration Register

0 Synchronous Read

1 Asynchronous Read (Default at power-on)

1. The combination X-Latency = 2, Data held for two clock cycles and Wait active one data cycle before the

WAIT state is not supported.

0 WAIT is active Low

1 WAIT is active High (default)

0 Data held for one clock cycle

1 Data held for two clock cycles (default)

0 WAIT is active during WAIT state

1 WAIT is active one data cycle before WAIT

1 Sequential (default)

0 Falling Clock edge

1 Rising Clock edge (default)

1 No Wrap (default)

111 Continuous (default)

Table 12. Burst type definition

Table 12. Burst type definition (continued)

Read modes M58LT128HST, M58LT128HSB

7 Read modes

Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for the data output, the Read operation is asynchronous. If the data output is synchronized with clock, the Read operation is synchronous. The Read mode and format of the data output are determined by the Configuration Register. (See Section 6: Configuration Register for details). All banks support both asynchronous and Synchronous Read operations.

7.1 Asynchronous Read mode

In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data corresponding to the address latched; that is the memory array, Status Register, Common Flash Interface, or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for synchronous operations. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. In Asynchronous Read mode a page of data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by address inputs A0 and A1. The first Read operation within the page has a longer access time (t AVQV, random access time). Subsequent reads within the same page have much shorter access times (tAVQV1, page access time). If the page changes, then the normal, longer timings apply again. The device features an Automatic Standby mode. During Asynchronous Read operations, after a bus inactivity of 150 ns, the device automatically switches to the Automatic Standby mode. In this situation, the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, the WAIT signal is always de-asserted. See Table 22: Asynchronous Read AC characteristics, Figure 9: Asynchronous random access Read AC waveforms, and Figure 10: Asynchronous Page Read AC waveforms for details.

M58LT128HST, M58LT128HSB Read modes

7.2 Synchronous Burst Read mode

In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform Burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other Read operations, such as Read Status Register, Read CFI and Read Electronic Signature, then Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay, which depends on the X-latency bits CR13-CR11 of the Configuration Register. The number of words to be output during a Synchronous Burst Read operation can be configured as 4 words, 8 words, 16 words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Wrap Burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4-, 8- or 16-word boundary (wrap) or overcome the boundary (no wrap). The WAIT signal may be asserted to indicate to the system that an output delay occurs. This delay depends on the starting address of the burst sequence and on the burst configuration. WAIT is asserted during the X-latency, the WAIT state, and at the end of a 4-, 8- and 16- word burst. It is only de-asserted when output data is valid. In Continuous Burst Read mode a WAIT state occurs when crossing the first 16-word boundary. If the starting address is aligned to the burst length (4-, 8- or 16-words), the wrapped configuration has no impact on the output sequence. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 23: Synchronous Read AC characteristics and Figure 11: Synchronous Burst Read AC waveforms for details.

Read modes M58LT128HST, M58LT128HSB

7.2.1 Synchronous Burst Read Suspend

A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when Chip Enable, E , is Low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The Clock signal is then halted at V IH or at VIL, and Output Enable, G, goes High. When Output Enable, G, becomes Low again and the Clock signal restarts, the Synchronous Burst Read operation resumes exactly where it stopped. WAIT reverts to high-impedance whenever Chip Enable, E, or Output Enable, G, goes High. See Table 23: Synchronous Read AC characteristics and Figure 13: Synchronous Burst Read Suspend AC waveforms for details.

7.3 Single Synchronous Read mode

Single Synchronous Read operations are similar to Synchronous Burst Read operations except that the memory outputs the same data to the end of the operation. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register, or Read Electronic Signature mode, the WAIT signal is asserted during the X-latency, the WAIT state, and at the end of a 4-, 8- and 16-word burst. It is only de-asserted when output data are valid. See Table 23: Synchronous Read AC characteristics and Figure 12: Single Synchronous Read AC waveforms for details.

8 Dual operations and multiple bank architecture

from one bank while another bank is being programmed or erased. to be in Program or Erase mode). block in Erase Suspend mode, one programming, and other banks in Read mode. Program or Erase operations. Table 13. Dual operations allowed in other banks

Table 14. Dual operations allowed in same bank

1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase
2. The Read Array command is accepted but the data output is not guaranteed in the block that is being

erased, or in the word that is being programmed.

1. Not allowed in the block that is being erased or in the word that is being programmed.

Table 15. Dual operation limitations

M58LT128HST, M58LT128HSB Block protection

9 Block protection

The M58LT128HST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency. This protection scheme has two levels of protection.

• Protect/unprotect: this first level allows software only control of block protection.
• VPP ≤ VPPLK : the second level offers a complete hardware protection against Program and Erase operations on all blocks. The protection status of each block can be set to protected and unprotected. Appendix C, Figure 25 shows a flowchart for the protection operations.

9.1 Protection status

The protection status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode, issue the Read Electronic Signature command. Subsequent reads at the address specified in Table 7 output the protection status of that block. The protection status is represented by DQ0. DQ0 indicates the block protect/unprotect status. It is set by the Protect command and cleared by the Unprotect command. The following sections explain the operation of the protection system.

9.2 Protected state

The default state of all blocks on power-up or after a hardware reset is protected (state = 1). Protected blocks are fully protected from Program or Erase operations. Any Program or Erase operations attempted on a protected block return an error in the Status Register. The state of a protected block can be changed to unprotected using the appropriate software commands. An unprotected block can be protected by issuing the Protect command.

9.3 Unprotected state

Unprotected blocks (state = 0) can be programmed or erased. All unprotected blocks return to the protected state after a hardware reset or when the device is powered-down. The state of an unprotected block can be changed to protected using the appropriate software commands. A protected block can be unprotected by issuing the Unprotect command.

Block protection M58LT128HST, M58LT128HSB

9.4 Protection operations during Erase Suspend

Changes to the block protection state can be made during an Erase Suspend by using the standard protection command sequences to unprotect or protect a block. This is useful in the case where another block needs to be updated while an Erase operation is in progress. To change block protection during an Erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the Erase operation has been suspended. Next, write the desired Protect command sequence to a block and the protection status changes. After completing any desired Protect, Read, or Program operations, resume the Erase operation with the Erase Resume command. If a block is protected during an Erase Suspend of the same block, the Erase operation completes when the erase is resumed. Protection operations cannot be performed during a Program Suspend operation.

10 Program and erase times and endurance cycles

Table 16. Program/erase times and endurance cycles (1) (2)

1. Values are liable to change with t he external system-level overhead (command sequence and Status Register polling
2. Excludes the time needed to execute the command sequence.
3. This is an average value on the entire device.

Table 16. Program/erase times and endurance cycles (1) (2) (continued)

11 Maximum rating

other relevant quality documents. Table 17. Absolute maximum ratings

12 DC and AC parameters

Figure 7. AC measurement I/O waveform Table 18. Operating and AC measurement conditions

Figure 8. AC measurement load circuit Table 19. Capacitance (1)

1. Sampled only, not 100% tested.

Table 20. DC characteristics - currents

1. Sampled only, not 100% tested.
2. V DD Dual Operation current is the sum of Read and Program or Erase currents.

Table 21. DC characteristics - voltages

Figure 9. Asynchronous random access Read AC waveforms Notes: 1. Write Enable, W, is High, WAIT is active Low.

1. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported.

Figure 10. Asynchronous Page Read AC waveforms

Table 22. Asynchronous Read AC characteristics

1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.

Figure 11. Synchronous Burst Read AC waveforms Note 1. The number of clock cycles to be inserted depends on the X-latency set in the Burst Configuration Register.

1. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge.
3. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.

Figure 12. Single Synchronous Read AC waveforms

1. The WAIT signal is configured to be active dur ing wait state. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock

signal, K, can be configured as the active edge. Here, the active edge is the rising one.

Figure 13. Synchronous Burst Read Suspend AC waveforms Notes 1. The number of clock cycles to be inserted depends on the X-latency set in the Configuration Register.

1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. The CLOCK signal can be held high or low.
3. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge.

Here, the active edge is the rising one.

Figure 14. Clock input AC waveform Table 23. Synchronous Read AC characteristics (1) (2)

1. Sampled only, not 100% tested.
2. For other timings please refer to Table 22: Asynchronous Read AC characteristics.

Figure 15. Write AC waveforms, Write Enable controlled

Table 24. Write AC characteristics, Write Enable controlled (1)

1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept low.
3. t WHEL and tWHLL have this value when reading in the targeted bank or when reading following a Set

been issued, tWHEL and tWHLL are 0 ns.

Figure 16. Write AC waveforms, Chip Enable controlled

Table 25. Write AC characteristics, Chip Enable controlled (1)

1. Sampled only, not 100% tested.
2. t WHEL has this value when reading in the targeted bank or when reading following a Set Configuration

Figure 17. Reset and power-up AC waveforms Table 26. Reset and power-up AC characteristics

1. The device Reset is possible but not guaranteed if t PLPH < 50ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during power-up or reset.

the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 18. TBGA64 10 × 13 mm - 8 × 8 active ball array, 1 mm pitch, bottom view

14 Part numbering

Devices are shipped from the factory with the memory content bits erased to ’1’. of this device, please contact the Numonyx Sales Office nearest to you. Table 28. Ordering information scheme

Table 29. Top boot block addresses, M58LT128HST

Table 29. Top boot block addresses, M58LT128HST (continued)

1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;

Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).

Table 30. Bottom boot block addresses, M58LT128HSB

Table 30. Bottom boot block addresses, M58LT128HSB (continued)

1. There are two bank regions : bank region 2 contains all the banks that are made up of main blocks only;

bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank).

software to upgrade itself when necessary. lowest order data outputs (DQ0-DQ7), and the other outputs (DQ8-DQ15) are set to 0. been written by Numonyx. Issue a Read Array command to return to Read mode.

1. The Flash memory displays the CFI data structure w hen the CFI Query command is issued. This table lists

Table 31. Query structure overview

Table 32. CFI query identification string

Table 33. CFI query system interface information

Table 34. Device geometry definition

Table 35. Primary algorithm-specific extended query table (P+5)h contains less significant bytes.

Table 36. Protection Register information (P+E)h = 118h 0002h Number of Protection Register fields in JEDEC ID space. Table 37. Burst Read information determine page-mode data output width. reaches the end of the device’s burstable address space. determine the burst data output width. Synchronous mode read capability configuration 4 Cont.

M58LT128HST, M58LT128HSB Common Flash Interface Table 38. Bank and Erase Block region information (1) (2)

1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There ar e two bank regions, see Table 29 and Table 30.

(P+23)h = 12Dh 02h (P+23)h = 12Dh 02h Number of bank regions within the device Table 39. Bank and Erase Block region 1 information contiguous same-size erase blocks.

1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There ar e two bank regions, see Table 29 to Table 30.

Table 39. Bank and Erase Block region 1 information (continued)

Table 40. Bank and Erase Block region 2 Information contiguous same-size erase blocks.

1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Table 29 and Table 30.

Table 40. Bank and Erase Block region 2 Information (continued)

Figure 19. Program flowchart and pseudo code

1. Status check of SR1 (protected block), SR3 (V PP Invalid) and SR4 (program error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cl eared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 20. Blank Check flowchart and pseudo code

1. Any address within the bank can equally be used.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

Figure 21. Buffer Program flowchart and pseudo code

1. n + 1 is the number of data being programmed.
2. Next program data is an element belonging to buffer_Progra m[].data; next program address is an element belonging to
3. Routine for Error Check by reading SR3, SR4 and SR1.

Figure 22. Program Suspend & Resume flowchart and pseudo code

1. The Read Status Register command (Write 70h) can be issu ed just before or just after the Program Resume command.

Figure 23. Block Erase flowchart and pseudo code

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.

Figure 24. Erase Suspend & Resume flowchart and pseudo code

1. The Read Status Register command (Write 70h) can be is sued just before or just after the Erase Resume command.

Figure 25. Protect/Unprotect operation flowchart and pseudo code

1. Any address within the bank can equally be used.

Figure 26. Protection Register Program flowchart and pseudo code

1. Status check of SR1 (protected block), SR3 (V PP Invalid) and SR4 (program error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cl eared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 27. Buffer Enhanced Factory Program flowchart and pseudo code

Table 41. Command Interface states - modify table, next state (1)

Table 41. Command Interface states - modify table, next state (1) (continued)

1. CI = Command Interface, CR = Configuration register, BEF P = Buffer Enhanced Factory program, P/E C = Program/Erase

controller, IS = Illegal State, BP = Buffer Program, ES = Erase Suspend.

1. At power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined
2. The two cycle command should be issued to the same bank address.
3. If the Program/Erase Controller is active, both cycles are ignored.
4. The Clear Status Register command clear s the SR error bits except when the Program/Erase Controller is busy or
5. BEFP is allowed only when Status Register bit SR0 is reset to '0'. BEFP is busy if block address is first BEFP address. Any

other commands are treated as data.

Table 42. Command Interface states - modify table, next output state (1) (2)

1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command

depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank output state.

1. CI = Command Interface, CR = Configuration Register , BEFP = Buffer Enhanced Factory Program, Program/Erase

Controller = Program/Erase Controller.

1. At power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined
2. The two cycle command should be issued to the same bank address.
3. If the Program/Erase Controller is active, both cycles are ignored.

Table 42. Command Interface states - modify table, next output state (1) (2) (continued)

Table 43. Command interface states - lock table, next state (1)

1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase
2. If the Program/Erase Controller is active, both cycle are ignored.
3. BEFP exit when block address is different from first block address and data are FFFFh.
4. Illegal commands are those not defined in the command set.
5. N/A: not available. In this case the state remains unchanged.
6. If N=0 go to Buffer Program Confirm. Else ( not = 0) go to Buffer Program Load 2 (data load)
7. If N=0 go to Buffer Program Confirm in Erase suspend. Else (not =0) go to Buffer Program Load 2 in Erase suspend.
8. BEFP is allowed only when Status Register bit SR0 is set to '0'. BEFP is busy if Block Address is first BEFP Address. Any

other commands are treated as data. Table 43. Command interface states - lock table, next state (1) (continued)

Table 44. Command interface states - lock table, next output state (1) (2)

1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command

depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank's output state.

1. CI = Command Interface, CR = Configuration Register , BEFP = Buffer Enhanced Factory Program, P/E. C. =
2. If the Program/Erase Controller is active, both cycles are ignored.
3. BEFP Exit when block address is different fr om first block address and data are FFFFh.
4. Illegal commands are those not defined in the command set.

Table 44. Command interface states - lock table, next output state (continued) (1) (2)

Revision history

Table 45. Document revision history 02-Mar-2007 1 Initial release. – Modified WAIT de-assertion criteria on page 45. – Modified the t VDHPH parameter values in Table 26. 10-Dec-2007 3 Applied Numonyx branding.