M58LT128GST1ZA5F

M58LT128GS STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Summary description
• 2 Signal descriptions
• 2.1 Address Inputs (A0-A22)
• 2.2 Data Input/Output (DQ0-DQ15)
• 2.3 Chip Enable (E)
• 2.4 Output Enable (G)
• 2.5 Write Enable (W)
• 2.6 Reset (RP)
• 2.7 Latch Enable (L)
• 2.8 Clock (K)
• 2.9 Wait (WAIT)
• 2.10.1 VDDQ Supply Voltage
• 2.11 V PP Program Supply Voltage
• 2.12 V SS Ground
• 2.13 V SSQ Ground
• 3 Bus operations
• 3.1 Bus Read
• 3.2 Bus Write
• 3.3 Address Latch
• 3.4 Output Disable
• 3.5 Standby
• 3.6 Reset
• 4 Command Interface
• 4.1 Read Array command
• 4.2 Read Status Register command
• 4.3 Read Electronic Signature command
• 4.4 Read CFI Query command
• 4.5 Clear Status Register command

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev 1.0 September 2005 1/98 M58LT128GST M58LT128GSB 128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories Features Summary ■ SUPPLY VOLTAGE –V DD = 1.7 to 2.0V for program, erase and read –V DDQ = 2.7 to 3.6V for I/O Buffers –V PP = 9V for fast program ■ SYNCHRONOUS / ASYNCHRONOUS READ – Random Access: 110ns – Asynchronous Page Read: 25ns. – Synchronous Burst Read: 52MHz ■ SYNCHRONOUS BURST READ SUSPEND ■ PROGRAMMING TIME – 10µs typical Word program time using Buffer Enhanced Factory Program command ■ MEMORY ORGANIZATION – Multiple Bank Memory Array:

8 Mbit Banks

– Parameter Blocks (Top or Bottom location) ■ DUAL OPERATIONS – program/erase in one Bank while read in others – No delay between read and write operations ■ HARDWARE PROTECTION – All Blocks Write Protected when VPP ≤VPPLK ■ SECURITY – Software Security Features – 64-bit Unique Device Identifier – 2112 bits of User-Programmable OTP memory ■ COMMON FLASH INTERFACE (CFI) ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: M58LT128GST: 88C6h M58LT128GSB: 88C7h ■ ECOPACK ® PACKAGE AVAILABLE BGA TBGA64 (ZA) 10 x 13mm

M58LT128GST, M58LT128GSB 5.5 V

M58LT128GST, M58LT128GSB

1 Summary description M58LT128GST, M58LT128GSB

1 Summary description

The M58LT128GST and M58LT128GSB are 128 Mbit (8 Mbit x16) non-volatile Secure Flash memories. The devices may be erased electrically at block level and programmed in-system on a Word-by- Word basis using a 1.7 to 2.0V VDD supply for the circuitry and a 2.7 to 3.6V VDDQ supply for the Input/Output pins. An optional 9V VPP power supply is provided to speed up factory programming. The devices feature an asymmetrical block architecture and are based on a multi-level cell technology. The memory array is organized as 131 blocks, and is divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 KWords, and one parameter bank containing 4 parameter blocks of 16 KWords and 7 main blocks of 64 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory maps are shown in Figure 3. The Parameter Blocks are located at the top of the memory address space for the M58LT128GST, and at the bottom for the M58LT128GSB. Each block can be erased separately. Erase can be suspended, in order to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage V DD . There is a Buffer Enhanced Factory programming command available to speed up programming. Program and erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports Synchronous Burst Read and Asynchronous Read and Page Read from all blocks of the memory array; at power-up the device is configured for Asynchronous Read. In Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to 52MHz. The Synchronous Burst Read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. The M58LT128GST and M58LT128GSB are equipped with several features to increase data protection:

• Hardware Protection: all blocks are protected from program and erase operations when the V PP ≤ VPPLK .
• A full set of Software Security Features described in a dedicated Application Note. Please contact STMicroelectronics for further details.
• 64-bit Unique Device Identifier
• 2112 bits of User-Programmable OTP memory

protected. Figure 4 shows the Protection Register Memory Map. The devices are offered in TBGA64 10 x 13mm, 1mm pitch. The memories are supplied with all the bits erased (set to ’1’). Figure 1. Logic Diagram

Table 1. Signal Names

Figure 2. TBGA64 Connections (Top view through package) Table 2. Bank Architecture

Figure 3. Memory Map

8 Main

64 KWord000000h

64 KWord070000h

64 KWord600000h

64 KWord670000h

64 KWord680000h

64 KWord6F0000h

64 KWord700000h

64 KWord770000h

64 KWord780000h

64 KWord7E0000h

16 KWord7F0000h

16 KWord7FC000h

4 Parameter

16 KWord000000h

16 KWord00C000h

64 KWord010000h

64 KWord080000h

64 KWord0F0000h

64 KWord100000h

64 KWord170000h

64 KWord180000h

64 KWord1F0000h

64 KWord7F0000h

7 Main

M58LT128GST, M58LT128GSB 2 Signal descriptions

2 Signal descriptions

See Figure 1: Logic Diagram and Table 1: Signal Names, for a brief overview of the signals connected to this device.

2.1 Address Inputs (A0-A22)

The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller.

2.2 Data Input/Output (DQ0-DQ15)

The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation.

2.3 Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V ILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level.

2.4 Output Enable (G )

The Output Enable input controls data outputs during the Bus Read operation of the memory.

2.5 Write Enable (W)

The Write Enable input controls the Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.

2.6 Reset (RP )

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current I DD2 . Refer to Table 20: DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Protected state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to V RPH (refer to Table 21: DC Characteristics - Voltages).

2 Signal descriptions M58LT128GST, M58LT128GSB

2.7 Latch Enable (L)

Latch Enable latches the A0-A22 address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH.

2.8 Clock (K)

The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at V IL. Clock is ignored during asynchronous read and in write operations.

2.9 Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at V IH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAIT signal is forced deasserted when Output Enable is at VIH.

2.10 V DD Supply Voltage

VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase).

2.10.1 VDDQ Supply Voltage

VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD . VDDQ can be tied to VDD or can use a separate supply.

2.11 V PP Program Supply Voltage

The VPP pin is both a power supply and a write protect pin. The functions are selected by the voltage range applied to the pin. When V PP is lower than VPPLK , it is seen as a write protect pin protecting the whole memory array. Program and erase operations on all blocks are ignored while VPP is Low. When V PP is Higher than VPP1 , the memory reverts to the previous protection state of the memory array. Program and erase operations can now modify the data in any block (refer to Table 21: DC Characteristics - Voltages for V PPLK and VPP1 values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If V PP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed. The VPP pin must not be left floating or unconnected or the device may become unreliable. A 0.1µF capacitor should be connected between the VPP pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, I PP.

M58LT128GST, M58LT128GSB 2 Signal descriptions

2.12 V SS Ground

VSS ground is the reference for the core supply. It must be connected to the system ground.

2.13 V SSQ Ground

VSSQ ground is the reference for the input/output circuitry driven by VDDQ . VSSQ must be connected to VSS Note: Each device in a system should have VDD , VDDQ and VPP decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 8: AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required V PP program and erase currents.

3 Bus operations M58LT128GST, M58LT128GSB

3 Bus operations

There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 3: Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations.

3.1 Bus Read

Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at V IL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figure 9, Figure 11 and Figure 12 Read AC Waveforms, and Ta bl e 2 2 and Table 23 Read AC Characteristics, for details of when the output becomes valid.

3.2 Bus Write

Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the write operation by toggling Latch Enable. In this case the Latch Enable should be tied to V IH during the bus write operation. See Figure 15 and Figure 16, Write AC Waveforms, and Table 24 and Table 25, Write AC Characteristics, for details of the timing requirements.

3.3 Address Latch

Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. The addresses are latched on the rising edge of Latch Enable.

3.4 Output Disable

The outputs are high impedance when the Output Enable is at VIH.

3.5 Standby

Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at V IH. The power consumption is reduced to the standby level IDD3 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished.

3.6 Reset

Table 3. Bus Operations

1. WAIT signal polarity is configured using the Set Configuration Register command.

4 Command Interface M58LT128GST, M58LT128GSB

4 Command Interface

monitor the progress or the result of the operation. DD is lower than VLKO . Command sequences must be followed exactly. Any invalid combination of commands will be ignored. STMicroelectronics for further details. Table 4. Command Codes

M58LT128GST, M58LT128GSB 4 Command Interface

4.1 Read Array command

The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read Array mode, subsequent read operations will output the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank will return to Read Array mode but the program or erase operation will continue, however the data output from the bank is not guaranteed until the program or erase operation has finished. The read modes of other banks are not affected.

4.2 Read Status Register command

The device contains a Status Register that is used to monitor program or erase operations. The Read Status Register command is used to read the contents of the Status Register for the addressed bank. One Bus Write cycle is required to issue the Read Status Register command. Once a bank is in Read Status Register mode, subsequent read operations will output the contents of the Status Register. The Status Register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the Status Register data The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Status Register. A Read Array command is required to return the bank to Read Array mode. See Table 9 for the description of the Status Register Bits.

4.3 Read Electronic Signature command

The Read Electronic Signature command is used to read the Manufacturer and Device Codes, the Protection Status of the addressed bank, the Configuration Register and the Protection Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once a bank is in Read Electronic Signature mode, subsequent read operations in the same bank will output the Manufacturer Code, the Device Code, the Protection Status of the addressed bank, or the Configuration Register (see Table 7). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during Protection Register Program operations. Dual operations between the Parameter bank and the Electronic Signature location are not allowed (see Table 15: Dual Operation Limitations for details). If a Read Electronic Signature command is issued to a bank that is executing a program or erase operation the bank will go into Read Electronic Signature mode. Subsequent Bus Read

cycles will output the Electronic Signature data and the Program/Erase controller will continue to program or erase in the background. The Read Electronic Signature command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Electronic Signature. A Read Array command is required to return the bank to Read Array mode.

4.4 Read CFI Query command

The Read CFI Query command is used to read data from the Common Flash Interface (CFI). One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in Read CFI Query mode, subsequent Bus Read operations in the same bank read from the Common Flash Interface. The Read CFI Query command can be issued at any time, even during program or erase operations. If a Read CFI Query command is issued to a bank that is executing a program or erase operation the bank will go into Read CFI Query mode. Subsequent Bus Read cycles will output the CFI data and the Program/Erase controller will continue to program or erase in the background. The Read CFI Query command will only change the read mode of the addressed bank. The read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read from the CFI. A Read Array command is required to return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI memory space are not allowed (see Table 15: Dual Operation Limitations for details). See Appendix B: Common Flash Interface, Table 36, Table 37, Table 38, Table 39, Table 40, Table 42, Table 43, Table 44 and Table 45 for details on the information contained in the Common Flash Interface memory area.

4.5 Clear Status Register command

The Clear Status Register command can be used to reset (set to ‘0’) all error bits (SR1, 3, 4 and 5) in the Status Register. One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the read mode of the bank. The error bits in the Status Register do not automatically return to ‘0’ when a new command is issued. The error bits in the Status Register should be cleared before attempting a new program or erase command.

M58LT128GST, M58LT128GSB 4 Command Interface

4.6 Block Erase command

The Block Erase command is used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. 1. The first bus cycle sets up the Block Erase command. 2. The second latches the block address and starts the Program/Erase Controller. If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5 are set and the command is aborted. Once the command is issued the bank enters Read Status Register mode and any read operation within the addressed bank will output the contents of the Status Register. A Read Array command is required to return the bank to Read Array mode. During Block Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. The Block Erase operation aborts if Reset, RP , goes to VIL. As data integrity cannot be guaranteed when the Block Erase operation is aborted, the block must be erased again. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 16: Program/Erase Times and Endurance Cycles. See Appendix C, Figure 22: Block Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Block Erase command.

4.7 Program command

The program command is used to program a single Word to the memory array. Two Bus Write cycles are required to issue the Program Command. 1. The first bus cycle sets up the Program command. 2. The second latches the address and data to be programmed and starts the Program/ Erase Controller. Once the programming has started, read operations in the bank being programmed output the Status Register content. During a Program operation, the bank containing the Word being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. A Read Array command is required to return the bank to Read Array mode. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 16: Program/Erase Times and Endurance Cycles. The Program operation aborts if Reset, RP , goes to VIL. As data integrity cannot be guaranteed when the Program operation is aborted, the Word must be reprogrammed.

See Appendix C, Figure 19: Program Flowchart and Pseudo Code, for the flowchart for using the Program command.

4.8 Buffer Program command

The Buffer Program Command makes use of the device’s 32-Word Write Buffer to speed up programming. Up to 32 Words can be loaded into the Write Buffer. The Buffer Program command dramatically reduces in-system programming time compared to the standard non- buffered Program command. Four successive steps are required to issue the Buffer Program command. 1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. After the first Bus Write cycle, read operations in the bank will output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to update the Status Register contents. 2. The second Bus Write cycle sets up the number of Words to be programmed. Value n is written to the same block address, where n+1 is the number of Words to be programmed. 3. Use n+1 Bus Write cycles to load the address and data for each Word into the Write Buffer. Addresses must lie within the range from the start address to the start address + n. Optimum performance is obtained when the start address corresponds to a 32 Word boundary. If the start address is not aligned to a 32 word boundary, the total programming time is doubled 4. The final Bus Write cycle confirms the Buffer Program command and starts the program operation. All the addresses used in the Buffer Program operation must lie within the same block. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the operation without affecting the data in the memory array. If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not accepted. Clear the Status Register before re-issuing the command. If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. During Buffer Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 20: Buffer Program Flowchart and Pseudo Code, for a suggested flowchart on using the Buffer Program command.

M58LT128GST, M58LT128GSB 4 Command Interface

4.9 Buffer Enhanced Factory Program command

The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. It is used to program one or more Write Buffer(s) of 32 Words to a block. Once the device enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. The use of the Buffer Enhanced Factory Program command requires certain operating conditions:

• The targeted block must be unprotected. if it is protected, the user must return the device to read mode.
• VPP must be set to VPPH .
• VDD must be within operating range.
• Ambient temperature TA must be 30°C ± 10°C.
• The start address must be aligned with the start of a 32 Word buffer boundary.
• The address must remain the Start Address throughout programming. Dual operations are not supported during the Buffer Enhanced Factory Program operation and the command cannot be suspended. The Buffer Enhanced Factory Program Command consists of three phases: the Setup Phase, the Program and Verify Phase, and the Exit Phase, See Appendix C, Figure 25: Buffer Enhanced Factory Program Flowchart and Pseudo Code, for a suggested flowchart on using the Buffer Program command and to Table 6: Factory Program Command for details on the Buffer Enhanced Factory Program command.

4.9.1 Setup phase

The Buffer Enhanced Factory Program command requires two Bus Write cycles to initiate the command. 1. The first Bus Write cycle sets up the Buffer Enhanced Factory Program command. 2. The second Bus Write cycle confirms the command. After the confirm command is issued, read operations output the contents of the Status Register. The read Status Register command must not be issued as it will be interpreted as data to program. The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program operation is terminated. See Status Register section for details on the error.

4.9.2 Program and Verify phase

The Program and Verify Phase requires 32 cycles to program the 32 Words to the Write Buffer. The data is stored sequentially, starting at the first address of the Write Buffer, until the Write Buffer is full (32 Words). To program less than 32 Words, the remaining Words should be programmed with FFFFh. Three successive steps are required to issue and execute the Program and Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address must remain the Start Address as the P/E.C. increments the address location.If any address that is not in the same block as the Start Address is given, the Program and Verify Phase terminates. Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. 3. Once the Write Buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary. The Program and Verify phase can be repeated, without re-issuing the command, to program additional 32 Word locations as long as the address remains in the same block. 4. Finally, after all Words, or the entire block have been programmed, write one Bus Write operation to any address outside the block containing the Start Address, to terminate Program and Verify Phase. Status Register bit SR0 must be checked to determine whether the program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed.

4.9.3 Exit phase

Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has exited the Buffer Enhanced Factory Program operation and returned to Read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical program times are given in Table 16 See Appendix C, Figure 25: Buffer Enhanced Factory Program Flowchart and Pseudo Code, for a suggested flowchart on using the Buffer Enhanced Factory Program command.

M58LT128GST, M58LT128GSB 4 Command Interface

4.10 Program/Erase Suspend command

The Program/Erase Suspend command is used to pause a Program or Block Erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to ‘1’. The following commands are accepted during Program/Erase Suspend:

• Program/Erase Resume
• Read Array (data from erase-suspended block or program-suspended Word is not valid)
• Read Status Register
• Read Electronic Signature
• Read CFI Query. In addition, if the suspended operation was a Block Erase then the following commands are also accepted:
• Clear Status Register
• Program (except in erase-suspended block)
• Buffer Program (except in erase suspended blocks) It is possible to accumulate multiple suspend operations. For example: suspend an erase operation, start a program operation, suspend the program operation, then read the array. If a Program command is issued during a Block Erase Suspend, the erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. Refer to Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to V IH. Program/erase is aborted if Reset, RP, goes to VIL. See Appendix C, Figure 21: Program Suspend & Resume Flowchart and Pseudo Code, and Figure 23: Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Program/Erase Suspend command.

4.11 Program/Erase Resume command

The Program/Erase Resume command is used to restart the program or erase operation suspended by the Program/Erase Suspend command. One Bus Write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data.

If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the program operation has completed. See Appendix C, Figure 21: Program Suspend & Resume Flowchart and Pseudo Code, and Figure 23: Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Program/Erase Resume command.

4.11.1 Protection Register Program command

The Protection Register Program command is used to program the user One-Time- Programmable (OTP) segments of the Protection Register and the two Protection Register Locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown in Figure 4: Protection Register Map. The segments are programmed one Word at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two Bus Write cycles are required to issue the Protection Register Program command. 1. The first bus cycle sets up the Protection 2. Register Program command. 3. The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the program operation has started. Attempting to program a previously protected Protection Register will result in a Status Register error. The Protection Register Program cannot be suspended. Dual operations between the Parameter Bank and the Protection Register memory space are not allowed (see Table 15: Dual Operation Limitations for details). The two Protection Register Locks are used to protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 4: Protection Register Map, and Table 8: Protection Register Lock Bits, for details on the Lock bits. See Appendix C, Figure 24: Protection Register Program Flowchart and Pseudo Code, for a flowchart for using the Protection Register Program command.

4.12 Set Configuration Register command

The Set Configuration Register command is used to write a new value to the Configuration Register. Two Bus Write cycles are required to issue the Set Configuration Register command. 1. The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content. 2. The second cycle writes the Configuration Register data and the confirm command. The Configuration Register data must be written as an address during the bus write cycles, that is DQ0 = CR0, DQ1 = CR1, …, DQ15 = CR15. Addresses A0-A22 are ignored. Read operations output the array content after the Set Configuration Register command is issued.

Table 5. Standard Commands

1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic

Address, PRD = Protection Register Data, CRD=Configuration Register Data.

1. Must be same bank as in the first cycle. The signature addresses are listed in Table 7
2. Any address within the bank can be used.
3. n+1 is the number of Words to be programmed.

Table 6. Factory Program Command Table 7. Electronic Signature Codes

1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address, X = Don’t Care.
2. Any address within the bank can be used.
3. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same
4. WA 1 is the Start Address, NOT BA1 = Not Block Address of WA1.
5. CR = Configuration Register, DRC = Die Revision Code.

Figure 4. Protection Register Map

Table 8. Protection Register Lock Bits

Description

Bit 0 Read-only bit preprogrammed to ‘0’ protect Unique Device Number (address 81h to 84h in PR0) Bit 1 protects 64bits of OTP segment (address 85h to 88h in PR0) when set to ‘0’ Default Value is ‘1’ Protection Register Lock 2 89h Bit 0 protects 128bits of OTP segment PR1 Bit 1 protects 128bits of OTP segment PR2 Bit 2 protects 128bits of OTP segment PR3 - - - - - - Bit 13 protects 128bits of OTP segment PR14 Bit 14 protects 128bits of OTP segment PR15 Bit 15 protects 128bits of OTP segment PR16

M58LT128GST, M58LT128GSB 5 Status Register

5 Status Register

The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to V IH. The Status Register can only be read using single Asynchronous or Single Synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during program and erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. Refer to Table 9: Status Register Bits in conjunction with the following text descriptions.

5.1 Program/Erase Controller Status Bit (SR7)

The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status bit is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High.

5.2 Erase Suspend Status Bit (SR6)

The Erase Suspend Status bit indicates that an erase operation has been suspended in the addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low.

5 Status Register M58LT128GST, M58LT128GSB

5.3 Erase Status Bit (SR5)

The Erase Status bit is used to identify if there was an error during a block or bank erase operation. When the Erase Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is issued, otherwise the new command will appear to fail.

5.4 Program Status Bit (SR4)

The Program Status bit is used to identify if there was an error during a program operation. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the Word and still failed to verify that it has programmed correctly. Attempting to program a '1' to an already programmed bit while V PP = VPPH will also set the Program Status bit High. If VPP is different from VPPH , SR4 remains Low (set to '0') and the attempt is not shown. Once set High, the Program Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program command is issued, otherwise the new command will appear to fail.

5.5 V PP Status Bit (SR3)

The VPP Status bit is used to identify an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid voltage. when the VPP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK , the memory is protected and program and erase operations cannot be performed. Once set High, the VPP Status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail.

M58LT128GST, M58LT128GSB 5 Status Register

5.6 Program Suspend Status Bit (SR2)

The Program Suspend Status bit indicates that a program operation has been suspended in the addressed block. The Program Suspend Status bit should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. SR1. Reserved.

5.7 Bank Write/Multiple Word Program Status Bit (SR0)

The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the device is ready to accept a new Word to be programmed to the memory array. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to ‘0’). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to ‘0’), the addressed bank is executing a program or erase operation. When the Program/Erase Controller Status bit is Low (set to ‘0’) and the Bank Write Status bit is High (set to ‘1’), a program or erase operation is being executed in a bank other than the one being addressed. In Buffer Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to ‘0’), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to ‘1’) the device is not ready for the next Word. For further details on how to use the Status Register, see the Flowcharts and Pseudo codes provided in Appendix C.

Table 9. Status Register Bits

1. Logic level '1' is High, '0' is Low.

M58LT128GST, M58LT128GSB 6 Configuration Register

6 Configuration Register

The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface using the Set Configuration Register command. After a reset or power-up the device is configured for asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 10 They specify the selection of the burst length, burst type, burst X latency and the read operation. Refer to Figure 5 and Figure 6 for examples of synchronous burst configurations.

6.1 Read Select Bit (CR15)

The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read operations. When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to ’1’ for asynchronous access.

6.2 X-Latency Bits (CR13-CR11)

The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 10: Configuration Register. The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: 1. Depending on whether t AVK_CPU or tDELAY is supplied either one of the following two equations must be satisfied: (n + 1) tK ≥ tAVQV - tAVK_CPU + tQVK_CPU (n + 2) tK ≥ tAVQV + tDELAY + tQVK_CPU 2. and also tK > tKQV + tQVK_CPU where

• n is the chosen X-Latency configuration code
• tK is the clock period
• tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last
• tDELAY is address valid, L Low, or E Low to clock, whichever occurs last
• tQVK_CPU is the data setup time required by the system CPU,
• tKQV is the clock to data valid time
• tAVQV is the random access time of the device.

6 Configuration Register M58LT128GST, M58LT128GSB

Refer to Figure 5: X-Latency and Data Output Configuration Example.

6.3 Wait Polarity Bit (CR10)

The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst Read mode. During Synchronous Burst Read mode the Wait signal indicates whether the data output are valid or a WAIT state must be inserted. When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait Polarity bit is set to ‘1’ the Wait signal is active High.

6.4 Data Output Configuration Bit (CR9)

The Data Output Configuration bit is used to configure the output to remain valid for either one or two clock cycles during synchronous mode. When the Data Output Configuration Bit is ’0’ the output data is valid for one clock cycle, when the Data Output Configuration Bit is ’1’ the output data is valid for two clock cycles. The Data Output Configuration must be configured using the following condition:

• tK > tKQV + tQVK_CPU where
• tK is the clock period
• tQVK_CPU is the data setup time required by the system CPU
• tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 5: X-Latency and Data Output Configuration Example.

6.5 Wait Configuration Bit (CR8)

The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in Synchronous Burst Read mode. When WAIT is asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid. When the Wait Configuration bit is Low (set to ’0’) the Wait output pin is asserted during the WAIT state. When the Wait Configuration bit is High (set to ’1’), the Wait output pin is asserted one data cycle before the WAIT state.

6.6 Burst Type Bit (CR7)

The Burst Type bit determines the sequence of addresses read during Synchronous Burst Reads. The Burst Type bit is High (set to ’1’), as the memory outputs from sequential addresses only. See Table 11: Burst Type Definition, for the sequence of addresses output from a given starting address in sequential mode.

M58LT128GST, M58LT128GSB 6 Configuration Register

6.7 Valid Clock Edge Bit (CR6)

The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during synchronous read operations. When the Valid Clock Edge bit is Low (set to ’0’) the falling edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to ’1’) the rising edge of the Clock is the active edge.

6.8 Wrap Burst Bit (CR3)

The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous burst reads can be confined inside the 4, 8 or 16 Word boundary (wrap) or overcome the boundary (no wrap). When the Wrap Burst bit is Low (set to ‘0’) the burst read wraps. When it is High (set to ‘1’) the burst read does not wrap.

6.9 Burst length Bits (CR2-CR0)

The Burst Length bits are used to set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 Words, 8 Words, 16 Words or continuous burst, where all the Words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 Words no-wrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is aligned to an 8 Word boundary no WAIT states are needed and the WAIT output is not asserted. If the starting address is not aligned to the 8 Word boundary, WAIT will be asserted when the burst sequence crosses the first 16 Word boundary to indicate that the device needs an internal delay to read the successive Words in the array. In the worst case, the number of WAIT states is one clock cycle less than the latency setting. The exact number is reported in Table 12: Wait at the Boundary. WAIT will be asserted only once during a continuous burst access. See also Table 11: Burst Type Definition. CR14, CR5 and CR4 are reserved for future use.

Table 10. Configuration Register

0 Synchronous Read

1 Asynchronous Read (Default at power-on)

1. The combination X-Latency=2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not

0 WAIT is active Low (default)

1 WAIT is active High

0 Data held for one clock cycle

1 Data held for two clock cycles (default)

0 WAIT is active during WAIT state (default)

1 WAIT is active one data cycle before WAIT state(1)

0 Reserved

1 Sequential (default)

0 Falling Clock edge

1 Rising Clock edge (default)

1 No Wrap (default)

111 Continuous (default)

Table 11. Burst Type Definition

4 Words 8 Words 16 Words

Table 12. Wait at the Boundary Figure 5. X-Latency and Data Output Configuration Example

1. The settings shown are X-latency = 4, Data Output held for one clock cycle.

Figure 6. Wait Configuration Example

7 Read modes M58LT128GST, M58LT128GSB

7 Read modes

Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the Configuration Register. (See Configuration Register section for details). All banks support both asynchronous and synchronous read operations.

7.1 Asynchronous Read modes

In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for asynchronous operations. In Asynchronous Read mode, the WAIT signal is always deasserted. The device features an Automatic Standby mode. During Asynchronous Read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Read and Asynchronous Page Read.

7.1.1 Asynchronous Random Read

Asynchronous Random Read operations are controlled by the Latch Enable, L, signal. A valid bus operation involves setting the desired address on the Address Inputs, setting Chip Enable and Latch Enable Low, VIL, and keeping Write Enable High, VIH. The address is latched on the rising edge of Latch Enable, L, before the value is output on the data bus. Once latched, the Address Inputs can change. Set Output Enable Low, VIL, to read the data on the Data Inputs/Outputs. See Table 22: Asynchronous Read AC Characteristics, and Figure 9: Asynchronous Random Access Read AC Waveforms for details.

7.1.2 Asynchronous Page Read

Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. In Asynchronous Page Read mode, a Page of data is internally read and stored in a Page Buffer. The Page size is 8 Words and is addressed by address inputs A0, A1 and A2. The first read operation within the Page has the normal access time (t AVQV ), subsequent reads within the same Page have much shorter access times (tAVQV1 ). If the Page changes then the normal longer timings apply again. See Table 22: Asynchronous Read AC Characteristics, Figure 10: Asynchronous Page Read AC Waveforms for details.

M58LT128GST, M58LT128GSB 7 Read modes

7.2 Synchronous Burst Read modes

In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration Register. The number of Words to be output during a Synchronous Burst Read operation can be configured as 4 Words, 8 Words, 16 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Wrap Burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 Word boundary (Wrap) or overcome the boundary (No Wrap). The WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence and on the burst configuration. WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 Word burst. It is only deasserted when output data are valid or when G is at VIH. In Continuous Burst Read mode a WAIT state will occur when crossing the first 16 Word boundary. If the starting address is aligned to the Burst Length (4, 8 or 16 Words) the wrapped configuration has no impact on the output sequence. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 23: Synchronous Read AC Characteristics, and Figure 11: Synchronous Burst Read AC Waveforms, for details.

7.2.1 Synchronous Burst Read Suspend

A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) in which case the initial latency time can be reduced to zero, or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when Chip Enable, E , is Low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The Clock signal is then halted at V IH or at VIL, and Output Enable, G, goes High. When Output Enable, G, becomes Low again and the Clock signal restarts, the Synchronous Burst Read operation is resumed exactly where it stopped.

WAIT being gated by E, it will remain active and will not revert to high impedance when G goes High. So if two or more devices are connected to the system’s READY signal, to prevent bus contention the WAIT signal of the M58LT128GST and M58LT128GSB should not be directly connected to the system’s READY signal. WAIT will revert to high-impedance when Output Enable, G , or Chip Enable, E, goes High. See Table 23: Synchronous Read AC Characteristics, and Figure 13: Synchronous Burst Read Suspend AC Waveforms, for details.

7.2.2 Single Synchronous Read mode

Single Synchronous Read operations are similar to Synchronous Burst Read operations except that the memory outputs the same data to the end of the operation. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Configuration Register Status, or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is deasserted when Output Enable, G , is at VIH or for the one clock cycle during which output data is valid. Otherwise, it is asserted. See Table 23: Synchronous Read AC Characteristics, and Figure 11: Synchronous Burst Read AC Waveforms, for details.

8 Dual Operations and Multiple Bank architecture

flexibility for software developers to split the code and data spaces within the memory array. code to be executed from one bank while another bank is being programmed or erased. be in program or erase mode). program or erase operations. M58LT128GST and M58LT128GSB devices. between the CFI, the Electronic Signature locations and the memory array. Table 13 and Table 14 show the dual operations possible in other banks and in the same bank. Table 13. Dual Operations Allowed In Other Banks

8 Dual Operations and Multiple Bank architecture M58LT128GST, M58LT128GSB

Table 14. Dual Operations Allowed In Same Bank Table 15. Dual Operation Limitations

1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.
2. Not allowed in the Word that is being erased or programmed.

9 Program and Erase times and Endurance cycles

Table 16. Program/Erase Times and Endurance Cycles

9 Program and Erase times and Endurance cycles M58LT128GST, M58LT128GSB

VPP = VPPH Erase Parameter Block (16 KWord) 0.4 2.5 s Main Block (64 KWord) 1 4 s Program(3) Single Cell Word Program 30 60 µs Single Word Word Program 85 170 µs Buffer Enhanced Factory Program(4) 10 µs Buffer (32 Words) Buffer Program 340 680 µs Buffer Enhanced Factory Program 320 µs Main Block (64 KWords) Buffer Program 640 ms Buffer Enhanced Factory Program 640 ms Bank (16 Mbits) Buffer Program 10 s Buffer Enhanced Factory Program 10 s Program/Erase Cycles (per Block) Main Blocks 1000 cycles Parameter Blocks 2500 cycles 2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). 3. Excludes the time needed to execute the command sequence. 4. This is an average value on the entire device. Parameter Condition(1)(2) Min Typ Typical after 100kW/E Cycles Max Unit

10 Maximum Rating

other relevant quality documents. Table 17. Absolute Maximum Ratings

11 DC and AC parameters M58LT128GST, M58LT128GSB

11 DC and AC parameters

Table 18. Operating and AC Measurement Conditions Figure 7. AC Measurement I/O Waveform

Figure 8. AC Measurement Load Circuit Table 19. Capacitance

1. Sampled only, not 100% tested.

Table 20. DC Characteristics - Currents

4 Word 16 18 mA

8 Word 18 20 mA

16 Word 23 25 mA

1. Sampled only, not 100% tested.
2. V DD Dual Operation current is the sum of read and program or erase currents.

Table 21. DC Characteristics - Voltages

Figure 9. Asynchronous Random Access Read AC Waveforms Note. Write Enable, W, is High, WAIT is active Low.

Figure 10. Asynchronous Page Read AC Waveforms

Table 22. Asynchronous Read AC Characteristics

1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV .

Figure 11. Synchronous Burst Read AC Waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.

1. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge.
3. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.

Figure 12. Single Synchronous Read AC Waveforms Note 1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.

1. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can

be configured as the active edge. Here, the active edge is the rising one.

Figure 13. Synchronous Burst Read Suspend AC Waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. The CLOCK signal can be held high or low
3. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge.

Here, the active edge is the rising one.

Figure 14. Clock input AC Waveform Table 23. Synchronous Read AC Characteristics

1. Sampled only, not 100% tested.

For other timings please refer to Table 22: Asynchronous Read AC Characteristics.

Figure 15. Write AC Waveforms, Write Enable Controlled

Table 24. Write AC Characteristics, Write Enable Controlled

1. Sampled only, not 100% tested.
2. These timings are meaningful only if Latch Enable, L, is always kept Low, VIL.
3. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may

operation in a different bank tWHEL is 0ns.

Figure 16. Write AC Waveforms, Chip Enable Controlled

Table 25. Write AC Characteristics, Chip Enable Controlled

1. Sampled only, not 100% tested.
2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may

operation in a different bank tWHEL is 0ns.

Figure 17. Reset and Power-up AC Waveforms Table 26. Reset and Power-up AC Characteristics

1. The device Reset is possible but not guaranteed if tPLPH < 50ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.

Figure 18. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, Bottom View Package Outline Table 27. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, Package Mechanical Data

13 Part Numbering

Table 28. Ordering Information Scheme

13 Part Numbering M58LT128GST, M58LT128GSB

Table 29. Daisy Chain Ordering Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. this device, please contact the ST Sales Office nearest to you.

M58LT128GST, M58LT128GSB 13 Part Numbering Appendix A Block address tables The following set of equations can be used to calculate a complete set of block addresses for the M58LT128GST and M58LT128GSB using the information contained in Table 30 to Table 35. To calculate the Block Base Address from the Block Number: First it is necessary to calculate the Bank Number and the Block Number Offset. This can be achieved using the following formulas: Bank_Number = (Block_Number − 3) / 16 Block_Number_Offset = Block_Number − 3 − (Bank_Number x 16) If Bank_Number = 0, the Block Base Address can be directly read from Table 30 and Ta bl e 3 3 (Parameter Bank Block Addresses) in the Address Range column, in the row that corresponds to the given block number. Otherwise: Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset To calculate the Bank Number and the Block Number from the Block Base Address: If the address is in the range of the Parameter Bank, the Bank Number is 0 and the Block Number can be directly read from Table 30 for the M58LT128GST and Table 33 for the M58LT128GSB (Parameter Bank Block Addresses), in the Block Number column, in the row that corresponds to the address given. Otherwise, the Block Number can be calculated using the formulas below: For the top configuration (M58LT128GST): Block_Number = ((NOT address) / 2 16) + 3 For the bottom configuration (M58LT128GSB): Block_Number = (address / 216) + 3 For both configurations the Bank Number and the Block Number Offset can be calculated using the following formulas: Bank_Number = (Block_Number − 3) / 16 Block_Number_Offset = Block_Number − 3 − (Bank_Number x 16)

Table 30. M58LT128GST - Parameter Bank Block Addresses Table 31. M58LT128GST - Main Bank Base Addresses

1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank

Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).

Table 32. M58LT128GST - Block Addresses in Main Banks Table 33. M58LT128GSB - Parameter Bank Block Addresses

Table 34. M58LT128GSB- Main Bank Base Addresses

1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank

Region 1 contains the banks that are made up of the parameter and main blocks (Parameter Bank). Table 35. M58LT128GSB - Block Addresses in Main Banks

software to upgrade itself when necessary. by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read Array command to return to Read mode. Table 36. Query Structure Overview

1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-

Table 37. CFI Query Identification String Table 38. CFI Query System Interface Information

Table 39. Device Geometry Definition

Table 40. Primary Algorithm-Specific Extended Query Table contains less significant byte. bit field of optional features follows at the end of the bit-30 field.

Table 41. Protection Register Information Table 42. Burst Read Information

16 Bytes

width to determine the burst data output width. Synchronous mode read capability configuration 4 Cont.

Table 43. Bank and Erase Block Region Information

1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Table 30 to Table 35.

(P+23)h = 12Dh 02h (P+23)h = 12Dh 02h Number of Bank Regions within the device

Table 44. Bank and Erase Block Region 1 Information Symmetrically blocked banks have one blocking region(2).

1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank Regions. There are two Bank Regions, see Table 30 to Table 35. (P+32)h = 13Ch 06h Bank Region 1 Erase Block T ype 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+33)h = 13Dh 00h (P+34)h = 13Eh 00h (P+35)h = 13Fh 02h (P+36)h = 140h 64h Bank Region 1 (Erase Block T ype 2) Minimum block erase cycles × 1000(P+37)h = 141h 00h (P+38)h = 142h 02h Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+39)h = 143h 03h Bank Region 1 (Erase Block T ype 2): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Flash memory (top) Flash memory (bottom) Description Offset Data Offset Data

M58LT128GST, M58LT128GSB 13 Part Numbering Table 45. Bank and Erase Block Region 2 Information (P+32)h = 13Ch 01h (P+3A)h = 144h 0Fh Number of identical banks within Bank Region 2 (P+33)h = 13Dh 00h (P+3B)h = 145h 00h (P+34)h = 13Eh 11h (P+3C)h = 146h 11h Number of program or erase operations allowed in Bank Region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+35)h = 13Fh 00h (P+3D)h = 147h 00h Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+36)h = 140h 00h (P+3E)h = 148h 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+37)h = 141h 02h (P+3F)h = 149h 01h Types of erase block regions in Bank Region 2 n = number of erase block regions with contiguous same- size erase blocks. Symmetrically blocked banks have one blocking region. (2) (P+38)h = 142h 06h (P+40)h = 14Ah 07h Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+39)h = 143h 00h (P+41)h = 14Bh 00h (P+3A)h = 144h 00h (P+42)h = 14Ch 00h (P+3B)h = 145h 02h (P+43)h = 14Dh 02h (P+3C)h = 146h 64h (P+44)h = 14Eh 64h Bank Region 2 (Erase Block T ype 1) Minimum block erase cycles × 1000(P+3D)h = 147h 00h (P+45)h = 14Fh 00h (P+3E)h = 148h 02h (P+46)h = 150h 02h Bank Region 2 (Erase Block T ype 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+3F)h = 149h 03h (P+47)h = 151h 03h Bank Region 2 (Erase Block T ype 1):Page mode and Synchronous mode capabilities (defined in Table 42) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+40)h = 14Ah 03h Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+41)h = 14Bh 00h (P+42)h = 14Ch 80h (P+43)h = 14Dh 00h

1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank Regions. There are two Bank Regions, see Table 30 to Table 32 for the M58LT128GST and Table 33 to Table 35 for the M58LT128GSB. (P+44)h = 14Eh 64h Bank Region 2 (Erase Block Type 2) Minimum block erase cycles × 1000(P+45)h = 14Fh 00h (P+46)h = 150h 02h Bank Region 2 (Erase Block T ype 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+47)h = 151h 03h Bank Region 2 (Erase Block T ype 2): Page mode and Synchronous mode capabilities (defined in Table 42) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+48)h = 152h (P+48)h = 152h Feature Space definitions (P+49)h = 153h (P+43)h = 153h Reserved Flash memory (top) Flash memory (bottom)

Figure 19. Program Flowchart and Pseudo Code

1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 20. Buffer Program Flowchart and Pseudo Code

1. n + 1 is the number of data being programmed.
2. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to
3. Routine for Error Check by reading SR3, SR4 and SR1.

Figure 21. Program Suspend & Resume Flowchart and Pseudo Code

1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.

Figure 22. Block Erase Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.

Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code

1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.

Figure 24. Protection Register Program Flowchart and Pseudo Code

Figure 25. Buffer Enhanced Factory Program Flowchart and Pseudo Code

1. For how to check the targeted block protection status, refer to the Application Note concerning the device security features.

Table 46. Command Interface States - Modify Table, Next State

M58LT128GST, M58LT128GSB 13 Part Numbering Buffer Program in Erase Suspend Setup Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N not =0) go to Buffer Program Load 2 Buffer Load

1 Buffer Program Load 2 in Erase Suspend (data load)

Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program will fail at this point if any block address is different from the first address) Confirm Ready (error) Buffer Program Busy in Erase Suspend Ready (error) Busy Buffer Program Busy in Erase Suspend Buffer Program Suspend in Erase Suspend Buffer Program Busy in Erase Suspend Suspend Buffer Program Suspend in Erase Suspend Buffer Program Busy in Erase Suspend Buffer Program Suspend in Erase Suspend Lock/CR Setup in Erase Suspend Erase Suspend (Lock Error) Erase Suspend Erase Suspend (Lock Error) Buffer EFP Setup Ready (error) BEFP Busy Ready (error) Busy BEFP Busy(6) 1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/ Erase Controller. 2. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E.C. is active, both cycles are ignored. 5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 6. BEFP is allowed only when Status Register bit SR0 is set to ‘0’. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data. Current CI State Command Input (1) Read Array (FFh)(2) Program Setup (10/40h) (3)(4) Buffer Program (E8h)(3)(4) Block Erase, Setup (20h) (3)(4) BEFP Setup (80h) Erase Confirm P/E Resume, BEFP Confirm(D0h) (3)(4) Buffer Program, Program/ Erase Suspend (B0h) Read Status Register (70h) Clear status Register (50h)(5) Read Electronic Signature, Read CFI Query (90h, 98h)

Table 47. Command Interface States - Modify Table, Next Output State

Table 48. Command Interface States - Lock Table, Next State

1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command

depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank output state.

1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/
2. At Power-Up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined
3. The two cycle command should be issued to the same bank address.
4. If the P/E.C. is active, both cycles are ignored.

1 Buffer Program Load 2(5) Exit see note(5) N/A

1 Buffer Program Load 2 in Erase Suspend(6) Exit see note (6)

Erase Suspend (Lock error) Erase Suspend Erase Suspend (Lock error) N/A BEFP Setup Ready (error) N/A Busy BEFP Busy(7) Exit BEFP Busy(7) N/A 1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/ Erase Controller, WA0 = Address in a block different from first BEFP address. 2. If the P/E.C. is active, both cycles are ignored. 3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 4. Illegal commands are those not defined in the command set. 5. if N=0 go to Buffer Program Confirm. Else (N ≠ 0) go to Buffer Program Load 2 (data load). 6. if N=0 go to Buffer Program Confirm in Erase Suspend. Else (N ≠ 0) go to Buffer Program Load 2 in Erase Suspend. 7. BEFP is allowed only when Status Register bit SR0 is set to ‘0’. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data. Current CI State Command Input (1)(2) Lock/CR Setup(60h)(2) Set CR Confirm (03h) Block Address (WA0) (XXXXh)(3) Illegal Command(4) WSM Operation Completed

Table 49. Command Interface States - Lock Table, Next Output State

1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command

depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank's output state.

1. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/ Erase Controller, WA0 = Address in a block different from first BEFP address. 3. If the P/E.C. is active, both cycles are ignored. 4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh. 5. Illegal commands are those not defined in the command set.

Table 50. Document Revision History 16-Nov-2004 0.1 First Issue. Table 22: Asynchronous Read AC Characteristics for tAVQV1 . WP and R pins removed from Figure 1: Logic Diagram. Figure 16: Write AC Waveforms, Chip Enable Controlled. 80ns speed class chagned into 85ns. tWHQV removed from Figure 15, Figure 16. Table 22, Table 23 and Table 26 updated. Synchronous Read AC Characteristics. Burst frequency chagned from 54 to 52MHz. VIO maximum value updated in Table 17: Absolute Maximum Ratings. tAVLH and tLLLH updated in Table 22: Asynchronous Read AC Characteristics. tAVKH , tELKH and tLLKH updated in Table 23: Synchronous Read AC Characteristics. Controlled and Table 25: Write AC Characteristics, Chip Enable Controlled.

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