M58LR128KB

M58LR128KT NUMONYX | Alldatasheet

Document overview

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• PDF pages: 110

Technical content

Datasheet sections

• 1 Description
• 2 Signal descriptions
• 2.1 Address inputs (A0-Amax)
• 2.2 Data inputs/outputs (DQ0-DQ15)
• 2.3 Chip Enable (E )
• 2.4 Output Enable (G )
• 2.5 Write Enable (W )
• 2.6 Write Protect (WP )
• 2.7 Reset (RP )
• 2.8 Latch Enable (L )
• 2.9 Clock (K)
• 2.10 Wait (WAIT)
• 2.12 V DDQ supply voltage
• 2.13 V PP program supply voltage
• 2.14 V SS ground
• 2.15 V SSQ ground
• 3 Bus operations
• 3.1 Bus read
• 3.2 Bus write
• 3.3 Address Latch
• 3.4 Output disable
• 3.5 Standby
• 3.6 Reset
• 4 Command interface
• 4.1 Read Array command
• 4.2 Read Status Register command
• 4.3 Read Electronic Signature command
• 4.4 Read CFI Query command

Datasheet sections

• 6.7 Valid Clock edge bit (CR6)
• 6.8 Wrap burst bit (CR3)
• 6.9 Burst length bits (CR2-CR0)
• 7 Read modes
• 7.1 Asynchronous read mode
• 7.2 Synchronous burst read mode
• 7.2.1 Synchronous burst read suspend
• 7.3 Single synchronous read mode
• 8 Dual operations and multiple bank architecture
• 9 Block locking
• 9.1 Reading block lock status
• 9.2 Locked state
• 9.3 Unlocked state
• 9.4 Lock-down state
• 9.5 Locking operations during erase suspend
• 10 Program and erase times and endurance cycles
• 11 Maximum ratings
• 12 DC and AC parameters
• 13 Part numbering
• 14 Revision history

Features

■ Supply voltage –V DD = 1.7 V to 2.0 V for program, erase and read –V DDQ = 1.7 V to 2.0 V for I/O buffers –V PP = 9 V for fast program ■ Synchronous/asynchronous read – Synchronous burst read mode:

54 MHz, 66 MHz

– Asynchronous page read mode – Random access: 70 ns, 85 ns ■ Synchronous burst read suspend ■ Programming time – 2.5 µs typical word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple bank memory array:

8 Mbit banks for the M58LR128KT/B

16 Mbit banks for the M58LR256KT/B

– Parameter blocks (top or bottom location) ■ Dual operations – Program/erase in one bank while read in others – No delay between read and write operations ■ Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency –W P for block lock-down – Absolute write protection with V PP = VSS ■ Security – 64 bit unique device number – 2112 bit user programmable OTP cells ■ Common Flash interface (CFI) ■ 100 000 program/erase cycles per block ■ Electronic signature – Manufacturer code: 20h – Top device codes: M58LR128KT: 88C4h M58LR256KT: 880Dh – Bottom device codes M58LR128KB: 88C5h M58LR256KB: 880Eh The M58LRxxxKT/B memories are only available as part of a multichip package. Not packaged separately www.numonyx.com

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Contents 5.5 V

Description M58LR128KT, M58LR1 28KB, M58LR256KT, M58LR256KB

1 Description

The M58LR128KT/B and M58LR256KT/B are 128 Mbit (8 Mbit ×16) and 256 Mbit (16 Mbit ×16) non-volatile Flash memories, respectively. They can be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to accelerate factory programming. The devices feature an asymmetrical block architecture:

• The M58LR128KT/B have an array of 131 blocks, and are divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 7 main blocks of 64 Kwords.
• The M58LR256KT/B have an array of 259 blocks, and are divided into 16 Mbit banks. There are 15 banks each containing 16 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 15 main blocks of 64 Kwords. The multiple bank architecture allows dual operations. While programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure 2. The parameter blocks are located at the top of the memory address space for the M58LR128KT and M58LR256KT, and at the bottom for the M58LR128KB and M58LR256KB. Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage V DD. There is a buffer enhanced factory programming command available to speed up programming. Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 66 MHz. The synchronous burst read operation can be suspended and resumed. The device features an automatic standby mode. When the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. The M58LRxxxKT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V PP ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at power-up.

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Description The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 one-time-programmable (OTP) Protection Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment OTP by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register memory map. The M58LRxxxKT/B are only available as part of a multichip package. The devices are supplied with all the bits erased (set to ’1’).

Figure 1. Logic diagram

1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.

Table 1. Signal names

1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.

Figure 2. M58LR128K T/B memory map Table 2. M58LR128KT/B bank architecture

8 Main

64 Kword000000h

64 Kword070000h

64 Kword600000h

64 Kword670000h

64 Kword680000h

64 Kword6F0000h

64 Kword700000h

64 Kword770000h

64 Kword780000h

64 Kword7E0000h

16 Kword7F0000h

16 Kword7FC000h

4 Parameter

16 Kword000000h

16 Kword00C000h

64 Kword010000h

64 Kword080000h

64 Kword0F0000h

64 Kword100000h

64 Kword170000h

64 Kword180000h

64 Kword1F0000h

64 Kword7F0000h

7 Main

Figure 3. M58LR256K T/B memory map Table 3. M58LR256KT/B bank architecture

16 Main

64 KwordC00000h

64 KwordCF0000h

64 KwordD00000h

64 KwordDF0000h

64 KwordE00000h

64 KwordEF0000h

64 KwordF00000h

64 KwordFE0000h

16 KwordFF0000h

16 KwordFFC000h

64 Kword200000h

64 Kword2F0000h

64 Kword300000h

64 Kword3F0000h

64 KwordFF0000h

15 Main

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Signal descriptions

2 Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals connected to this device.

2.1 Address inputs (A0-Amax)

Amax is the highest order address input. It is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. The address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the Program/Erase Controller.

2.2 Data inputs/outputs (DQ0-DQ15)

The data I/O output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation.

2.3 Chip Enable (E )

The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V ILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.

2.4 Output Enable (G )

The Output Enable input controls data outputs during the bus read operation of the memory.

2.5 Write Enable (W )

The Write Enable input controls the bus write operation of the memory’s command interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable, whichever occurs first.

2.6 Write Protect (WP )

Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V IL, the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. When Write Protect is at VIH, the lock-down is disabled and the locked-down blocks can be locked or unlocked. (refer to Table 17: Lock status).

Signal descriptions M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

2.7 Reset (RP )

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset supply current I DD2. Refer to Table 22: DC characteristics - currents for the value of IDD2. After Reset all blocks are in the locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, and a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs.

2.8 Latch Enable (L )

Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at V IL and it is inhibited when Latch Enable is at VIH.

2.9 Clock (K)

The Clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at V IL. Clock is ignored during asynchronous read and in write operations.

2.10 Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at V IH, Output Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance.

2.11 V DD supply voltage

VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase).

2.12 V DDQ supply voltage

VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply.

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Signal descriptions

2.13 V PP program supply voltage

VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK provides absolute protection against program or erase, while VPP in the VPP1 range enables these functions (see Tables 22 and 23, DC characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase. A change in its value after the operation has started does not have any effect and program or erase operations continue. If V PP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the program/erase algorithm is completed.

2.14 V SS ground

VSS ground is the reference for the core supply. It must be connected to the system ground.

2.15 V SSQ ground

VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS Note: Each device in a system should have V DD, VDDQ and VPP decoupled with a 0.1 µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 8: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.

Bus operations M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

3 Bus operations

There are six standard bus operations that control the device. These are bus read, bus write, address latch, output disable, standby and reset. See Table 4: Bus operations for a summary. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus write operations.

3.1 Bus read

Bus read operations are used to output the contents of the memory array, the electronic signature, the Status Register and the Common Flash interface. Both Chip Enable and Output Enable must be at V IL to perform a read operation. The Chip Enable input should be used to enable the device, and Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see command interface section). See Figures 9, 10 and 11 read AC waveforms, and Tables 24 and 25 read AC characteristics for details of when the output becomes valid.

3.2 Bus write

Bus write operations write commands to the memory or latch input data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at V IL with Output Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the write operation by toggling Latch Enable (when Chip Enable is at V IL). The Latch Enable must be tied to VIH during the bus write operation. See Figures 15 and 16, write AC waveforms, and Tables 26 and 27, write AC characteristics for details of the timing requirements.

3.3 Address Latch

Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at V IL during address latch operations. The addresses are latched on the rising edge of Latch Enable.

3.4 Output disable

The outputs are high impedance when the Output Enable is at VIH.

3.5 Standby

during a program or erase operation, the device enters standby mode when finished.

3.6 Reset

Table 4. Bus operations (1)

1. WAIT signal polarity is configured us ing the Set Configuration Register command.
2. L can be tied to VIH if the valid address has been previously latched.

4 Command interface

All bus write operations to the memory are interpreted by the command interface. whose output may be read at any time to monitor the progress or the result of the operation. DD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands are ignored. Table 5. Command codes

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Command interface

4.1 Read Array command

The Read Array command returns the addressed bank to read array mode. One bus write cycle is required to issue the Read Array command. Once a bank is in read array mode, subsequent read operations outputs the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank returns to read array mode but the program or erase operation continues, however the data output from the bank is not guaranteed until the program or erase operation has finished. The read modes of other banks are not affected.

4.2 Read Status Register command

The device contains a Status Register that monitors program or erase operations. The Read Status Register command reads the contents of the Status Register for the addressed bank. One bus write cycle is required to issue the Read Status Register command. Once a bank is in read Status Register mode, subsequent read operations output the contents of the Status Register. The Status Register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the Status Register data. The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command only changes the read mode of the addressed bank. The read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the Status Register. A Read Array command is required to return the bank to read array mode. See Table 10 for the description of the Status Register bits.

Command interface M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

4.3 Read Electronic Signature command

The Read Electronic Signature command reads the manufacturer and device codes, the lock status of the addressed bank, the Protection Register, and the Configuration Register. One bus write cycle is required to issue the Read Electronic Signature command. Once a bank is in read electronic signature mode, subsequent read operations in the same bank output the manufacturer code, the device code, the lock status of the addressed bank, the Protection Register, or the Configuration Register (see Table 9). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during Protection Register Program operations. Dual operations between the parameter bank and the electronic signature location are not allowed (see Table 16: Dual operation limitations for details). If a Read Electronic Signature command is issued to a bank that is executing a program or erase operation, the bank goes into read electronic signature mode. Subsequent bus read cycles output the electronic signature data and the Program/Erase Controller continue to program or erase in the background. The Read Electronic Signature command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read the electronic signature. A Read Array command is required to return the bank to read array mode.

4.4 Read CFI Query command

The Read CFI Query command reads data from the common Flash interface (CFI). One bus write cycle is required to issue the Read CFI Query command. Once a bank is in read CFI query mode, subsequent bus read operations in the same bank read from the common Flash interface. The Read CFI Query command can be issued at any time, even during program or erase operations. If a Read CFI Query command is issued to a bank that is executing a program or erase operation the bank gos into read CFI query mode. Subsequent bus read cycles output the CFI data and the Program/Erase Controller continues to program or erase in the background. The Read CFI Query command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read from the CFI. A Read Array command is required to return the bank to read array mode. Dual operations between the parameter bank and the CFI memory space are not allowed (see Table 16: Dual operation limitations for details). See Appendix B: Common Flash interface and Tables 42, 43, 44, 45, 46, 47, 48, 49, 50 and 51 for details on the information contained in the common Flash interface memory area.

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Command interface

4.5 Clear Status Register command

The Clear Status Register command resets (set to ‘0’) all error bits (SR1, 3, 4 and 5) in the Status Register. One bus write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the read mode of the bank. The error bits in the Status Register do not automatically return to ‘0’ when a new command is issued. The error bits in the Status Register should be cleared before attempting a new program or erase command.

4.6 Block Erase command

The Block Erase command erases a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the erase operation aborts, the data in the block does not change and the Status Register outputs the error. Two bus write cycles are required to issue the command.

• The first bus cycle sets up the Block Erase command.
• The second latches the block address and starts the Program/Erase Controller. If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5 are set and the command is aborted. Once the command is issued the bank enters Read Status Register mode and any read operation within the addressed bank outputs the contents of the Status Register. A Read Array command is required to return the bank to read array mode. During block erase operations the bank containing the block being erased only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend commands; all other commands are ignored. The block erase operation aborts if Reset, RP , goes to VIL. As data integrity cannot be guaranteed when the block erase operation is aborted, the block must be erased again. Refer to Section 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being erased. Typical erase times are given in Table 18: Program/erase times and endurance cycles. See Appendix C, Figure 22: Block erase flowchart and pseudocode for a suggested flowchart for using the Block Erase command.

Command interface M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

4.7 Blank Check command

The Blank Check command checks whether a main array block has been completely erased. Only one block at a time can be checked. To use the Blank Check command VPP must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the command and no error is shown in the Status Register. Two bus cycles are required to issue the Blank Check command:

• The first bus cycle writes the Blank Check command (BCh) to any address in the block to be checked.
• The second bus cycle writes the Blank Check Confirm command (CBh) to any address in the block to be checked and starts the blank check operation. If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are set to '1' and the command aborts. Once the command is issued, the addressed bank automatically enters the Status Register mode and further reads within the bank output the Status Register contents. The only operation permitted during blank check is Read Status Register. Dual operations are not supported while a blank check operation is in progress. Blank check operations cannot be suspended and are not allowed while the device is in program/erase suspend. The SR7 Status Register bit indicates the status of the blank check operation in progress. SR7 = '0' means that the Blank Check operation is still ongoing, and SR7 = '1' means that the operation is complete. The SR5 Status Register bit goes High (SR5 = '1') to indicate that the blank check operation has failed. At the end of the operation the bank remains in the read Status Register mode until another command is written to the command interface. See Appendix C, Figure 19: Blank check flowchart and pseudocode for a suggested flowchart for using the Blank Check command. Typical blank check times are given in Table 18: Program/erase times and endurance cycles.

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Command interface

4.8 Program command

The Program command programs a single word to the memory array. If the block being programmed is protected, then the program operation aborts, the data in the block does not change and the Status Register outputs the error. Two bus write cycles are required to issue the Program command:

• The first bus cycle sets up the Program command.
• The second latches the address and data to be programmed and starts the Program/Erase Controller. Once the programming has started, read operations in the bank being programmed output the Status Register content. During a program operation, the bank containing the word being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend commands; all other commands are ignored. A Read Array command is required to return the bank to read array mode. Refer to Section 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being programmed. Typical program times are given in Table 18: Program/erase times and endurance cycles. The program operation aborts if Reset, RP , goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the word must be reprogrammed. See Appendix C, Figure 18: Program flowchart and pseudocode for the flowchart for using the Program command.

4.9 Buffer Program command

The Buffer Program Command uses the device’s 32-word write buffer to speed up programming. Up to 32 words can be loaded into the write buffer. The Buffer Program command dramatically reduces in-system programming time compared to the standard non- buffered Program command. Four successive steps are required to issue the Buffer Program command: 1. The first bus write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. After the first bus write cycle, read operations in the bank output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to update the Status Register contents. 2. The second bus write cycle sets up the number of words to be programmed. Value n is written to the same block address, where n+1 is the number of words to be programmed.

Command interface M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 3. Use n+1 bus write cycles to load the address and data for each word into the write buffer. Addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. Optimum performance is obtained when the start address corresponds to a 32 word boundary. 4. The final bus write cycle confirms the Buffer Program command and starts the program operation. All the addresses used in the Buffer Program operation must lie within the same block. Invalid address combinations or failing to follow the correct sequence of bus write cycles sets an error in the Status Register and aborts the operation without affecting the data in the memory array. If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program command is not accepted. Clear the Status Register before re-issuing the command. If the block being programmed is protected an error sets in the Status Register and the operation aborts without affecting the data in the memory array. During Buffer Program operations the bank being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend commands; all other commands are ignored. Refer to Section 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 20: Buffer program flowchart and pseudocode for a suggested flowchart on using the Buffer Program command.

4.10 Buffer Enhanced Factory Program command

The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. It is used to program one or more write buffer(s) of 32 words to a block. Once the device enters Buffer Enhanced Factory Program mode, the write buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. If the block being programmed is protected, then the Program operation aborts the data in the block does not change, and the Status Register outputs the error. The use of the Buffer Enhanced Factory Program command requires the following operating conditions:

• VPP must be set to VPPH
• VDD must be within operating range
• Ambient temperature TA must be 30°C ± 10°C
• The targeted block must be unlocked
• The start address must be aligned with the start of a 32 word buffer boundary
• The address must remain the start address throughout programming. Dual operations are not supported during the Buffer Enhanced Factory Program operation and the command cannot be suspended.

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Command interface The Buffer Enhanced Factory Program Command consists of three phases: the setup phase, the program and verify phase, and the exit phase, Please refer to Table 7: Factor y commands for detailed information.

4.10.1 Setup phase

The Buffer Enhanced Factory Program command requires two bus write cycles to initiate the command:

• The first bus write cycle sets up the Buffer Enhanced Factory Program command.
• The second bus write cycle confirms the command. After the confirm command is issued, read operations output the contents of the Status Register. The Read Status Register command must not be issued or it is interpreted as data to program. The Status Register P/EC bit SR7 should be read to check that the P/EC is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program operation is terminated. See Section 5: Status Register for details on the error.

4.10.2 Program an d verify phase

The program and verify phase requires 32 cycles to program the 32 words to the write buffer. The data is stored sequentially, starting at the first address of the write buffer, until the write buffer is full (32 words). To program less than 32 words, the remaining words should be programmed with FFFFh. Three successive steps are required to issue and execute the program and verify phase of the command: 1. Use one bus write operation to latch the start address and the first word to be programmed. The Status Register bank write status bit SR0 should be read to check that the P/EC is ready for the next word. 2. Each subsequent word to be programmed is latched with a new bus write operation. The address must remain the start address as the P/EC increments the address location. If any address is given that is not in the same block as the start address, the program and verify phase terminates. Status Register bit SR0 should be read between each bus write cycle to check that the P/EC is ready for the next word. 3. Once the write buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary. The program and verify phase can be repeated, without re-issuing the command, to program additional 32 word locations as long as the address remains in the same block. 4. Finally, after all words, or the entire block have been programmed, write one bus write operation to any address outside the block containing the start address, to terminate program and verify phase. Status Register bit SR0 must be checked to determine whether the program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed.

Command interface M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

4.10.3 Exit phase

Status Register P/EC bit SR7 set to ‘1’ indicates that the device has exited the buffer enhanced factory program operation and returned to read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See Section 5: Status Register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm continues to work properly but some degradation in performance is possible. Typical program times are given in Table 18. See Appendix C, Figure 26: Buffer enhanced factory program flowchart and pseudocode for a suggested flowchart on using the Buffer Enhanced Factory Program command.

4.11 Program/Erase Suspend command

The Program/Erase Suspend command pauses a program or block erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register are set to ‘1’. The following commands are accepted during Program/Erase Suspend: – Program/Erase Resume – Read Array (data from erase-suspended block or program-suspended word is not valid) – Read Status Register – Read Electronic Signature – Read CFI Query – Clear Status Register Additionally, if the suspended operation was a block erase then the following commands are also accepted: – Set Configuration Register – Program (except in erase-suspended block) – Buffer Program (except in erase suspended blocks) – Block Lock – Block Lock-Down – Block Unlock. During an erase suspend the block being erased can be protected by issuing the Block Lock or Block Lock-Down commands. When the Program/Erase Resume command is issued the operation completes. It is possible to accumulate multiple suspend operations. For example,it is possible to suspend an erase operation, start a program operation, suspend the program operation, and then read the array.

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Command interface If a Program command is issued during a block erase suspend, the erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in read Status Register, read electronic signature or read CFI query mode, the bank remains in that mode and outputs the corresponding data. Refer to Section 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to V IH. Program/erase is aborted if Reset, RP, goes to VIL. See Appendix C, Figure 21: Program suspend and resume flowchart and pseudocode, and Figure 23: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Program/Erase Suspend command.

4.12 Program/Erase Resume command

The Program/Erase Resume command restarts the program or erase operation suspended by the Program/Erase Suspend command. One bus write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in read Status Register, read electronic signature or read CFI query mode the bank remains in that mode and outputs the corresponding data. If a program command is issued during a block erase suspend, then the erase cannot be resumed until the program operation has completed. See Appendix C, Figure 21: Program suspend and resume flowchart and pseudocode, and Figure 23: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Program/Erase Resume command.

4.13 Protection Register Program command

The Protection Register Program command programs the user OTP segments of the Protection Register and the two Protection Register locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown in Figure 4: Protection Register memory map. The segments are programmed one word at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two bus write cycles are required to issue the Protection Register Program command.

• The first bus cycle sets up the Protection Register Program command.
• The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the program operation has started. Attempting to program a previously protected Protection Register results in a Status Register error.

Command interface M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB The Protection Register Program cannot be suspended. Dual operations between the parameter bank and the Protection Register memory space are not allowed (see Table 16: Dual operation limitations for details) The two Protection Register locks protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 4: Protection Register memory map and Table 9: Protection Register locks for details on the lock bits. See Appendix C, Figure 25: Protection Register program flowchart and pseudocode for a flowchart for using the Protection Register Program command.

4.14 Set Configuration Register command

The Set Configuration Register command writes a new value to the Configuration Register. Two bus write cycles are required to issue the Set Configuration Register comman:

• The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content.
• The second cycle writes the Configuration Register data and the confirm command. The Configuration Register data must be written as an address during the bus write cycles, that is A0 = CR0, A1 = CR1, …, A15 = CR15. Addresses A16-A22 are ignored. Read operations output the array content after the Set Configuration Register command is issued. The Read Electronic Signature command is required to read the updated contents of the Configuration Register.

4.15 Block Lock command

The Block Lock command locks a block and prevent program or erase operations from changing the data in it. All blocks are locked after power-up or reset. Two bus write cycles are required to issue the Block Lock command:

• The first bus cycle sets up the Block Lock command.
• The second bus write cycle latches the block address and locks the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 17 shows the lock status after issuing a Block Lock command. Once set, the block lock bits remain set even after a hardware reset or power-down/power- up. They are cleared by a Block Unlock command. Refer to Section 9: Block locking for a detailed explanation. See Appendix C, Figure 24: Locking operations flowchart and pseudocode for a flowchart for using the Lock command.

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Command interface

4.16 Block Unlock command

The Block Unlock command unlocks a block, allowing the block to be programmed or erased. Two bus write cycles are required to issue the Block Unlock command:

• The first bus cycle sets up the Block Unlock command.
• The second bus write cycle latches the block address and unlocks the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 17 shows the protection status after issuing a Block Unlock command. Refer to Section 9: Block locking for a detailed explanation and Appendix C, Figure 24: Locking operations flowchart and pseudocode for a flowchart for using the Block Unlock command.

4.17 Block Lock-Down command

The Block Lock-Down command is used to lock down a locked or unlocked block. A locked-down block cannot be programmed or erased. The lock status of a locked-down block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two bus write cycles are required to issue the Block Lock-Down command:

• The first bus cycle sets up the Block Lock-Down command.
• The second bus write cycle latches the block address and locks down the block. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 17 shows the lock status after issuing a Block Lock-Down command. Refer to Section 9: Block locking for a detailed explanation and Appendix C, Figure 24: Locking operations flowchart and pseudocode for a flowchart for using the Lock-Down command.

Table 6. Standard commands (1)

1. X = Don't Care, WA = Word Address in targeted bank, RD =Read Data, SRD =Status Register Data,
2. Must be same bank as in the first cyc le. The signature addresses are listed in Table 8.
3. Any address within the bank can be used.
4. n+1 is the number of words to be programmed.

Table 7. Factory commands

1. WA = Word Address in targeted bank, BKA = Bank Addr ess, PD =Program Data, BA = Block Address, X =
2. Any address within the bank can be used.
3. The program/verify phase can be executed any number of times as long as the data is to be programmed
4. WA 1 is the start address, NOT BA1 = Not Block Address of WA1.

Table 8. Electronic signature codes

1. CR = Configuration Register, PRLD = Protection Register Lock Data.

Figure 4. Protection Register memory map

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Command interface Table 9. Protection Register locks

Description

Bit 0 Preprogrammed to protect unique device number, address 81h to 84h in PR0 Bit 1 Protects 64 bits of OTP segment, address 85h to 88h in PR0 Bits 2 to 15 Reserved Lock 2 89h Bit 0 Protects 128 bits of OTP segment PR1 Bit 1 Protects 128 bits of OTP segment PR2 Bit 2 Protects 128 bits of OTP segment PR3 ---- ---- Bit 13 Protects 128 bits of OTP segment PR14 Bit 14 Protects 128 bits of OTP segment PR15 Bit 15 Protects 128 bits of OTP segment PR16

Status Register M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

5 Status Register

The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register (refer to Section 4.2: Read Status Register command for more details). To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to V IH. The Status Register can only be read using single Asynchronous or single synchronous reads. Bus read operations from any address within the bank always read the Status Register during program and erase operations if no Read Array command has been issued. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 10: Status Register bits. Refer to Table 10 in conjunction with the following text descriptions.

5.1 Program/Erase Controller status bit (SR7)

The Program/Erase Controller status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller status bit is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High.

5.2 Erase suspend status bit (SR6)

The erase suspend status bit indicates that an erase operation has been suspended in the addressed block. When the erase suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The erase suspend status bit should only be considered valid when the Program/Erase Controller status bit is High (Program/Erase Controller inactive). SR6 is set within the erase suspend latency time of the Program/Erase Suspend command being issued, therefore, the memory may still complete the operation rather than entering the suspend mode. When a Program/Erase Resume command is issued the erase suspend status bit returns Low.

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Status Register

5.3 Erase/blank check status bit (SR5)

The erase/blank check status bit identifies if there was an error during a block erase operation. When the erase/blank check status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that it has erased correctly. The erase/blank check status bit should be read once the Program/Erase Controller status bit is High (Program/Erase Controller inactive). The erase/blank check status bit is also used to indicate whether an error occurred during the blank check operation. If the data at one or more locations in the block where the Blank Check command has been issued is different from FFFFh, SR5 is set to '1'. Once set High, the erase/blank check status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is issued, otherwise the new command appears to fail.

5.4 Program status bit (SR4)

The program status bit identifies if there was an error during a program operation. It should be read once the Program/Erase Controller status bit is High (Program/Erase Controller inactive). When the program status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the word and still failed to verify that it has programmed correctly. Attempting to program a '1' to an already programmed bit while V PP = VPPH also sets the program status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0') and the attempt is not shown. Once set High, the program status bit must be set Low by a Clear Status Register command or a hardware reset before a new program command is issued, otherwise the new command appears to fail.

5.5 V PP status bit (SR3)

The VPP status bit identifies an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an operation When the VPP status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid voltage. When the VPP status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP lockout voltage, VPPLK, the memory is protected and program and erase operations cannot be performed. Once set High, the VPP status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command appears to fail.

Status Register M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

5.6 Program suspend status bit (SR2)

The program suspend status bit indicates that a program operation has been suspended in the addressed block. The program suspend status bit should only be considered valid when the Program/Erase Controller status bit is High (Program/Erase Controller inactive). When the program suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. SR2 is set within the program suspend latency time of the Program/Erase Suspend command being issued, therefore, the memory may still complete the operation rather than entering the suspend mode. When a Program/Erase Resume command is issued the program suspend status bit returns Low.

5.7 Block protection status bit (SR1)

The block protection status bit identifies if a program or block erase operation has tried to modify the contents of a locked or locked-down block. When the block protection status bit is High (set to ‘1’), a program or erase operation has been attempted on a locked or locked-down block Once set High, the block protection status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command appears to fail.

5.8 Bank write/multiple word program status bit (SR0)

The bank write status bit indicates whether the addressed bank is programming or erasing. In buffer enhanced factory program mode the multiple word program bit shows if the device is ready to accept a new word to be programmed to the memory array. The bank write status bit should only be considered valid when the Program/Erase Controller status bit SR7 is Low (set to ‘0’). When both the Program/Erase Controller status bit and the bank write status bit are Low (set to ‘0’), the addressed bank is executing a program or erase operation. When the Program/Erase Controller status bit is Low (set to ‘0’) and the bank write status bit is High (set to ‘1’), a program or erase operation is being executed in a bank other than the one being addressed. In buffer enhanced factory program mode if multiple word program status bit is Low (set to ‘0’), the device is ready for the next word. If the multiple word program status bit is High (set to ‘1’) the device is not ready for the next word. For further details on how to use the Status Register, see the Flowcharts and Pseudocodes provided in Appendix C.

Table 10. Status Register bits

1. Logic level '1' is High, '0' is Low.

6 Configuration Register

The Configuration Register configures the type of bus access that the memory performs. Refer to Section 7: Read modes for details on read operations. operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations.

6.1 Read select bit (CR15)

select bit is set to ’0’, read operations are synchronous. On reset or power-up the read select bit is set to ’1’ for asynchronous access.

6.2 X latency bits (CR13-CR11)

Figure 5: X latency and data output configuration example. the device and the frequency used to read the Flash memory in synchronous mode. Table 11. X latency settings

30 MHz 33 ns 3

40 MHz 25 ns 4

54 MHz 19 ns 5

66 MHz 15 ns 5

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Configuration Register

6.3 Wait polarity bit (CR10)

The wait polarity bit is used to set the polarity of the Wait signal used in synchronous burst read mode. During synchronous burst read mode the Wait signal indicates whether the data output are valid or a WAIT state must be inserted. When the wait polarity bit is set to ‘0’ the Wait signal is active Low. When the wait polarity bit is set to ‘1’ the Wait signal is active High.

6.4 Data output configuration bit (CR9)

The data output configuration bit configures the output to remain valid for either one or two clock cycles during synchronous mode. When the data output configuration bit is ’0’ the output data is valid for one clock cycle, and when the data output configuration bit is ’1’ the output data is valid for two clock cycles. The data output configuration bit must be configured using the following condition:

• tK > tKQV + tQVK_CPU where
• tK is the clock period
• tQVK_CPU is the data setup time required by the system CPU
• tKQV is the clock to data valid time. If this condition is not satisfied, the data output configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 5: X latency and data output configuration example.

6.5 Wait configuration bit (CR8)

The wait configuration bit is used to control the timing of the Wait output pin, WAIT, in synchronous burst read mode. When WAIT is asserted, data is not valid and when WAIT is de-asserted, data is valid. When the wait configuration bit is Low (set to ’0’) the Wait output pin is asserted during the WAIT state. When the wait configuration bit is High (set to ’1’), the Wait output pin is asserted one data cycle before the WAIT state.

6.6 Burst type bit (CR7)

The burst type bit determines the sequence of addresses read during synchronous burst reads. The burst type bit is High (set to ’1’), as the memory outputs from sequential addresses only. See Table 13: Burst type definition for the sequence of addresses output from a given starting address in sequential mode.

Configuration Register M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB

6.7 Valid Clock edge bit (CR6)

The valid Clock edge bit, CR6, configures the active edge of the Clock, K, during synchronous read operations. When the valid Clock edge bit is Low (set to ’0’) the falling edge of the Clock is the active edge. When the valid Clock edge bit is High (set to ’1’) the rising edge of the Clock is the active edge.

6.8 Wrap burst bit (CR3)

The wrap burst bit, CR3, selects between wrap and no wrap. Synchronous burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). When the Wrap Burst bit is Low (set to ‘0’) the burst read wraps. When it is High (set to ‘1’) the burst read does not wrap.

6.9 Burst length bits (CR2-CR0)

The burst length bits sets the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is shifted by 1, 2 or 3 positions from the four-word boundary, WAIT is asserted for 1, 2 or 3 clock cycles, respectively. When the burst sequence crosses the first 16-word boundary this indicates that the device needs an internal delay to read the successive words in the array. WAITis asserted only once during a continuous burst access. See also Table 13: Burst type definition. CR14, CR5 and CR4 are reserved for future use.

Table 12. Configuration Register

0 Synchronous read

1 Asynchronous Read (default at power-on)

1. The combination X latency=2, data held for two cloc k cycles and Wait active one data cycle before the

WAIT state is not supported.

0 WAIT is active Low

1 WAIT is active High (default)

0 Data held for one clock cycle

1 Data held for two clock cycles (default)

0 WAIT is active during WAIT state

1 WAIT is active one data cycle before WAIT

1 Sequential (default)

0 Falling Clock edge

1 Rising Clock edge (default)

1 No wrap (default)

111 Continuous (default)

Table 13. Burst type definition

Table 13. Burst type definition (continued)

Figure 5. X latency and data output configuration example

1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.
2. The settings shown are X latency = 4, data output held for one clock cycle.

Figure 6. Wait configuration example

1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.

Read modes M58LR128KT, M58LR1 28KB, M58LR256KT, M58LR256KB

7 Read modes

Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchronous If the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the Configuration Register. (see Section 6: Configuration Register for details). All banks support both asynchronous and synchronous read operations.

7.1 Asynchronous read mode

In asynchronous read operations the clock signal is ‘don’t care’. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, common Flash interface or electronic signature depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for asynchronous operations. Asynchronous read operations can be performed in two different ways, Asynchronous random access read and asynchronous page read. Only asynchronous page read takes full advantage of the internal page storage so different timings are applied. In asynchronous read mode a page of data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by address inputs A0 and A1. The first read operation within the page has a longer access time (t AVQV, random access time), subsequent reads within the same page have much shorter access times (tAVQV1, page access time). If the page changes then the normal, longer timings apply again. The device features an automatic standby mode. During asynchronous read operations, after a bus inactivity of 150 ns, the device automatically switches to automatic standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In asynchronous read mode, the WAIT signal is always deasserted. See Table 24: Asynchronous read AC characteristics, Figure 9: Asynchronous random access read AC waveforms and Figure 10: Asynchronous page read AC waveforms for details.

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Read modes

7.2 Synchronous burst read mode

In synchronous burst read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous burst read mode can only be used to read the memory array. For other read operations, such as read Status Register, read CFI , and read electronic signature, single synchronous read or asynchronous random access read must be used. In synchronous burst read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence starts at the first clock edge (rising or falling depending on valid Clock edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration Register. The number of words to be output during a synchronous burst read operation can be configured as 4 words, 8 words, 16 words or continuous (burst length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (data output configuration bit CR9). The order of the data output can be modified through the wrap burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). The WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay depends on the starting address of the burst sequence and on the burst configuration. WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 word burst. It is only de-asserted when output data are valid. In continuous burst read mode a WAIT state occurs when crossing the first 16 word boundary. If the starting address is aligned to the burst length (4, 8 or 16 words) the wrapped configuration has no impact on the output sequence. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 25: Synchronous read AC characteristics and Figure 11: Synchronous burst read AC waveforms for details.

Read modes M58LR128KT, M58LR1 28KB, M58LR256KT, M58LR256KB

7.2.1 Synchronous burst read suspend

A synchronous burst read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) or after the device has output data. When the synchronous burst read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A synchronous burst read operation is suspended when Chip Enable, E , is Low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The Clock signal is then halted at V IH or at VIL, and Output Enable, G, goes High. When Output Enable, G, becomes Low again and the Clock signal restarts, the synchronous burst read operation is resumed exactly where it stopped. WAIT reverts to high-impedance when Chip Enable, E, or Output Enable, G, goes High. See Table 25: Synchronous read AC characteristics and Figure 13: Synchronous burst read suspend AC waveforms for details.

7.3 Single synchronous read mode

Single synchronous read operations are similar to synchronous burst read operations except that the memory outputs the same data to the end of the operation. Synchronous single reads are used to read the electronic signature, Status Register, CFI, block protection status, Configuration Register Status or the Protection Register. When the addressed bank is in read CFI, read Status Register or read electronic signature mode, the WAIT signal is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 word burst. It is only de-asserted when output data are valid. See Table 25: Synchronous read AC characteristics and Figure 12: Single synchronous read AC waveforms for details.

8 Dual operations and multiple bank architecture

from one bank while another bank is being programmed or erased. to be in program or erase mode). erase operation can be suspended. programming, and other banks in read mode. program or erase operations. Tables 14 and 15 show the dual operations possible in other banks and in the same bank. Table 14. Dual operations allowed in other banks

Table 15. Dual operations allowed in same bank

1. The Read Array command is accepted but the data output is not guaranteed until the program or erase has
2. Not allowed in the block that is being erased or in the word that is being programmed.

Table 16. Dual operation limitations

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Block locking

9 Block locking

The M58LRxxxKT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection.

• Lock/unlock - this first level allows software only control of block locking.
• Lock-down - this second level requires hardware interaction before locking can be changed.
• VPP ≤ VPPLK - the third level offers complete hardware protection against program and erase on all blocks. The protection status of each block can be set to locked, unlocked, and locked-down. Table 17, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 24 shows a flowchart for the locking operations.

9.1 Reading block lock status

The lock status of every block can be read in read electronic signature mode of the device. To enter this mode issue the Read Electronic Signature command. Subsequent reads at the address specified in Table 8 output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the block lock/unlock status and is set by the Lock command and cleared by the Unlock command. DQ0 is automatically set when entering lock-down. DQ1 indicates the lock-down status and is set by the Lock- Down command. DQ1 cannot be cleared by software, except a hardware reset or power- down. The following sections explain the operation of the locking system.

9.2 Locked state

The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any program or erase operations attempted on a locked block will return an error in the Status Register. The status of a locked block can be changed to unlocked or locked-down using the appropriate software commands. An unlocked block can be locked by issuing the Lock command.

9.3 Unlocked state

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command.

Block locking M58LR128KT, M58LR1 28KB, M58LR256KT, M58LR256KB

9.4 Lock-down state

Blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by issuing the Lock-Down command. Locked-down blocks revert to the locked state when the device is reset or powered-down. The lock-down function is dependent on the Write Protect, WP , input pin. When WP=0 (VIL), the blocks in the lock-down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (VIH) the lock-down function is disabled (1,1,x) and locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. When the lock-down function is disabled (WP =1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. When WP=0 blocks that were previously locked-down return to the lock- down state (0,1,x) regardless of any changes that were made while WP=1. Device reset or power-down resets all blocks, including those in lock-down, to the locked state.

9.5 Locking operations during erase suspend

Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status is changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked down during an erase suspend of the same block, the locking status bits is changed immediately, but when the erase is resumed, the erase operation completes. Locking operations cannot be performed during a program suspend.

Table 17. Lock status

1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for

a locked block) as read in the Read Electronic Signature command with DQ1 = VIH and DQ0 = VIL.

1. All blocks are locked at power-up, so the de fault configuration is 001 or 101 according to WP status.
2. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

10 Program and erase times and endurance cycles

Table 18. Program/erase times and endurance cycles (1) (2)

1. Values are liable to change with t he external system-level overhead (command sequence and Status Register polling
2. Excludes the time needed to execute the command sequence.
3. This is an average value on the entire device.

Table 18. Program/erase times and endurance cycles (1) (2) (continued)

11 Maximum ratings

and other relevant quality documents. Table 19. Absolute maximum ratings

12 DC and AC parameters

Figure 7. AC measurement I/O waveform Table 20. Operating and AC measurement conditions

Figure 8. AC measurement load circuit Table 21. Capacitance (1)

1. Sampled only, not 100% tested.

Table 22. DC characteristics - currents

128 Mbit

256 Mbit 70 110

1. Sampled only, not 100% tested.
2. V DD dual operation current is the sum of read and program or erase currents.

Table 23. DC characteristics - voltages

Figure 9. Asynchronous random access read AC waveforms Notes: 1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.

1. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2. Write Enable, W, is High, WAIT is active Low.

Figure 10. Asynchronous page read AC waveforms Notes: 1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.

Table 24. Asynchronous read AC characteristics

1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.

Figure 11. Synchronous burst read AC waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.

1. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge.
3. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.
4. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.

Figure 12. Single synchronous read AC waveforms

1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.
2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock

signal, K, can be configured as the active edge. Here, the active edge is the rising one.

1. The WAIT signal is configured to be active dur ing wait state. WAIT signal is active Low.

Figure 13. Synchronous burst read suspend AC waveforms Notes 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. The CLOCK signal can be held high or low
3. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge.

Here, the active edge is the rising one.

1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.

Figure 14. Clock input AC waveform Table 25. Synchronous read AC characteristics (1) (2)

1. Sampled only, not 100% tested.
2. For other timings please refer to Table 24: Asynchronous read AC characteristics.

Figure 15. Write AC waveforms, Write Enable controlled Note: Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.

Table 26. Write AC characteristics, Write Enable controlled (1)

1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept low.
3. t WHEL and tWHLLhave this value when reading in the targeted bank or when reading following a Set

been issued, tWHEL and tWHLL is 0 ns.

Figure 16. Write AC waveforms, Chip Enable controlled Note: Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B.

Table 27. Write AC characteristics, Chip Enable controlled (1)

1. Sampled only, not 100% tested.
2. t WHEL has this value when reading in the targeted bank or when reading following a Set Configuration

Figure 17. Reset and power-up AC waveforms Table 28. Reset and power-up AC characteristics

1. The device Reset is possible but not guaranteed if t PLPH < 50 ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP

to allow proper CPU initialization during power-up or Reset.

13 Part numbering

Devices are shipped from the factory with the memory content bits erased to ’1’. of this device, please contact the Numonyx sales office nearest to you. Table 29. Ordering information scheme

1. The M58LRxxxKT/B are only availabl e as part of a multichip package.

Block address tables M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Appendix A Block address tables The following set of equations can be used to calculate a complete set of block addresses for the M58LRxxxKT/B using the information contained in Tables 33 to 41. To calculate the block base address from the block number: First it is necessary to calculate the bank number and the block number offset. This can be achieved using the following formulas: Bank_Number = (Block_Number − 3) / 8 Block_Number_Offset = Block_Number − 3 − (Bank_Number x 8), If Bank_Number= 0, the block base address can be directly read from Tables 33 and 39 (parameter bank block addresses) in the address range column, in the row that corresponds to the given block number. Otherwise: Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset To calculate the bank number and the block number from the block base address: If the address is in the range of the parameter bank, the Bank Number is 0 and the Block Number can be directly read from Tables 33 and 39 (parameter bank Block Addresses), in the Block Number column, in the row that corresponds to the address given. Otherwise, the Block Number can be calculated using the formulas below: For the top configuration (M58LR256KT and M58LR128KT): Block_Number = ((NOT address) / 2 16) + 3 For the bottom configuration (M58LR256KB and M58LR128KB): Block_Number = (address / 216) + 3 For both configurations the Bank Number and the Block Number Offset can be calculated using the following formulas: Bank_Number = (Block_Number − 3) / 8 Block_Number_Offset = Block_Number − 3 − (Bank_Number x 8)

Table 30. M58LR128KT - Parameter bank block addresses Table 31. M58LR128KT - main bank base addresses

1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;

Bank Region 2 contains the banks that are made up of the parameter and main blocks (parameter bank).

Table 32. M58LR128KT - block addresses in main banks Table 33. M58LR256KT - parameter bank block addresses

Table 34. M58LR256KT - main bank base addresses

1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only;

Bank Region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). Table 35. M58LR256KT - block addresses in main banks

Table 36. M58LR128KB - parameter bank block addresses Table 37. M58LR128KB - main bank base addresses

1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only;

Bank Region 1 contains the banks that are made up of the parameter and main blocks (parameter bank).

Table 38. M58LR128KB - block addresses in main banks Table 39. M58LR256KB - parameter bank block addresses

1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only;

Bank Region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). Table 40. M58LR256KB - main bank base addresses Table 41. M58LR256KB - block addresses in main banks

software to upgrade itself when necessary. lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0. been written by Numonyx. Issue a Read Array command to return to read mode.

1. The Flash memory display the CFI data structure w hen CFI Query command is issued. In this table are

Table 42. Query structure overview

Table 43. CFI query identification string

Table 44. CFI query system interface information

Table 45. Device geometry definition

Table 46. Primary algorithm-specific extended query table (P+5)h contains less significant byte.

Table 47. Protection Register information (P+E)h = 118h 0002h Number of protection register fields in JEDEC ID space. Table 48. Burst read information determine page-mode data output width. reaches the end of the device’s burstable address space. determine the burst data output width. Synchronous mode read capability configuration 4 Cont.

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Common Flash interface Table 49. Bank and erase block region information (1) (2)

1. The variable P is a pointer that is defined at CFI offset 015h.
2. Bank Regions. There ar e two Bank Regions, see Table 31, Table 34, Table 37 and Table 40.

(P+23)h = 12Dh 02h (P+23)h = 12Dh 02h Number of Bank Regions within the device Table 50. Bank and erase block region 1 information Offset(1) Data Offset (1) Data (P+24)h = 12Eh 0Fh (P+24)h = 12Eh 01h Number of identical banks within Bank Region 1(P+25)h = 12Fh 00h (P+25)h = 12Fh 00h (P+26)h = 130h 11h (P+26)h = 130h 11h Number of program or erase operations allowed in Bank Region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+27)h = 131h 00h (P+27)h = 131h 00h Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+28)h = 132h 00h (P+28)h = 132h 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+29)h = 133h 01h (P+29)h = 133h 02h Types of erase block regions in Bank Region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region(2) 0Fh(4) (P+2A)h = 134h 03h Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+2B)h = 135h 00h (P+2B)h = 135h 00h (P+2C)h = 136h 00h (P+2C)h = 136h 80h (P+2D)h = 137h 02h (P+2D)h = 137h 00h (P+2E)h = 138h 64h (P+2E)h = 138h 64h Bank Region 1 (Erase Block Type 1) Minimum block erase cycles × 1000(P+2F)h = 139h 00h (P+2F)h = 139h 00h

Common Flash interface M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB (P+30)h = 13Ah 01h (P+30)h = 13Ah 01h Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+31)h = 13Bh 03h (P+31)h = 13Bh 03h Bank Region 1 (Erase Block Type 1): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted (5) Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved 0Eh(4) Bank Region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+33)h = 13Dh 00h (P+34)h = 13Eh 00h (P+35)h = 13Fh 02h (P+36)h = 140h 64h Bank Region 1 (Erase Block Type 2) Minimum block erase cycles × 1000(P+37)h = 141h 00h (P+38)h = 142h 01h Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+39)h = 143h 03h Bank Region 1 (Erase Block Type 2): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved 1. The variable P is a pointer that is defined at CFI offset 015h. 2. Bank Regions. There ar e two Bank Regions, see Table 31, Table 34, Table 37 and Table 40. 3. Applies to M58LR128KT/B only. 4. Applies to M58LR256KT/B only. 5. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. Table 50. Bank and erase block region 1 information (continued) Offset(1) Data Offset (1) Data

M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Common Flash interface Table 51. Bank and erase block region 2 information Offset(1) Data Offset (1) Data (P+32)h = 13Ch 01h (P+3A)h = 144h 0Fh Number of identical banks within Bank Region 2(P+33)h = 13Dh 00h (P+3B)h = 145h 00h (P+34)h = 13Eh 11h (P+3C)h = 146h 11h Number of program or erase operations allowed in Bank Region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+35)h = 13Fh 00h (P+3D)h = 147h 00h Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+36)h = 140h 00h (P+3E)h = 148h 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+37)h = 141h 02h (P+3F)h = 149h 01h Types of erase block regions in Bank Region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2) 0Eh(4) (P+40)h = 14Ah 07h(3) 0Fh(4) Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+39)h = 143h 00h (P+41)h = 14Bh 00h (P+3A)h = 144h 00h (P+42)h = 14Ch 00h (P+3B)h = 145h 02h (P+43)h = 14Dh 02h (P+3C)h = 146h 64h (P+44)h = 14Eh 64h Bank Region 2 (Erase Block Type 1) Minimum block erase cycles × 1000(P+3D)h = 147h 00h (P+45)h = 14Fh 00h (P+3E)h = 148h 01h (P+46)h = 150h 01h Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved

Common Flash interface M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB (P+3F)h = 149h 03h (P+47)h = 151h 03h Bank Region 2 (Erase Block Type 1):Page mode and Synchronous mode capabilities (defined in Table 48) Bit 0: Page-mode reads permitted(5) Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+40)h = 14Ah 03h Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region (P+41)h = 14Bh 00h (P+42)h = 14Ch 80h (P+43)h = 14Dh 00h (P+44)h = 14Eh 64h Bank Region 2 (Erase Block Type 2) Minimum block erase cycles × 1000(P+45)h = 14Fh 00h (P+46)h = 150h 01h Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved (P+47)h = 151h 03h Bank Region 2 (Erase Block Type 2): Page mode and Synchronous mode capabilities (defined in Table 48) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+48)h = 152h (P+48)h = 152h Feature Space definitions (P+49)h = 153h (P+43)h = 153h Reserved 1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank Regions. There ar e two bank regions, see Table 31, Table 34, Table 37 and Table 40. 3. Applies to M58LR128KT/B only. 4. Applies to M58LR256KT/B only. 5. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. Table 51. Bank and erase block region 2 information (continued) Offset(1) Data Offset (1) Data

Figure 18. Program flowchart and pseudocode

1. Status check of SR1 (Protected Block), SR3 (V PP Invalid) and SR4 (Program Error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cl eared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 19. Blank check flowchart and pseudocode

1. Any address within the bank can equally be used.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

Figure 20. Buffer program flowchart and pseudocode

1. n + 1 is the number of data being programmed.
2. Next Program data is an element belonging to buffer_Progr am[].data; Next Program address is an element belonging to
3. Routine for Error Check by reading SR3, SR4 and SR1.

Figure 21. Program suspend and resume flowchart and pseudocode

1. The Read Status Register command (Write 70h) can be issu ed just before or just after the Program Resume command.

Figure 22. Block erase flowchart and pseudocode

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.

Figure 23. Erase suspend and resume flowchart and pseudocode

1. The Read Status Register command (Write 70h) can be is sued just before or just after the Erase Resume command.

Figure 24. Locking operations flowchart and pseudocode

1. Any address within the bank can equally be used.

Figure 25. Protection Register program flowchart and pseudocode

1. Status check of SR1 (Protected Block), SR3 (V PP Invalid) and SR4 (Program Error) can be made after each program

operation or after a sequence.

1. If an error is found, the Status Register must be cl eared before further Program/Erase Controller operations.
2. Any address within the bank can equally be used.

Figure 26. Buffer enhanced factory program flowchart and pseudocode

Table 52. Command interface states - modify table, next state (1)

Table 52. Command interface states - modify table, next state (1) (continued)

1. CI = Command Interface, CR = Configuration register, BEF P = Buffer Enhanced Factory program, P/E C = Program/Erase

controller, IS = Illegal State, BP = Buffer Program, ES = Erase Suspend.

1. At power-up, all banks are in read array mode. Issuing a Read Array command to a busy bank, results in undetermined
2. The two cycle command should be issued to the same bank address.
3. If the P/E C is active, both cycles are ignored.
4. The Clear Status Register command clears the SR erro r bits except when the P/E C. is busy or suspended.
5. BEFP is allowed only when Status Register bi t SR0 is reset to '0'. BEFP is busy if Block Address is first BEFP Address. Any

other commands are treated as data.

Table 53. Command interface states - modify table, next output state (1) (2)

1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command

depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank output state.

1. CI = Command Interface, CR = Configuration Register , BEFP = Buffer Enhanced Factory Program, P/E. C. =
2. At Power-Up, all banks are in read array mode. Issuing a Read Array command to a busy bank, results in undetermined
3. The two cycle command should be issued to the same bank address.
4. If the P/EC is active, both cycles are ignored.

Table 53. Command interface states - modify table, next output state (1) (2) (continued)

Table 54. Command interface states - lock table, next state (1)

1. CI = Command Interface, CR = Configuration register, BEF P = Buffer Enhanced Factory program, P/E C = Program/Erase
2. If the P/E C is active, both cycle are ignored.
3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
4. Illegal commands are those not defined in the command set.
5. N/A: not available. In this case the state remains unchanged.
6. If N=0 go to Buffer Program Confirm. Else (not =0) go to Buffer Program Load 2 (data load)
7. If N=0 go to Buffer Program Confirm in Erase suspend. Else (not =0) go to Buffer Program Load 2 in Erase suspend.
8. BEFP is allowed only when Status Register bit SR0 is set to '0'. BEFP is busy if Block Address is first BEFP Address. Any

other commands are treated as data. Table 54. Command interface states - lock table, next state (1) (continued)

Table 55. Command interface states - lock table, next output state (1) (2)

1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command

depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank's output state.

1. CI = Command Interface, CR = Configuration Register , BEFP = Buffer Enhanced Factory Program, P/E. C. =
2. If the P/EC is active, both cycles are ignored.
3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
4. Illegal commands are those not defined in the command set.

Table 55. Command interface states - lock table, next output state (continued) (1) (2)

Table 56. Document revision history 23-Mar-2007 1 Initial release. respectively, to 20 and 25 for both. value from 3.8 to VDDQ + 0.6 V. – Added the 256 Mbit values for IDD2, IDD3, and IDD7. another bank” values to 50 and 67, respectively. tVDHPH value from 250 to 300. 27-Mar-2008 3 Applied Numonyx branding.