M58LR016C100ZC6T

M58MR016C STMICROELECTRONICS | Alldatasheet

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Technical content

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

16 Mbit (1Mb x16, Mux I/O, Dual Bank, Burst)

Figure 1. Logic Diagram

M58MR016C, M58MR016D Figure 2. TFBGA Connections (Top view through package)

DESCRIPTION

The M58MR016 is a 16 Mbit non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by- Word basis using a 1.7V to 2.0V VDD supply for the circuitry. For Program and Erase operations the necessary high voltages are generated internally. The device supports synchronous burst read and asynchronous read from all the blocks of the mem- ory array; at power-up the device is configured for page mode read. In synchronous burst mode, a new data is output at each clock cycle for frequen- cies up to 40MHz. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against pro- gramming and erase at Power-up. Blocks can be unprotected to make changes in the application and then re-protected. A parameter block "Security block" can be perma- nently protected against programming and erasing in order to increase the data security. An optional 12V V PP power supply is provided to speed up the program phase at costumer production. An inter- nal command interface (C.I.) decodes the instruc- tions to access/modify the memory content. The program/erase controller (P/E.C.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. Two status registers indicate the state of each bank. Instructions for Read Array, Read Electronic Sig- nature, Read Status Register, Clear Status Regis- ter, Write Read Configuration Register, Program, Block Erase, Bank Erase, Program Suspend, Pro- gram Resume, Erase Suspend, Erase Resume, Block Protect, Block Unprotect, Block Locking, Protection Program, CFI Query, are written to the memory through a Command Interface (C.I.) using standard micro-processor write timings. The memory is offered in TFBGA48, 0.5 mm ball pitch packages and it is supplied with all the bits erased (set to ’1’).

Table 1. Signal Names The M58MR016 is organized as 1Mb by 16 bits. address lines A16-A19 are the MSB addresses. W inputs provide memory control. microprocessor during burst read. perform burst reads that cross bank boundaries. Table 2. Absolute Maximum Ratings

1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

Table 3. Bank Size and Sectorization Figure 3. Memory Map

512 Kbit or

32 KWord

64 Kbit or

4 KWord

M58MR016C, M58MR016D SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs or Data Input/Output (ADQ0- ADQ15). When Chip Enable E is at VIL and Out- put Enable G is at VIH the multiplexed address/ data bus is used to input addresses for the memo- ry array, data to be programmed in the memory ar- ray or commands to be written to the C.I. The address inputs for the memory array are latched on the rising edge of Latch Enable L . The address latch is transparent when L is at VIL. In synchro- nous operations the address is also latched on the first rising/falling edge of K (depending on clock configuration) when L is low. Both input data and commands are latched on the rising edge of Write Enable W . When Chip Enable E and Output En- able G are at VIL the address/data bus outputs data from the Memory Array, the Electronic Signa- ture Manufacturer or Device codes, the Block Pro- tection status the Read Configuration Register status, the protection register or the Status Regis- ter. The address/data bus is high impedance when the chip is deselected, Output Enable G is at VIH, or RP is at VIL. Address Inputs (A16-A19).The five MSB ad- dresses of the memory array are latched on the rising edge of Latch Enable L . In synchronous op- eration these inputs are also latched on the first rising/falling edge of K (depending on clock config- uration) when L is low. Chip Enable (E).The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memo- ry array, while W remains at VIL. Output Enable (G).The Output Enable gates the outputs through the data buffers during a read op- eration. When G is at VIH the outputs are High im- pedance. Write Enable (W).This input controls writing to the Command Register and Data latches. Data are latched on the rising edge of W Write Protect (WP).This input gives an addition- al hardware protection level against program or erase when pulled at VIL, as described in the Block Lock instruction description. Reset/Power-down Input (RP).The RP input provides hardware reset of the memory, and/or Power-down functions, depending on the Read Configuration Register status. Reset/Power-down of the memory is achieved by pulling RP to VIL for at least tPLPH . When the reset pulse is given, the memory will recover from Power-down (when en- abled) in a minimum of t PHEL , tPHLL or tPHWL (see Table 31 and Figure 15) after the rising edge of RP . Exit from Reset/Power-down changes the contents of the Read Configuration Register bits 14 and 15, setting the memory in asynchronous page mode read and power save function dis- abled. All blocks are protected and unlocked after a Reset/Power-down. Latch Enable (L ).L latches the address bits ADQ0-ADQ15 and A16-A19 on its rising edge. The address latch is transparent when L is at VIL and it is inhibited when L is at VIH. Clock (K).The clock input synchronizes the memory to the micro controller during burst mode read operation; the address is latched on a K edge (rising or falling, according to the configuration set- tings) when L is at VIL. K is don't care during asyn- chronous page mode read and in write operations. Wait (WAIT).WAIT is an output signal used dur- ing burst mode read, indicating whether the data on the output bus are valid or a wait state must be inserted. This output is high impedance when E or G are high or RP is at VIL, and can be configured to be active during the wait cycle or one clock cy- cle in advance. Bus Invert (BINV).BINV is an input/output signal used to reduce the amount of power needed to switch the external address/data bus. The power saving is achieved by inverting the data output on ADQ0-ADQ15 every time this gives an advantage in terms of number of toggling bits. In burst mode read, each new data output from the memory is compared with the previous data. If the number of transitions required on the data bus is in excess of 8, the data is inverted and the BINV signal will be driven by the memory at V OH to inform the receiv- ing system that data must be inverted before any further processing. By doing so, the actual transi- tions on the data bus will be less than 8. In a similar way, when a command is given, BINV may be driven by the system at VIH to inform the memory that the data input must be inverted. Like the other input/output pins, BINV is high im- pedance when the chip is deselected, output en- able G is at VIH or RP is at VIL; when used as an input, BINV must follow the same set-up and hold timings of the data inputs. VDD and VDDQ Supply Voltage (1.7V to 2.0V). VDD is the main power supply for all operations (Read, Program and Erase). VDDQ is the supply voltage for Input and Output.

M58MR016C, M58MR016D VPP Program Supply Voltage (12V).VPP is both a control input and a power supply pin. The two functions are selected by the voltage range ap- plied to the pin; if V PP is kept in a low voltage range (0 to 2V) VPP is seen as a control input, and the current absorption is limited to 5µA (0.2µA typical). In this case with V PP = VIL we obtain an absolute protection against program or erase; with VPP = VPP1 these functions are enabled (see Table 26). VPP value is only sampled during program or erase write cycles; a change in its value after the operation has been started does not have any ef- fect and program or erase are carried on regularly. If V PP is used in the 11.4V to 12.6V range (VPPH ) then the pin acts as a power supply (see Table 26). This supply voltage must remain stable as long as program or erase are running. In read mode the current sunk is less then 0.5mA, while during program and erase operations the current may increase up to 10mA. V SS Ground. VSS is the reference for all the volt- age measurements.

Table 4. User Bus Operations (1) Table 5. Read Electronic Signature (AS and Read CFI instructions) (1) Note: 1. Addresses are latched on the rising edge of L input.

1. EA means Electronic Signature Address (see Read Electronic Signature)
2. Value during address latch.

Table 6. Read Block Protection (AS and Read CFI instructions) (1) Note: 1. Addresses are latched on the rising edge of L input.

1. A locked block can be unprotected only with WP at VIH.
2. Value during address latch.
3. BA means Block Address. First cycle command address should indicate the bank of the block address.

down and Block Locking. See Table 4. ter status and the Protection Register. data is internally read and stored in a page buffer. by ADQ0 and ADQ1 address inputs. single synchronous read (see Figure 4).

Table 7. Read Protection Register (RSIG and RCFI Instruction) (1) Note: 1. Addresses are latched on the rising edge of L input. Table 8. Dual Bank Operations (1, 2, 3) Note: 1. For detailed description of command see Table 33 and 34.

1. There is a status register for each bank; status register indicates bank state, not P/E.C. status.
2. Command must be written to an address within the block targeted by that command.

Figure 4. Single Synchronous Read Sequence (RSIG, RCFI, RSR instructions) at VIL in order to read the output of the memory. exiting power down or after power up. and clock is ignored during write. one of the read modes (see Table 8). the block targeted by that command.

standby and the outputs are in high impedance. is reset or powered-down (see Protect instruction). Table 9. Identifier Codes Note: 1. DRC means Die Revision Code. CR means Read Configuration Register. LPR means Lock Protection Register. PR means Unique Device Number and User Programmable OTP.

Table 10. Commands reset the device to Read Array. G must be toggled to update the latched data. output the protection Status of Blocks of bank B. acteristics of M58MR016C and M58MR016D.

Table 11. Instructions

1. BKA = Address within the bank, BA = Block Address, EA = Electronic Signature Address, CFIA = Common Flash Interface Address;
2. WA1, WA2, WA3 and WA4 must be consecutive address differing only for address bits A1-A0.
3. Read cycle after CLSR instruction will output the memory array.

1 Write BKA B0h

1 Write BKA D0h

2 Write PA C0h Write PA PD

2 Write LPA C0h Write LPA LPD

2 Write RCA 60h Write RCA 03h

M58MR016C, M58MR016D CFI Query (RCFI) The CFI Query Mode is associated to bank A. The address of the first write cycle must be within the bank A. The status of the other bank is not affected by the command (see Table 8). Writing 98h the de- vice enters the Common Flash Interface Query mode. Next read operations in the bank A will read the CFI data. Write a read instruction to return to Read mode (refer to the Common Flash Interface section). Clear Status Register (CLSR) The Clear Status Register uses a single write op- eration, which resets bits b1, b3, b4 e b5 of the sta- tus register. The Clear Status Register is executed writing the command 50h independently of the ap- plied V PP voltage. After executing this command the device returns to read array mode. The Clear Status Register command clears only the status register of the addressed bank. Block Erase (EE) Block erasure sets all the bits within the selected block to '1'. One block at a time can be erased. It is not necessary to pre-program the block as the P/E.C. will do it automatically before erasing. This instruction use two writes cycles. The first com- mand written is the Block Erase Set up command 20h. The second command is the Erase Confirm command D0h. An address within the block to be erased should be given to the memory during the two cycles command. If the second command giv- en is not an erase confirm, the status register bits b4 and b5 are set and the instruction aborts. After writing the command, the device outputs sta- tus register data when any address within the bank is read. At the end of the operation the bank will re- main in read status register until a read array com- mand is written. Status Register bit b7 is '0' while the erasure is in progress and '1' when it has completed. After com- pletion the Status Register bit b5 returns '1' if there has been an Erase Failure. Status register bit b1 returns '1' if the user is attempting to erase a pro- tected block. Status Register bit b3 returns a '1' if V PP is below VPPLK . Erase aborts if RP turns to VIL. As data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated (see Table 12). A Clear Status Register instruction must be issued to reset b1, b3, b4 and b5 of the Status Register. During the execution of the erase by the P/E.C., the bank with the block in erase accepts only the RSR (Read Status Regis- ter) and PES (Program/Erase Suspend) instruc- tions. See figure 19 for Erase Flowchart and Pseudo Code. Bank Erase (BE) Bank erase sets all the bits within the selected bank to ’1’. It is not necessary to pre-program the block as the P/E.C. will do it automatically before erasing. This instruction uses two writes cycles. The first command written is the Bank Erase set-up com- mand 80h. The second command is the Erase Confirm command D0h. An address within the bank to be erased should be given to the memory during the two cycles command. See the Block Erase command section for status register bit de- tails. Program (PG) The Program instruction programs the array on a word-by-word basis. The first command must be given to the target block and only one partition can be programmed at a time; the other partition must be in one of the read modes or in the erase sus- pended mode (see Table 8). This instruction uses two write cycles. The first command written is the Program Set-up command 40h (or 10h). A second write operation latches the Address and the Data to be written and starts the P/E.C. Read operations in the targeted bank output the Status Register content after the programming has started. The Status Register bit b7 returns '0' while the pro- gramming is in progress and '1' when it has com- pleted. After completion the Status register bit b4 returns '1' if there has been a Program Failure (see Table 12). Status register bit b1 returns '1' if the user is attempting to program a protected block. Status Register bit b3 returns a '1' if V PP is below VPPLK . Any attempt to write a ’1’ to an already pro- grammed bit will result in a program fail (status register bit b4 set) if VPP = VPPH and will be ig- nored if VPP = VPP1 . Programming aborts if RP goes to VIL. As data in- tegrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and repro- grammed. A Clear Status Register instruction

Table 12. Status Register Bits Note:Logic level ’1’ is VIH and ’0’ is VIL.

1 Suspended On an Erase Suspend instruction P/ECS and

1 Program Error

1 Suspended On a program Suspend instruction P/ECS and

0 No operation to

0 Reserved

The two words must differ only for the address A0. if VPP is below VPPH but result could be uncertain. written and starts the P/E.C. (see Table 11). register bit b4 set). (See Table 12).

Table 13. Protection States (1) Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status.

1. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect in and by
2. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed
3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

100 Y es 101 100 111 000

101 No 101 100 111 001

110 Y es 111 110 111 011

111 No 111 110 111 011

000 Y es 001 000 011 100

001 No 001 000 011 101

011 No 011 011 011 111 or 110

Figure 5. Security Block Memory Map

M58MR016C, M58MR016D Programming aborts if RP goes to VIL. As data in- tegrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. A Clear Status Regis- ter instruction must be issued to reset b5, b4, b3 and b1 of the Status Register. During the execu- tion of the program by the P/E.C., the bank in pro- gramming accepts only the RSR (Read Status Register) instruction. See Figure 17 for Double Word Program Flowchart and Pseudo code. Tetra Word Program (TPG) This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel. The first command must be given to the target block and only one partition can be pro- grammed at a time; the other partition must be in one of the read modes or in the erase suspended mode (see Table 8). The four words must differ only for the addresses A0 and A1. Programming should not be attempted when V PP is not at VPPH . The operation can also be executed if VPP is below VPPH but result could be uncertain. These instruction uses five write cy- cles. The first command written is the Tetra Word Program Set-Up command 55h. A second write operation latches the Address and the Data of the first word to be written, the third write operation latches the Address and the Data of the second word to be written, the fourth write operation latch- es the Address and the Data of the third word to be written, the fifth write operation latches the Ad- dress and the Data of the fourth word to be written and starts the P/E.C. (see Table 11). Read operations in the targeted bank output the Status Register content after the programming has started. The Status Register bit b7 returns '0' while the programming is in progress and '1' when it has completed. After completion the Status reg- ister bit b4 returns '1' if there has been a Program Failure. Status register bit b1 returns '1' if the user is attempting to program a protected block. Status Register bit b3 returns a '1' if V PP is below VPPLK . Any attempt to write a ’1’ to an already pro- grammed bit will result in a program fail (status register bit b4 set). (See Table 12). Programming aborts if RP goes to VIL. As data in- tegrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. A Clear Status Regis- ter instruction must be issued to reset b5, b4, b3 and b1 of the Status Register. During the execu- tion of the program by the P/E.C., the bank in pro- gramming accepts only the RSR (Read Status Register) instruction. See Figure 17 for Tetra Word Program Flowchart and Pseudo code. Erase Suspend/Resume (PES/PER) The Erase Suspend freezes, after a certain laten- cy period (within 25us), the erase operation and al- lows read in another block within the targeted bank or program in the other block. This instruction uses one write cycle B0h and the address should be within the bank with the block in erase (see Table 11). The device continues to output status register data after the erase suspend is issued. The status register bit b7 and bit b6 are set to ’1’ then the erase operation has been sus- pended. Bit b6 is set to '0' in case the erase is com- pleted or in progress (see Table 12). The valid commands while erase is suspended are: Program/Erase Resume, Program, Read Memory Array, Read Status Register, Read Elec- tronic Signature, CFI Query, Block Protect, Block Unprotect and Block Lock. The user can protect the Block being erased issuing the Block Protect or Block Lock commands. During a block erase suspend, the device goes into standby mode by taking E to VIH, which reduc- es active current draw. Erase is aborted if RP turns to VIL. If an Erase Suspend instruction was previously ex- ecuted, the erase operation may be resumed by issuing the command D0h using an address within the suspended bank. The status register bit b6 and bit b7 are cleared when erase resumes and read operations output the status register after the erase is resumed. Block erase cannot resume until program operations initiated during block erase suspend have completed. It is also possible to nest suspends as follows: suspend erase in the first partition, start programming in the second or in the same partition, suspend programming and then read from the second or the same partition. The suggested flowchart for erase suspend/re- sume features of the memory is shown from Fig- ure 20. Program Suspend/Resume (PES/PER) Program suspend is accepted only during the Pro- gram instruction execution. When a Program Sus- pend command is written to the C.I., the P/E.C. freezes the Program operation. Program Resume (PER) continues the Program operation. Program Suspend (PES) consists of writing the command B0h and the address should be within the bank with the word in programming (see Table 11). The Status Register bit b2 is set to '1' (within 5µs) when the program has been suspended. Bit b2 is set to '0' in case the program is completed or in progress (see Table 12). The valid commands while program is suspended are: Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature, CFI Query. During program suspend mode, the device goes in standby mode by taking E to VIH. This re-

M58MR016C, M58MR016D duces active current consumption. Program is aborted if RP turns to VIL. If a Program Suspend instruction was previously executed, the Program operation may be resumed by issuing the command D0h using an address within the suspended bank (see Table 11). The status register bit b2 and bit b7 are cleared when program resumes and read operations output the status register after the erase is resumed (see Ta- ble 12). The suggested flowchart for program sus- pend/resume features of the memory is shown from Figure 18. Block Protect (BP) The BP instruction use two write cycles. The first command written is the protection set-up 60h. The second command is block Protect command 01h, written to an address within the block to be protect- ed (see Table 11). If the second command is not recognized by the C.I the bit 4 and bit 5 of the sta- tus register will be set to indicate a wrong se- quence of commands (see Table 12). To read the status register write the RSR command. Block Unprotect (BU) The instruction use two write cycles. The first com- mand written is the protection set-up 60h. The sec- ond command is block Unprotect command D0h, written to an address within the block to be protect- ed (see Table 11). If the second command is not recognized by the C.I the bit 4 and bit 5 of the sta- tus register will be set to indicate a wrong se- quence of commands (see Table 12). To read the status register write the RSR command. Block Lock (BL) The instruction use two write cycles. The first com- mand written is the protection set-up 60h. The sec- ond command is block Lock command 2Fh, written to an address within the block to be protect- ed (see Table 11). If the second command is not recognized by the C.I the bit 4 and bit 5 of the sta- tus register will be set to indicate a wrong se- quence of commands. To read the status register write the RSR command (see Table 12). BLOCK PROTECTION The M58MR016C/M58MR016D provide a flexible protection of all the memory providing the protec- tion, un-protection and locking of any blocks. All blocks are protected at power-up. Each block of the array has two levels of protection against pro- gramming or erasing operation. The first level is set by the Block Protect instruction; a protected block cannot be programmed or erased until a Block Unprotect instruction is given for that block. A second level of protection is set by the Block Lock instruction, and requires the use of the WP pin, according to the following scheme: – when WP is at VIH, the Lock status is overridden and all blocks can be protected or unprotected; – when WP is at VIL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Blocks that are not locked can still change their protection status; – the lock status is cleared for all blocks at power up. The protection and lock status can be monitored for each block using the Read Electronic Signature (RSIG) instruction. Protected blocks will output a '1' on DQ0 and locked blocks will output a '1' in DQ1 (see Table 13). PROTECTION REGISTER PROGRAM (PRP) and LOCK PROTECTION REGISTER PROGRAM (LPRP) The M58MR016C/M58MR016D features a 128-bit protection register and a security Block in order to increase the protection of a system design. The Protection Register is divided in two 64-bit seg- ments. The first segment (81h to 84h) is a unique device number, while the second one (85h to 88h) can be programmed by the user. When shipped the user programmable segment is read at '1'. It can be only programmed at '0'. The user programmable segment can be protect- ed writing the bit 1 of the Protection Lock register (80h). The bit 1 protects also the bit 2 of the Pro- tection Lock Register. The M58MR016C/M58MR016D feature a security Block. The security Block is located at 0FF000- 0FFFFF (M58MR016C) or at 000000-000FFF (M58MR016D) of the device. This block can be permanently protected by the user programming the bit 2 of the Protection Lock Register (see Fig- ure 5). The protection Register and the Protection Lock Register can be read using the RSIG and RCFI in- structions. A subsequent read in the address start- ing from 80h to 88h, the user will retrieve respectively the Protection Lock register, the unique device number segment and the OTP user programmable register segment (see Table 23). WRITE READ CONFIGURATION REGISTER (CR). This instruction uses two Coded Cycles, the first write cycle is the write Read Configuration Regis- ter set-up 60h, the second write cycle is write Read Configuration Register confirm 03h both to Read Configuration Register address (see Table 11). This instruction writes the contents of address bits ADQ15-ADQ0 to bits CR15-CR0 of the Read Con-

M58MR016C, M58MR016D figuration Register (A19-A16 are don't care). At Power-up the Read Configuration Register is set to asynchronous Read mode, Power-down dis- abled and bus invert (power save function) dis- abled. A description of the effects of each configuration bit is given in Table 14. Read mode (CR15). The device supports an asynchronous page mode and a synchronous burst mode. In asynchronous page mode, the de- fault at power-up, data is internally read and stored in a buffer of 4 words selected by ADQ0 and ADQ1 address inputs. In synchronous burst mode, the device latches the starting address and then out- puts a sequence of data that depends on the Read Configuration Register settings (see Figures 10, 11 and 12). Synchronous burst mode is supported in both pa- rameter and main blocks; it is also possible to per- form burst mode read across the banks. Bus Invert configuration (CR14).This register bit is used to enable the BINV pin functionality. BINV functionality depends upon configuration bits CR14 and CR15 (see Table 14 for configura- tion bits definition) as shown in Table 15. As output pin BINV is active only when enabled (CR14 = 1) in Read Array burst mode (CR15 = 0). As input pin BINV is active only when enabled (CR14 = 1). BINV is ignored when ADQ0-ADQ15 lines are used as address inputs (addresses must not be in- verted). X-Latency (CR13-CR11).These configuration bits define the number of clock cycles elapsing from L going low to valid data available in burst mode (see Figure 6). The correspondence be- tween X-Latency settings and the maximum sus- tainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: –( n + 2 ) t K ≥ tACC + tQVK_CPU + tAVK_CPU –t K > tKQV + tQVK_CPU where "n" is the chosen X-Latency configuration code, tK is the clock period, tAVK_CPU is the ad- dress setup time guaranteed by the system CPU, and tQVK_CPU is the data setup time required by the system CPU. Power-down configuration (CR10).The RP pin may be configured to give very low power con- sumption when driven low (power-down state). In power-down the I CC supply current is reduced to a typical figure of ICC2 ; if this function is disabled (default at power-up) the RP pin causes only a re- set of the device and the supply current is the stand-by value. The recovery time after a RP pulse is significantly longer when power-down is en- abled (see Table 31). Wait configuration (CR8).In burst mode WAIT indicates whether the data on the output bus are valid or a wait state must be inserted. The config- uration bit determines if WAIT will be asserted one clock cycle before the wait state or during the wait state (see Figure 7). WAIT is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap configuration is selected. Burst order configuration (CR7) and Burst Wrap configuration (CR3).See Table 16 for burst order and length. Clock configuration (CR6).In burst mode deter- mines if address is latched and data is output on the rising or falling edge of the clock. Burst length (CR2-CR0).In burst mode deter- mines the number of words output by the memory. It is possible to have 4 words, 8 words or a contin- uous burst mode, in which all the words are read sequentially. In continuous burst mode the burst sequence can cross the end of each of the two banks (all banks in read array mode). In continu- ous burst mode or in 4, 8 words no-wrap it may happen that the memory will stop the data output flow for a few clock cycles; this event is signaled by WAIT going low until the output flow is resumed. The initial address determines if the output delay will occur as well as its duration. If the starting ad- dress is aligned to a four words boundary no wait states will be needed. If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence is crossing the first 64 word boundary. WAIT will be asserted only once during a continuous burst access. See also Table 16.

Table 14. Read Configuration Register (AS and Read CFI instructions) (1) Note: 1. The RCR can be read via the RSIG command (90h). Bank A Address + 05h contains the RCR data. See Table 9.

1. All the bits in the RCR are set to default on device power-up or reset.

Table 15. BINV Configuration Bits

– BINV disabled: (CR14 = 0). All blocks are protected and unlocked. plies and can be biased in any order. quired VDD program and erase currents. Figure 6. X-Latency Configuration Sequence

Figure 7. Wait Configuration Sequence

M58MR016C, M58MR016D 22/51Table 16. Burst Order and Length Configuration Mode Starting Address 4 Words 8 Words Continuous Burst Linear Interleaved Linear Interleaved Wrap ... ... 62 62-63-WAIT -WAIT -64-65-66... 63 63-WAIT -WAIT -WAIT -64-65-66... Linear Interleaved Linear Interleaved No-wrap ... ... 62 62-63-WAIT -WAIT -64-65 62-63-WAIT -WAIT -64-65-66-67-68-69 62-63-WAIT -WAIT -64-65-66... 63 63-WAIT -WAIT -WAIT -64-65-66 63-WAIT -WAIT -WAIT-64-65-66-67-68-69-70 63-WAIT -WAIT -WAIT -64-65-66...

that can be read from the Flash memory device. software to configure itself when necessary. instruction to return to Read mode (see Table 11). how the M58MR016 enters the CFI Query mode. Table 17. Query Structure Overview detailed in Tables 18, 19, 20, 21, 22 and 23. Query data are always presented on the lowest order data outputs. Table 18. CFI Query Identification String Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15 are ‘0’.

1. DRC means Die Revision Code.

Table 19. CFI Query System Interface Information

Table 20. Device Geometry Definition contiguous Erase Blocks of the same size.

Table 21. Primary Algorithm-Specific Extended Query Table contains less significant byte.

Table 22. Burst Read Information Table 23. Security Code Area

8 Byte

indicates no burst capability. (P+17)h = 4Ch 0007h Synchronous mode read capability configuration 3 Cont.

Table 26. DC Characteristics Note: 1. Sampled only, not 100% tested.

1. VPP may be connected to 12V power supply for a total of less than 100 hrs.

Table 27. Asynchronous Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV .

Figure 10. Asynchronous Read AC Waveforms Note: Write Enable (W) = High.

Figure 11. Page Read AC Waveforms

Table 28. Synchronous Burst Read AC Characteristics

Figure 12. Synchronous Burst Read Note: 1. The number of clock cycles to be inserted depends upon the x-latency set in the read configuration register.

1. WAIT signal can be configured to be active during wait state or one cycle below wait state.
2. WAIT signal is asserted only when burst length is configured as continuous (see Burst Read section for further information).

Table 29. Write AC Characteristics, Write Enable Controlled

Figure 13. Write AC Waveforms, W Controlled

Table 30. Write AC Characteristics, Chip Enable Controlled

Figure 14. Write AC Waveforms, E Controlled

Figure 15. Reset and Power-up AC Waveforms Table 31. Reset and Power-up AC Characteristics Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns.

1. Sampled only, not 100% tested.
2. It is important to assert RP in order to allow proper CPU initialization during Power-up or System reset.

Table 32. Program, Erase Times and Program, Erase Endurance Cycles erase should perform significantly better.

1. Excludes the time needed to execute the sequence for program instruction.
2. Same timing value if VPP = 12V.

Figure 16. Program Flowchart and Pseudo Code (1)

1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

Figure 17. Double Word Program and Tetra Word Program Flowchart and Pseudo code (1)

1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
2. Address 1 and address 2 must be consecutive addresses differing only for address bit A0.
3. Address, address 2, address 3 and address 4 must be consecutive addresses differing only for address bit A1-A0.

Figure 18. Program Suspend & Resume Flowchart and Pseudo Code

Figure 19. Block Erase Flowchart and Pseudo Code

Figure 20. Erase Suspend & Resume Flowchart and Pseudo Code

Table 33. Command Interface States - Lock table

Table 34. Command Interface States - Modify table

Table 35. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. Table 36. Daisy Chain Ordering Scheme vice, please contact the STMicroelectronics Sales Office nearest to you.

Table 37. Document Revision History sion version 01 equals 1.0). modified in Table 28, Synchronous Burst Read AC Characteristics. Document status changed from Product Preview to Preliminary Data.

Table 38. TFBGA48 - 10 x 4 ball array, 0.5 mm pitch, Package Mechanical Data Figure 21. TFBGA48 - 10 x 4 ball array, 0.5 mm pitch, Bottom View Package Outline

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