M58CR064Q85ZB6T

M58CR064C STMICROELECTRONICS | Alldatasheet

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64 Mbit (4Mb x 16, Dual Bank, Burst )

Figure 1. Package

M58CR064C, M58CR064D, M58CR064P, M58CR064Q SUMMARY DESCRIPTION The M58CR064 is a 64 Mbit (4Mbit x16) non-vola- tile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2V V DD sup- ply for the circuitry and a 1.65V to 3.3V VDDQ sup- ply for the Input/Output pins. An optional 12V VPP power supply is provided to speed up customer programming. In M58CR064C and M58CR064D the VPP pin can also be used as a control pin to provide absolute protection against program or erase. In M58CR064P and M58CR064Q this fea- ture is disabled. The device features an asymmetrical block archi- tecture. M58CR064 has an array of 135 blocks, and is divided into two banks, Banks A and B. The Dual Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in the other bank. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory maps are shown in Figure 4. The Parameter Blocks are located at the top of the memory address space for the M58CR064C and M58CR064P, and at the bot- tom for the M58CR064D and M58CR064Q. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage V DD . Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the tim- ings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC stan- dards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 54MHz. The M58CR064 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any acciden- tal programming or erasure. In M58CR064C and M58CR064D there is an additional hardware pro- tection against program and erase. When V PP ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at Power- Up. The device includes a Protection Register and a Security Block to increase the protection of a sys- tem’s design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. The Security Block, pa- rameter block 0, can be permanently protected by the user. Figure 5, shows the Security Block and Protection Register Memory Map. The memory is offered in a TFBGA56, 6.5 x 10mm, 0.75 mm ball pitch package and is supplied with all the bits erased (set to ’1’).

Figure 2. Logic Diagram Table 1. Signal Names

Figure 3. TFBGA Connections (Top view through package) Table 2. Bank Architecture

Figure 4. Memory Map

512 Kbit or

32 KWord

64 Kbit or

4 KWord

M58CR064C, M58CR064D, M58CR064P, M58CR064Q SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Bus Write operation. Chip Enable (E ). The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. When Chip Enable is at V ILand Reset/Power-Down is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the stand-by level. Output Enable (G ).The Output Enable controls the outputs during the Bus Read operation of the memory. Write Enable (W ).The Write Enable controls the Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Write Protect (WP ). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at V IL, the Lock- Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or un- locked. (refer to Table 13, Lock Status). Reset/Power-Down (RP ). The Reset/Power- Down input provides a hardware reset of the mem- ory, and/or Power-Down functions, depending on the Configuration Register status. When Reset/ Power-Down is at V IL, the memory is in reset mode: the outputs are high impedance and if the Power-Down function is enabled the current con- sumption is reduced to the Reset Supply Current I DD2 . Refer to Table 18, DC Characteristics - Cur- rents for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Reg- ister is reset. When Reset/Power-Down is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset/Power-Down pin can be interfaced with 3V logic without any additional circuitry. It can be tied to V RPH (refer to Table 19, DC Characteris- tics). Latch Enable (L).Latch Enable latches the ad- dress bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is in- hibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Clock (K).The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configura- tion settings) when Latch Enable is at V IL. Clock is don't care during asynchronous read and in write operations. Wait (WAIT ).Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high imped- ance when Chip Enable or Output Enable are at V IH or Reset/Power-Down is at VIL. It can be con- figured to be active during the wait cycle or one clock cycle in advance. VDD Supply Voltage.VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage.VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from V DD . VDDQ can be tied to VDD or can use a separate supply. VPP Program Supply Voltage.VPP i s b o t h a control input and a power supply pin. In M58CR064C/D the two functions are selected by the voltage range applied to the pin. In the M58CR064P/Q the control feature is disabled. In M58CR064C/D if V PP is kept in a low voltage range (0V to VDDQ ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while V PP > VPP1 enables these functions (see Ta- bles 18 and 19, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If V PP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable un- til the Program/Erase algorithm is completed. VSS Ground. VSS ground is the reference for the core supply. It must be connected to the system ground. VSSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by VDDQ . VSSQ must be connected to VSS

dress Latch, Output Disable, Standby and Reset. See Table 3, Bus Operations, for a summary. not affect Bus Write operations. the memory (see Command Interface section). details of the timing requirements. vice enters Standby mode when finished. Table 3. Bus Operations

1. L can be tied to VIH if the valid address has been previously latched.

the progress or the result of the operation. plain in detail how to perform each command. Table 4. Command Codes

M58CR064C, M58CR064D, M58CR064P, M58CR064Q COMMAND INTERFACE - STANDARD COMMANDS The following commands are the basic commands used to read, write to and configure the device. Refer to Table 5, Standard Commands, in con- junction with the following text descriptions. Read Array Command The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command and re- turn the addressed bank to Read Array mode. Subsequent read operations will read the ad- dressed location and output the data. A Read Ar- ray command can be issued in one bank while programming or erasing in the other bank. Howev- er if a Read Array command is issued to a bank currently executing a Program or Erase operation the command will be ignored. Read Status Register Command A Bank’s Status Register indicates when a Pro- gram or Erase operation is complete and the suc- cess or failure of operation itself. Issue a Read Status Register command to read the Status Reg- ister content of the addressed Bank. The Read Status Register command can be issued at any time, even during Program or Erase operations. The following Bus Read operations output the con- tent of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G re- turns to VIH. Either E or G must be toggled to up- date the latched data. See Table 8 for the description of the Status Register Bits. This mode supports asynchronous or single synchronous reads only. Read Electronic Signature Command The Read Electronic Signature command reads the Manufacturer and Device Codes, the Block Locking Status, the Protection Register, and the Configuration Register. The Read Electronic Signature command consists of one write cycle to an address within the bottom bank. A subsequent read operation in the address of the bottom bank will output the Manufacturer Code, the Device Code, the protection Status of Blocks of the bottom bank, the Die Revision Code, the Protection Register, or the Read Configuration Register (see Table 6). If the first write cycle of Read Electronic Signature command is issued to an address within the top bank, a subsequent read operation in an address of the top bank will output the protection Status of blocks of the top bank. The status of the other bank is not affected by the command (see Table 11). This mode supports asynchronous or single synchronous reads only, it does not support page mode or synchronous burst reads. Read CFI Query Command The Read CFI Query command is used to read data from the Common Flash Interface (CFI) memory area located in the bottom bank. The Read CFI Query Command consists of one Bus Write cycle, to an address within the bottom bank. Once the command is issued subsequent Bus Read operations in the same bank read from the Common Flash Interface. If a Read CFI Query command is issued in a bank that is executing a Program or Erase operation the bank will go into Read Status Register mode, sub- sequent Bus Read cycles will output the Status Register and the Program/Erase controller will continue to Program or Erase in the background. When the Program or Erase operation has fin- ished the device will enter Read CFI Query mode. This mode supports asynchronous or single syn- chronous reads only, it does not support page mode or synchronous burst reads. The status of the other banks is not affected by the command (see Table 11). After issuing a Read CFI Query command, a Read Array command should be issued to the addressed bank to return the bank to read mode. See Appendix B, Common Flash Interface, Tables 30, 31, 32, 33, 34 and 35 for details on the infor- mation contained in the Common Flash Interface memory area. Clear Status Register Command The Clear Status Register command can be used to reset (set to ‘0’) error bits SR1, SR3, SR4 and SR5 in the Status Register of the addressed bank. One bus write cycle is required to issue the Clear Status Register command. After the Clear Status Register command the bank returns to Read Array mode. The error bits in the Status Register do not auto- matically return to ‘0’ when a new command is is- sued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. Block Erase Command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. The Block Erase command can be issued at any moment, re- gardless of whether the block has been pro- grammed or not. Two Bus Write cycles are required to issue the command. ■ The first bus cycle sets up the Erase command.

M58CR064C, M58CR064D, M58CR064P, M58CR064Q ■ The second latches the block address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to V IL. As data integrity cannot be guaran- teed when the Erase operation is aborted, the block must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode un- til a Read Array, Read CFI Query or Read Elec- tronic Signature command is issued. During Erase operations the bank containing the block being erased will only accept the Read Sta- tus Register and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed infor- mation about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 14, Program, Erase Times and Pro- gram/Erase Endurance Cycles. See Appendix C, Figure 24, Block Erase Flow- chart and Pseudo Code, for a suggested flowchart for using the Block Erase command. Program Command The memory array can be programmed word-by- word. Only one Word in one bank can be pro- grammed at any one time. Two bus write cycles are required to issue the Program Command. ■ The first bus cycle sets up the Program command. ■ The second latches the Address and the Data to be written and starts the Program/Erase Controller. After programming has started, read operations in the bank being programmed output the Status Register content. During Program operations the bank being pro- grammed will only accept the Read Status Regis- ter and the Program/Erase Suspend command. Refer to Dual Operations section for detailed infor- mation about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. See Appendix C, Figure 20, Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. A Bank Erase operation cannot be suspended. One bus write cycle is required to issue the Pro- gram/Erase Suspend command. Once the Pro- gram/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to ‘1’. The command must be addressed to the bank containing the Program or Erase operation. During Program/Erase Suspend the Command In- terface will accept the Program/Erase Resume, Read Array (cannot read the suspended block), Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Clear status Register, Program, Block Lock, Block Lock- Down or Protection Program commands will also be accepted. The block being erased may be pro- tected by issuing the Block Lock, Block Lock- Down or Protection Register Program commands. Only the blocks not being erased may be read or programmed correctly. When the Program/Erase Resume command is issued the operation will complete. Refer to the Dual Operations section for detailed information about simultaneous opera- tions allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to V IH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 23, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 25, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command must be written to the bank containing the Program or Erase Suspend. The Program/Erase Resume command changes the read mode of the target bank to Read Status Register mode. If a Program command is issued during a Block Erase Suspend, then the erase cannot be re- sumed until the programming operation has com- pleted. It is possible to accumulate suspend operations. For example: suspend an erase oper- ation, start a programming operation, suspend the programming operation then read the array. See Appendix C, Figure 23, Program Suspend & Re- sume Flowchart and Pseudo Code, and Figure 25, Erase Suspend & Resume Flowchart and Pseudo

M58CR064C, M58CR064D, M58CR064P, M58CR064Q Code for flowcharts for using the Program/Erase Resume command. Protection Register Program Command The Protection Register Program command is used to Program the 128 bit user One-Time-Pro- grammable (OTP) segment of the Protection Reg- ister. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protec- tion Register Program command. ■ The first bus cycle sets up the Protection Register Program command. ■ The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register con- tent after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register. Bit 1 of the Pro- tection Lock Register also protects bit 2 of the Pro- tection Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of Parameter Block #0 (see Figure 5, Security Block and Protection Register Memory Map). Attempting to program a previously protect- ed Protection Register will result in a Status Reg- ister error. The protection of the Protection Register and/or the Security Block is not revers- ible. The Protection Register Program cannot be sus- pended. See Appendix C, Figure 27, Protection Register Program Flowchart and Pseudo Code, for a flowchart for using the Protection Register Program command. Set Configuration Register Command. The Set Configuration Register command is used to write a new value to the Configuration Control Register which defines the burst length, type, X la- tency, Synchronous/Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Configuration Register command. ■ The first cycle writes the setup command and the address corresponding to the Configuration Register content. ■ The second cycle writes the Configuration Register data and the confirm command. Once the command is issued the memory returns to Read mode. The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1 on A1, etc.; the other address bits are ignored. Block Lock Command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. ■ The first bus cycle sets up the Block Lock command. ■ The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 13 shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix C, Figure 26, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock command. Block Unlock Command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to is- sue the Block Unlock command. ■ The first bus cycle sets up the Block Unlock command. ■ The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 13 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and Ap- pendix C, Figure 26, Locking Operations Flow- chart and Pseudo Code, for a flowchart for using the Unlock command. Block Lock-Down Command A locked or unlocked block can be locked-down by issuing the Block Lock-Down command. A locked- down block cannot be programmed or erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock com- mand. Two Bus Write cycles are required to issue the Block Lock-Down command. ■ The first bus cycle sets up the Block Lock command. ■ The second Bus Write cycle latches the block address.

using the Read Electronic Signature command. for using the Lock-Down command. Table 5. Standard Commands Register Address, PRD=Protection Register Data, CRD=Configuration Register Data.

1. Must be same bank as in the first cycle. The signature addresses are listed in Table 6.
2. When addressed to a block in the Top Bank, reads Block Protection data only.

Table 6. Electronic Signature Codes Note: CR=Configuration Register. Figure 5. Security Block and Protection Register Memory Map

M58CR064C, M58CR064D, M58CR064P, M58CR064Q COMMAND INTERFACE - FACTORY PROGRAM COMMANDS The Factory Program commands are used to speed up programming. They require VPP to be at VPPH except for the Bank Erase command which also operates at VPP = VDD . Refer to Table 7, Fac- tory Program Commands, in conjunction with the following text descriptions. Bank Erase Command The Bank Erase command can be used to erase a bank. It sets all the bits within the selected bank to ’1’. All previous data in the bank is lost. The Bank Erase command will ignore any protected blocks within the bank. If all blocks in the bank are pro- tected then the Bank Erase operation will abort and the data in the bank will not be changed. The Status Register will not output any error. Bank Erase operations can be performed at both V PP = VPPH and VPP = VDD . Two Bus Write cycles are required to issue the command. ■ The first bus cycle sets up the Bank Erase command. ■ The second latches the bank address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Bank Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the bank must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode un- til a Read Array, Read CFI Query or Read Elec- tronic Signature command is issued. During Bank Erase operations the bank being erased will only accept the Read Status Register command, all other commands will be ignored. A Bank Erase operation cannot be suspended. For optimum performance, Bank Erase com- mands should be limited to a maximum of 100 Pro- gram/Erase cycles per Block. After 100 Program/ Erase cycles the internal algorithm will still operate properly but some degradation in performance may occur. Dual operations are not supported during Bank Erase operations and the command cannot be suspended. Typical Erase times are given in Table 14, Pro- gram, Erase Times and Program/Erase Endur- ance Cycles. Double Word Program Command The Double Word Program command improves the programming throughput by writing a page of two adjacent words in parallel. The two words must differ only for the address A0. Programming should not be attempted when V PP is not at VPPH . The command can be executed if VPP is below VPPH but the result is not guaranteed. Three bus write cycles are necessary to issue the Double Word Program command. ■ The first bus cycle sets up the Double Word Program Command. ■ The second bus cycle latches the Address and the Data of the first word to be written. ■ The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Read operations in the bank being programmed output the Status Register content after the pro- gramming has started. During Double Word Program operations the bank being programmed will only accept the Read Sta- tus Register command, all other commands will be ignored. Dual operations are not supported during Double Word Program operations. It is not recom- mended to suspend the Double Word Program command. Typical Program times are given in Ta- ble 14, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. See Appendix C, Figure 21, Double Word Pro- gram Flowchart and Pseudo Code, for the flow- chart for using the Double Word Program command. Quadruple Word Program Command The Quadruple Word Program command im- proves the programming throughput by writing a page of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. Programming should not be attempted when V PP is not at VPPH . The command can be executed if VPP is below VPPH but the result is not guaranteed. Five bus write cycles are necessary to issue the Quadruple Word Program command. ■ The first bus cycle sets up the Double Word Program Command. ■ The second bus cycle latches the Address and the Data of the first word to be written.

Data of the second word to be written. the Data of the third word to be written. the Program/Erase Controller. Table 7. Factory Program Commands Note: 1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, WA1 is the Start Address.

1. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0.
2. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

M58CR064C, M58CR064D, M58CR064P, M58CR064Q STATUS REGISTER The M58CR064 has two Status Registers, one for each bank. The Status Registers provide informa- tion on the current or previous Program or Erase operations executed in each bank. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updat- ed on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to V IH. The Status Reg- ister can only be read using single asynchronous or single synchronous reads. Bus Read opera- tions from any address within the bank, always read the Status Register during Program and Erase operations. The various bits convey information about the sta- tus and any errors of the operation. Bits SR7, SR6 and SR2 give information on the status of the bank and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by is- suing a Clear Status Register command or a hard- ware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 8, Status Register Bits. Refer to Table 8 in conjunction with the following text descriptions. Program/Erase Controller Status Bit (SR7).The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in the addressed bank. When the Pro- gram/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase Control- ler is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low im- mediately after a Program/Erase Suspend com- mand is issued until the Program/Erase Controller pauses. After the Program/Erase Controller paus- es the bit is High. During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Reg- ister should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, V PP Status and Block Lock Status bits should be tested for errors. Erase Suspend Status Bit (SR6).The Erase Suspend Status bit indicates that an Erase opera- tion has been suspended or is going to be sus- pended in the addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Re- sume command. The Erase Suspend Status should only be consid- ered valid when the Program/Erase Controller Sta- tus bit is High (Program/Erase Controller inactive). SR7 is set within 30µs of the Program/Erase Sus- pend command being issued therefore the memo- ry may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status Bit (SR5).The Erase Status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maxi- mum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be re- set Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status Bit (SR4).The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to ‘1’), the Pro- gram/Erase Controller has applied the maximum number of pulses to the byte and still failed to ver- ify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Con- troller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. V PP Status Bit (SR3).The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can oc- cur if VPP becomes invalid during an operation. When the VPP Status bit is Low (set to ‘0’), the volt- age on the VPP pin was sampled at a valid voltage; when the VPP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK , the memory is protected and Pro- gram and Erase operations cannot be performed.

otherwise the new command will appear to fail. bit is High (Program/Erase Controller inactive). sued the Program Suspend Status bit returns Low. modify the contents of a locked block. the new command will appear to fail. Table 8. Status Register Bits Note: Logic level '1' is High, '0' is Low.

M58CR064C, M58CR064D, M58CR064P, M58CR064Q CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will per- form. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power-Up the device is configured for asynchronous page read (CR15 = 1). The Configuration Register bits are described in Table 9. They specify the selec- tion of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 6 and 7 for examples of synchronous burst configurations. Read Select Bit (CR15) The Read Select bit, CR15, is used to switch be- tween asynchronous and synchronous Bus Read operations. When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst Read is support- ed in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to’1’ for asynchronous access. X-Latency Bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Ta- ble 9, Configuration Register. The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system pa- rameters. Two conditions must be satisfied: 1. Depending on whether t AVK_CPU or tDELAY is supplied either one of the following two equations must be satisfied: (n + 1) t K ≥ tACC - tAVK_CPU + tQVK_CPU (n + 2) tK ≥ tACC + tDELAY + tQVK_CPU 2. and also tK > tKQV + tQVK_CPU where n is the chosen X-Latency configuration code t K is the clock period tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last t DELAY is address valid, L Low, or E Low to clock, whichever occurs last tQVK_CPU is the data setup time required by the system CPU, tKQV is the clock to data valid time tACC is the random access time of the device. Refer to Figure 6, X-Latency and Data Output Configuration Example. Power-Down Bit (CR10) The Power-Down bit is used to enable or disable the power-down function. When the Power-Down bit is set to ‘0’ the power- down function is disabled. If the Reset/Power- Down, RP , pin goes Low, VIL, the device is reset and the supply current, IDD, is reduced to the standby value, IDD3 . When the Power-Down bit is set to ‘1’ the power- down function is enabled. If the Reset/Power- Down, RP , pin goes Low, VIL, the device goes into the power-down state and the supply current, IDD, is reduced to the power-down value, IDD2 . The recovery time after a Reset/Power-Down, RP, pulse is significantly longer when power-down is enabled (see Table 24). After a reset the Power-Down Bit is set to ‘0’. Wait Configuration Bit (CR8) In burst mode the Wait bit controls the timing of the Wait output pin, WAIT . When the Wait bit is ’0’ the Wait output pin is asserted during the wait state. When the Wait bit is ’1’ (default) the Wait output pin is asserted one clock cycle before the wait state. WAIT is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap config- uration is selected. WAIT is not asserted during asynchronous reads, single synchronous reads or during latency in synchronous reads. Burst Type Bit (CR7) The Burst Type bit is used to configure the se- quence of addresses read as sequential or inter- leaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses; when the Burst Type bit is ’1’ (default) the memory outputs from sequential addresses. See Tables 10, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode. Valid Clock Edge Bit (CR6) The Valid Clock Edge bit, CR6, is used to config- ure the active edge of the Clock, K, during Syn- chronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock is active. Wrap Burst Bit (CR3) The burst reads can be confined inside the 4 or 8 Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select be- tween wrap and no wrap. When the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not wrap.

ation as result of a single address latch cycle. necessary before the data is output. access. See also Table 10, Burst Type Definition. Table 9. Configuration Register

0 Synchronous Read

1 Asynchronous Read (Default at power-on)

111 Reserved

0 Power-Down disabled

1 Power-Down enabled

1 WAIT is active one data cycle before wait state (default)

0 Interleaved

1 Sequential (default)

0 Falling Clock edge

1 Rising Clock edge

0 Wrap

1 No Wrap

111 Continuous (CR7 m ust be set to ‘1’)

Table 10. Burst Type Definition

M58CR064C, M58CR064D, M58CR064P, M58CR064Q READ MODES Read operations can be performed in two different ways depending on the settings in the Configura- tion Register. If the clock signal is ‘don’t care’ for the data output, the read operation is Asynchro- nous; if the data output is synchronized with clock, the read operation is Synchronous. The Read mode and data output format are deter- mined by the Configuration Register. (See Config- uration Register section for details). All banks supports both asynchronous and synchronous read operations. The Dual Bank architecture al- lows read operations in one bank, while write op- erations are being executed in the other (see Tables 11 and 12). Asynchronous Read Mode In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data corre- sponding to the address latched, that is the mem- ory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Reg- ister must be set to ‘1’ for Asynchronous opera- tions. In Asynchronous Read mode a Page of data is in- ternally read and stored in a Page Buffer. The Page has a size of 4 Words and is addressed by A0 and A1 address inputs. The address inputs A0 and A1 are not gated by Latch Enable in Asyn- chronous Read mode. The first read operation within the Page has a longer access time (T acc, Random access time), subsequent reads within the same Page have much shorter access times. If the Page changes then the normal, longer timings apply again. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Ac- cess Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. See Table 20, Asynchronous Read AC Character- istics, Figure 10, Asynchronous Random Access Read AC Waveform and Figure 11, Asynchronous Page Read AC Waveform for details. Synchronous Burst Read Mode In Synchronous Burst Read mode the data is out- put in bursts synchronized with the clock. It is pos- sible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read opera- tions, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchro- nous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are con- figured in the Configuration Register. A burst sequence is started at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and after a delay of 2 to 5 clock cycles (X latency bits CR13-CR11) the corresponding data are out- put on each clock cycle. The number of Words to be output during a Syn- chronous Burst Read operation can be configured as 4 or 8 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Con- figuration bit CR9). The order of the data output can be modified through the Burst Type and the Wrap Burst bits in the Configuration Register. The burst sequence may be configured to be sequential or interleaved (CR7). The burst reads can be confined inside the 4 or 8 Word boundary (Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to the Burst Length (4 or 8 Words), the wrapped configuration has no impact on the output sequence. Interleaved mode is not allowed in Con- tinuous Burst Read mode or with No Wrap se- quences. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst se- quence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. WAIT is asserted during the Wait state and at the end of 4- and 8-Word Burst. It is deasserted during the X latency and when output data are valid. In Continuous Burst Read mode a Wait state will oc- cur when crossing the first 64 Word boundary. If the burst starting address is aligned to a 4 Word Page, the Wait state will not occur. The WAIT signal is active Low. The WAIT signal is meaningful only in Synchronous Burst Read mode, in other modes, WAIT is not asserted (ex- cept for Read Array mode). See Table 21, Synchronous Read AC Character- istics and Figure 12, Synchronous Burst Read AC Waveform for details. Single Synchronous Read Mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Other Configuration Register parameters have no effect on Single Synchronous Read operations.

is being programmed or erased. confirm cycles of program or erase operations. read operations are possible at any moment. pendix D, Command Interface State Tables. Table 11. Dual Operations Allowed In Other Bank Table 12. Dual Operations Allowed In Same Bank Note: 1. Not allowed in the Block or Word that is being erased or programmed.

M58CR064C, M58CR064D, M58CR064P, M58CR064Q BLOCK LOCKING The M58CR064 features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. ■ Lock/Unlock - this first level allows software- only control of block locking. ■ Lock-Down - this second level requires hardware interaction before locking can be changed. ■ VPP ≤ VPPLK - the third level offers a complete hardware protection against program and erase on all blocks (M58CR064C/D only). The first two levels (Lock/Unlock and Lock-Down) are available in M58CR064C/D and M58CR064P/ Q. The third level (V PP ≤ VPPLK ) is only available for the M58CR064C/D versions, in the M58CR064P/Q this feature has been disabled. For all devices the protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 13, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 26, shows a flowchart for the locking operations. Reading a Block’s Lock Status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subse- quent reads at the address specified in Table 6, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when enter- ing Lock-Down. DQ1 indicates the Lock-Down sta- tus and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or af- ter a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase oper- ations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software com- mands. An Unlocked block can be Locked by issu- ing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be un- locked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status can- not be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. Locked- Down blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from pro- gram, erase and protection status changes. When WP =1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individual- ly unlocked to the (1,1,0) state by issuing the soft- ware command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase opera- tion, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After complet- ing any desired lock, read, or program operations, resume the erase operation with the Erase Re- sume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix D, Com- mand Interface State Table, for detailed informa- tion on which commands are valid during erase suspend.

Table 13. Lock Status in the Read Electronic Signature command with A1 = VIH and A0 = VIL.

1. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
2. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

Table 14. Program, Erase Times and Program, Erase Endurance Cycles

1. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms).
2. Excludes the time needed to execute the command sequence.

Table 15. Absolute Maximum Ratings

ing on the quoted parameters. Table 16. Operating and AC Measurement Conditions Figure 8. AC Measurement I/O Waveform Figure 9. AC Measurement Load Circuit Table 17. Capacitance Note: Sampled only, not 100% tested.

Table 18. DC Characteristics - Currents Note: 1. Sampled only, not 100% tested.

1. VDD Dual Operation current is the sum of read and program or erase currents.

4 Word 6 13 mA

8 Word 8 14 mA

4 Word 7 16 mA

8 Word 10 18 mA

Table 19. DC Characteristics - Voltages

Figure 10. Asynchronous Random Access Read AC Waveforms Note. Write Enable, W, is High.

Figure 11. Asynchronous Page Read AC Waveforms

Table 20. Asynchronous Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV .

Figure 12. Synchronous Burst Read AC Waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

1. The WAIT signal can be configured to be active during wait state or one cycle before.
2. Address latched and data output on the rising clock edge.

Figure 13. Single Synchronous Read AC Waveforms Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.

1. The WAIT signal is configured to be active during wait state.
2. WAIT is always deasserted when addressed bank is in Read CFI, Read SR or Read electronic signature mode.

WAIT signals valid data if the addressed bank is in Read Array mode.

1. Address latched and data output on the rising clock edge.

Table 21. Synchronous Read AC Characteristics Note: 1. Sampled only, not 100% tested.

1. For other timings please refer to Table 20, Asynchronous Read AC Characteristics.

Figure 14. Write AC Waveforms, Write Enable Controlled

Table 22. Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.

1. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a

Figure 15. Write AC Waveforms, Chip Enable Controlled

Table 23. Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested.

1. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a

Figure 16. Reset and Power-up AC Waveforms Table 24. Reset and Power-up AC Characteristics Note: 1. The device Reset is possible but not guaranteed if tPLPH < 50ns.

1. Sampled only, not 100% tested.
2. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.

Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline Note: Drawing is not to scale. Table 25. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data

Figure 18. TFBGA56 Daisy Chain - Package Connections (Top view through package)

Figure 19. TFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package)

Table 26. Ordering Information Scheme Table 27. Daisy Chain Ordering Scheme D evices are shipped from the factory with the memory content bits erased to ’1’. please contact the ST Sales Office nearest to you.

Table 28. Top Boot Block Addresses,

M58CR064C, M58CR064D, M58CR064P, M58CR064Q Bank B 79 32 1B8000-1BFFFF 80 32 1B0000-1B7FFF 81 32 1A8000-1AFFFF 82 32 1A0000-1A7FFF 83 32 198000-19FFFF 84 32 190000-197FFF 85 32 188000-18FFFF 86 32 180000-187FFF 87 32 178000-17FFFF 88 32 170000-177FFF 89 32 168000-16FFFF 90 32 160000-167FFF 91 32 158000-15FFFF 92 32 150000-157FFF 93 32 148000-14FFFF 94 32 140000-147FFF 95 32 138000-13FFFF 96 32 130000-137FFF 97 32 128000-12FFFF 98 32 120000-127FFF 99 32 118000-11FFFF 100 32 110000-117FFF 101 32 108000-10FFFF 102 32 100000-107FFF 103 32 0F8000-0FFFFF 104 32 0F0000-0F7FFF 105 32 0E8000-0EFFFF 106 32 0E0000-0E7FFF 107 32 0D8000-0DFFFF 108 32 0D0000-0D7FFF 109 32 0C8000-0CFFFF Bank B 110 32 0C0000-0C7FFF 111 32 0B8000-0BFFFF 112 32 0B0000-0B7FFF 113 32 0A8000-0AFFFF 114 32 0A0000-0A7FFF 115 32 098000-09FFFF 116 32 090000-097FFF 117 32 088000-08FFFF 118 32 080000-087FFF 119 32 078000-07FFFF 120 32 070000-077FFF 121 32 068000-06FFFF 122 32 060000-067FFF 123 32 058000-05FFFF 124 32 050000-057FFF 125 32 048000-04FFFF 126 32 040000-047FFF 127 32 038000-03FFFF 128 32 030000-037FFF 129 32 028000-02FFFF 130 32 020000-027FFF 131 32 018000-01FFFF 132 32 010000-017FFF 133 32 008000-00FFFF 134 32 000000-007FFF

Table 29. Bottom Boot Block Addresses,

M58CR064C, M58CR064D, M58CR064P, M58CR064Q Bank B 54 32 178000-17FFFF 53 32 170000-177FFF 52 32 168000-16FFFF 51 32 160000-167FFF 50 32 158000-15FFFF 49 32 150000-157FFF 48 32 148000-14FFFF 47 32 140000-147FFF 46 32 138000-13FFFF 45 32 130000-137FFF 44 32 128000-12FFFF 43 32 120000-127FFF 42 32 118000-11FFFF 41 32 110000-117FFF 40 32 108000-10FFFF 39 32 100000-107FFF Bank A 38 32 0F8000-0FFFFF 37 32 0F0000-0F7FFF 36 32 0E8000-0EFFFF 35 32 0E0000-0E7FFF 34 32 0D8000-0DFFFF 33 32 0D0000-0D7FFF 32 32 0C8000-0CFFFF 31 32 0C0000-0C7FFF 30 32 0B8000-0BFFFF 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 0A0000-0A7FFF 26 32 098000-09FFFF 25 32 090000-097FFF 24 32 088000-08FFFF 23 32 080000-087FFF Bank A 22 32 078000-07FFFF 21 32 070000-077FFF 20 32 068000-06FFFF 19 32 060000-067FFF 18 32 058000-05FFFF 17 32 050000-057FFF 16 32 048000-04FFFF 15 32 040000-047FFF 14 32 038000-03FFFF 13 32 030000-037FFF 12 32 028000-02FFFF 11 32 020000-027FFF 10 32 018000-01FFFF 9 32 010000-017FFF 8 32 008000-00FFFF 7 4 007000-007FFF 6 4 006000-006FFF 5 4 005000-005FFF 4 4 004000-004FFF 3 4 003000-003FFF 2 4 002000-002FFF 1 4 001000-001FFF 0 4 000000-000FFF

the other outputs (DQ8-DQ15) are set to 0. Table 30. Query Structure Overview detailed in Tables 31, 32, 33, 34 and 35. Query data is always presented on the lowest order data outputs. Table 31. CFI Query Identification String

Table 32. CFI Query System Interface Information Table 33. Device Geometry Definition

Table 34. Primary Algorithm-Specific Extended Query Table contains less significant byte.

Table 35. Burst Read Information determine page-mode data output width.

8 Bytes

(P+17)h = 50h 0007h Synchronous mode read capability configuration 3 Cont.

Figure 20. Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

Figure 21. Double Word Program Flowchart and Pseudo code

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

Figure 22. Quadruple Word Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.

Figure 23. Program Suspend & Resume Flowchart and Pseudo Code

Figure 24. Block Erase Flowchart and Pseudo Code Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

Figure 25. Erase Suspend & Resume Flowchart and Pseudo Code

Figure 26. Locking Operations Flowchart and Pseudo Code

Figure 27. Protection Register Program Flowchart and Pseudo Code

1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

Table 36. Command Interface States - Lock table Note: PS = Program Suspend, ES = Erase Suspend.

Table 37. Command Interface States - Modify Table Note: PS = Program Suspend, ES = Erase Suspend.

M58CR064C, M58CR064D, M58CR064P, M58CR064Q

REVISION HISTORY

Table 38. Document Revision History modified at Offset 13h. Table 32, data modified at Offsets 20h, 23h, 24h and 25h. Erase Times and Program, Erase Endurance Cycles table modified. digit after the dot, and a major revision, by incrementing the digit before the dot. (revision version 09 equals 9.0). Document status changed from Preliminary Data to Datasheet. Table16, Operating and AC Measurement Conditions.

M58CR064C, M58CR064D, M58CR064P, M58CR064Q 24-Feb-2003 9.2 Revision History moved to end of document. 90ns Speed Class added. Bank Erase Command moved to Factory Program Commands section. Bank Erase cycles limited to 100 per Block. WAIT signal modified in Figure 7, Wait Configuration Example. WAIT behavior modified. Burst sequence in wrapped configuration and Burst sequence start specified in Synchronous Burst Read Mode paragraph. Erase replaced by Block Erase in Tables 11 and 12, Dual Operations allowed in Other Bank and in Same Bank, respectively. Latch signal corrected in Figure 11, Asynchronous Page Read AC Waveforms. Daisy Chain added. 06-Jun-2003 9.3 V DD and VDDQ minimum values changed for 90ns speed class in Table 16, Operating and AC Measurement Conditions. Minor text changes. Date Version Revision Details

M58CR064C, M58CR064D, M58CR064P, M58CR064Q Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.