M58BW16FB4T3

M58BW16F NUMONYX | Alldatasheet

Document overview

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• PDF pages: 87

Technical content

Datasheet sections

• 1 Description
• 1.1 Block protection
• 2 Signal descriptions
• 2.1 Address inputs (A0-Amax)
• 2.2 Data inputs/outputs (DQ0-DQ31)
• 2.3 Chip Enable (E
• 2.4 Output Enable (G )
• 2.5 Output Disable (GD )
• 2.6 Write Enable (W )
• 2.7 Reset/Power-down (RP )
• 2.8 Program/Erase Enable (PEN)
• 2.9 Latch Enable (L
• 2.10 Burst Clock (K)
• 2.11 Burst Address Advance (B )
• 2.12 Valid Data Ready (R)
• 2.13 Write Protect (WP )
• 2.14 Supply voltage (V DD)
• 2.15 Output supply voltage (V DDQ)
• 2.16 Input supply voltage (V DDQIN)
• 2.17 Ground (V SS and VSSQ)
• 2.18 Don’t use (DU)
• 2.19 Not connected (NC)
• 3 Bus operations
• 3.1 Asynchronous Bus operations
• 3.1.1 Asynchronous Bus Read
• 3.1.2 Asynchronous Latch Controlled Bus Read
• 3.1.3 Asynchronous Page Read
• 3.1.4 Asynchronous Bus Write
• 3.1.5 Asynchronous Latch Controlled Bus Write
• 3.1.6 Output Disable

Datasheet sections

• 5.5 PEN Status (bit 3)
• 5.6 Program Suspend Status (bit 2)
• 5.7 Block Protection Status (bit 1)
• 5.8 Bit
• 6 Maximum rating
• 7 DC and AC parameters
• 8 Package mechanical
• 9 Ordering information
• 10 Revision history

Features

■ Supply voltage –V DD = 2.7 V to 3.6 V (45 ns) or VDD = 2.5 V to 3.3 V (55 ns) –V DDQ = VDDQIN = 2.4 V to 3.6 V for I/O buffers ■ High performance – Access times: 45 and 55 ns – Synchronous burst reads – 75 MHz effective zero wait-state burst read – Asynchronous page reads ■ M58BW32F memory organization: – Eight 64 Kbit small parameter blocks – Four 128 Kbit large parameter blocks – Sixty-two 512 Kbit main blocks ■ M58BW16F memory organization: – Eight 64 Kbit parameter blocks – Thirty-one 512 Kbit main blocks ■ Hardware block protection –W P pin to protect any block combination from Program and Erase operations –P E N signal for Program/Erase Enable ■ Irreversible modify protection (OTP like) on

128 Kbits:

– Block 1 (bottom device) or block 72 (top device) in the M58BW32F – Blocks 2 and 3 (bottom device) or blocks 36 and 35 (top device) in the M58BW16F ■ Security – 64-bit unique device identifier (UID) ■ Fast programming – Write to buffer and program capability ■ Optimized for FDI drivers – Common Flash interface (CFI) – Fast Program/Erase Suspend feature in each block ■ Low power consumption – 100 µA typical Standby current ■ Electronic signature – Manufacturer code: 0020h – Top device codes: M58BW32FT: 8838h M58BW16FT: 883Ah – Bottom device codes: M58BW32FB: 8837h M58BW16FB: 8839h ■ Automotive device grade 3: – Temperature: –40 to 125 °C – Automotive grade certified LBGA LBGA80 (ZA) 10 x 8 ball array PQFP80 (T) www.numonyx.com

M58BW16F, M58BW32F Contents

Table 25. LBGA80 10 × 12 mm - 8 × 10 active ball array, 1 mm pitch, package

M58BW16F, M58BW32F Description

1 Description

The M58BW16F and M58BW32F are 16 and 32 Mbit non-volatile Flash memories, respectively. They can be erased electrically at block level and programmed in-system on a double-word basis using a 2.7 V to 3.6 V or 2.5 V to 3.3 V VDD supply for the circuit and a 2.4 V to 3.6 V VDDQ supply voltage for the input and output buffers. In the rest of the document the M58BW16F and M58BW32F will be referred to as M58BWxxF unless otherwise specified. The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous Bus operations. The Synchronous Burst Read interface allows a high data transfer rate controlled by the Burst Clock signal, K. It is capable of bursting fixed or unlimited lengths of data. The burst type, latency and length are configurable and can be easily adapted to a large variety of system clock frequencies and microprocessors. All write operations are asynchronous. On power-up the memory defaults to Read mode with an Asynchronous Bus. The device features an asymmetrical block architecture:

• The M58BW32F has an array of 62 main blocks of 512 Kbits each, plus 4 large parameter blocks of 128 Kbits each and 8 small parameter blocks of 64 Kbits each. The large and small parameter blocks are located either at the top (M58BW32FT) or at the bottom (M58BW32FB) of the address space. The first large parameter block is referred to as boot block and can be used either to store a boot code or parameters. The memory array organization is detailed in Table 2: M58BW32F top boot block addresses and Table 3: M58BW32F bottom boot block addresses.
• The M58BW16F has an array of 8 parameter blocks of 64 Kbits each and 31 main blocks of 512 Kbits each. In the M58BW16FT the parameter blocks are located at the top of the address space whereas in the M58BW16FB, they are located at the bottom. The memory array organization is detailed in Table 4: M58BW16F top boot block addresses and Table 5: M58BW16F bottom boot block addresses. Program and Erase commands are written to the command interface of the memory. An on- chip Program/Erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. Erase can be suspended in order to perform either Read or Program in any other block, and then resumed. Program can be suspended to Read data in any other block, and then resumed. Each block can be programmed and erased over 100,000 cycles.

Description M58BW16F, M58BW32F All blocks are protected during power-up. The M58BWxxF features five different levels of hardware and software block protection to avoid unwanted Program/Erase operations:

• Write/Protect Enable input, WP, hardware protects a combination of blocks from Program and Erase operations. The blocks to be protected are configured individually by issuing a Set Block Protection Configuration Register or a Clear Block Protection Configuration Register command.
• All Program or Erase operations are blocked when Reset, RP , is held Low.
• A Program/Erase Enable input, PEN, is used to protect all blocks, preventing Program and Erase operations from affecting their data.
• A permanent user-enabled protection against Modify operations is available: – on one specific 128-Kbit parameter block in the M58BW32F – block 1 for bottom devices or block 72 for top devices – on two specific 64-Kbit parameter blocks in the M58BW16F – blocks 2 and 3 for bottom devices or blocks 36 and 35 for top devices. A Reset/Power-down mode is entered when the RP input is Low. In this mode the power consumption is reduced to the standby level, the device is write protected and both the Status and Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High. A manufacturer code and a device code are available. They can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory. Finally, the M58BWxxF features a 64-bit unique device identifier (UID) which is programmed by Numonyx on the production line. It is unique for each die and can be used to implement cryptographic algorithms to improve security. Information is available in the CFI area (see Table 32: M58BW16F extended query information). The memory is offered in PQFP80 (14 x 20 mm) and LBGA80 (1.0 mm pitch) packages and it is supplied with all the bits erased (set to ’1’).

Figure 1. Logic diagram

Table 1. Signal names

1. Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F.

Figure 2. LBGA connections (top view through package)

1. Ball D3 is NC in the M58BW16F and A19 in the M58BW32F.

Figure 3. PQFP connections (top view through package)

M58BW16F, M58BW32F Description

1.1 Block protection

The M58BWxxF features four different levels of block protection.

• Write Protect pin, WP, - When WP is Low, VIL, the protection status that has been configured in the Block Protection Configuration Register is activated. The Block Protection Configuration Register is volatile. Any combination of blocks is possible. Any attempt to program or erase a protected block will return an error in the Status Register (see Table 13: Status Register bits).
• Reset/Power-down pin, RP, - If the device is held in reset mode (RP at VIL), no Program or Erase operation can be performed on any block.
• Program/Erase Enable, PEN, - The Program/Erase Enable input, PEN, protects all blocks by preventing Program and Erase operations from modifying the data. Prior to issuing a Program or Erase command, the Program/Erase Enable must be set to High (V IH). If it is Low (VIL), the Program or Erase operation is not accepted and an error is generated in the Status Register.
• Permanent protection against modify operations - specific OTP-like blocks can be permanently protected against modify operations (Program/Erase): – in the M58BW32F, a unique 128-Kbit parameter block – block 1 (01000h-01FFFh) for bottom devices or block 72 (FE000h-FEFFFh) for top devices – in the M58BW16F, two 64-Kbit parameter blocks – blocks 2 and 3 (01000h- 01FFFh) for bottom devices or blocks 36 and 35 (7E000h-7EFFFh) for top devices This protection is user-enabled. Details of how this protection is activated are provided in a dedicated application note. After a device reset the first two kinds of block protection (WP, RP) can be combined to give a flexible block protection. All blocks are protected at power-up.

Table 2. M58BW32F top boot block addresses

1. Addresses are indicated in 32-bit addressing.

Table 2. M58BW32F top boot block addresses (continued)

Table 3. M58BW32F bottom boot block addresses

1. Addresses are indicated in 32-bit word addressing.

Table 3. M58BW32F bottom boot block addresses (continued)

Table 4. M58BW16F top boot block addresses

Table 5. M58BW16F bottom boot block addresses

Signal descriptions M58BW16F, M58BW32F

2 Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device.

2.1 Address inputs (A0-Amax)

Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F. The Address inputs are used to select the cells to access in the memory array during Bus operations. During Bus Write operations they control the commands sent to the command interface of the Program/Erase controller. Chip Enable must be Low when selecting the addresses. The Address inputs are latched on the rising edge of Latch Enable L or Burst Clock K, whichever occurs first, in a Read operation. The Address inputs are latched on the rising edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write operation. The address latch is transparent when Latch Enable is Low, V IL. The address is internally latched in an Erase or Program operation.

2.2 Data inputs/outputs (DQ0-DQ31)

The Data inputs/outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. During Bus Write operations they represent the commands sent to the command interface of the Program/Erase controller. When used to input data or Write commands they are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. When Chip Enable and Output Enable are both Low, V IL, and Output Disable is at VIH, the data bus outputs data from the memory array, the Electronic Signature, the Block Protection Configuration Register, the CFI information or the contents of Burst Configuration Register or Status Register. The data bus is high impedance when the device is deselected with Chip Enable at V IH, Output Enable at VIH, Output Disable at VIL or Reset/Power-down at VIL. The Status Register content is output on DQ0-DQ7 and DQ8-DQ31 are at VIL.

2.3 Chip Enable (E )

The Chip Enable, E, input activates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E, at VIH deselects the memory and reduces the power consumption to the standby level.

2.4 Output Enable (G )

The Output Enable, G, gates the outputs through the data output buffers during a Read operation, when Output Disable GD is at VIH. When Output Enable G is at VIH, the outputs are high impedance independently of Output Disable.

M58BW16F, M58BW32F Signal descriptions

2.5 Output Disable (GD )

The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at VIH, the outputs are driven by the Output Enable. When Output Disable, GD, is at VIL, the outputs are high impedance independently of Output Enable. The Output Disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin.

2.6 Write Enable (W )

The Write Enable, W, input controls writing to the command interface, input address and data latches. Both addresses and data can be latched on the rising edge of Write Enable (also see Latch Enable, L

2.7 Reset/Power-down (RP )

The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware reset is achieved by holding Reset/Power-down Low, VIL, for at least tPLPH. Writing is inhibited to protect data, the command interface and the Program/Erase controller are reset. The Status Register information is cleared and power consumption is reduced to the standby level (I DD1). The device acts as deselected, that is the data outputs are high impedance. After Reset/Power-down goes High, VIH, the memory will be ready for Bus Read operations after a delay of tPHEL or Bus Write operations after tPHWL. If Reset/Power-down goes Low, VIL, during a Block Erase or a Program operation, the internal state machine handles the operation as a Program/Erase Suspend, so the maximum time defined inTable 12: Program, Erase times and endurance cycles must be applied. During power-up power should be applied simultaneously to V DD and VDDQIN with RP held at VIL. When the supplies are stable RP is taken to VIH. Output Enable, G, Chip Enable, E, and Write Enable, W, should be held at VIH during power-up. In an application, it is recommended to associate the Reset/Power-down pin, RP, with the reset signal of the microprocessor. Otherwise, if a Reset operation occurs while the memory is performing an Erase or program operation, the memory may output the Status Register information instead of being initialized to the default Asynchronous Random Read mode. See Table 24 and Figure 22: Reset, Power-down and Power-up AC waveforms - Control pins Low, for more details.

2.8 Program/Erase Enable (PEN)

The Program/Erase Enable input, PEN, protects all blocks by preventing Program and Erase operations from modifying the data. Prior to issuing a Program or Erase command, the Program/Erase Enable must be set to High (V IH). If it is Low (VIL), the Program or Erase operation is not accepted and an error is generated in the Status Register.

Signal descriptions M58BW16F, M58BW32F

2.9 Latch Enable (L )

The Bus Interface can be configured to latch the Address inputs on the rising edge of Latch Enable, L, for Asynchronous Latch Enable Controlled Read or Write or Synchronous Burst Read operations. In Synchronous Burst Read operations the address is latched on the active edge of the Clock when Latch Enable is Low, VIL. Once latched, the addresses may change without affecting the address used by the memory. When Latch Enable is Low, VIL, the latch is transparent. Latch Enable, L, can remain at VIL for Asynchronous Random Read and Write operations.

2.10 Burst Clock (K)

The Burst Clock, K, is used to synchronize the memory with the external bus during Synchronous Burst Read operations. Bus signals are latched on the active edge of the Clock. In Synchronous Burst Read mode the address is latched on the first rising clock edge when Latch Enable is Low, V IL, or on the rising edge of Latch Enable, whichever occurs first. During Asynchronous Bus Operations the Clock is not used.

2.11 Burst Address Advance (B )

The Burst Address Advance, B, controls the advancing of the address by the internal address counter during Synchronous Burst Read operations. Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the X-latency time has expired. If Burst Address Advance is Low, VIL, the internal address counter advances. If Burst Address Advance is High, VIH, the internal address counter does not change; the same data remains on the Data inputs/outputs and Burst Address Advance is not sampled until the Y -latency expires. The Burst Address Advance, B , may be tied to VIL.

2.12 Valid Data Ready (R)

The Valid Data Ready output, R, can be used during Synchronous Burst Read operations to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready, at V IH, indicates that new data is or will be available. When Valid Data Ready is Low, VIL, the previous data outputs remain active.

2.13 Write Protect (WP )

The Write Protect, WP, provides protection against Program or Erase operations. When Write Protect, WP, is at VIL, the protection status that has been configured in the Block Protection Configuration Register is activated. Program and Erase operations to protected blocks are disabled. When Write Protect WP is at VIH all the blocks can be programmed or erased, if no other protection is used.

M58BW16F, M58BW32F Signal descriptions

2.14 Supply voltage (V DD)

The supply voltage, VDD, is the core power supply. All internal circuits draw their current from the VDD pin, including the Program/Erase controller.

2.15 Output supply voltage (V DDQ)

The output supply voltage, VDDQ, is the output buffer power supply for all operations (Read, Program and Erase) used for DQ0-DQ31 when used as outputs.

2.16 Input supply voltage (V DDQIN)

The input supply voltage, VDDQIN, is the power supply for all input signal. Input signals are: K, B, L, W, GD, G, E, A0-Amax and DQ0-DQ31, when used as inputs.

2.17 Ground (V SS and VSSQ)

The ground VSS is the reference for the internal supply voltage VDD. The ground VSSQ is the reference for the output and input supplies VDDQ, and VDDQIN. It is essential to connect VSS and VSSQ together. Note: A 0.1 µF capacitor should be connected between the supply voltages, V DD, VDDQ and VDDQIN and the grounds, VSS and VSSQ to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during all operations of the parts, see Table 18: DC characteristics, for maximum current supply requirements.

2.18 Don’t use (DU)

This pin should not be used as it is internally connected. Its voltage level can be between V SS and VDDQ or leave it unconnected.

2.19 Not connected (NC)

This pin is not physically connected to the device.

Bus operations M58BW16F, M58BW32F

3 Bus operations

Each bus operations that controls the memory is described in this section, see tables 6 and 7 Bus operations, for a summary. The bus operation is selected through the Burst Configuration Register; the bits in this register are described at the end of this section. On power-up or after a hardware reset the memory defaults to Asynchronous Bus Read and Asynchronous Bus Write. No synchronous operation can be performed until the Burst Control Register has been configured. The Electronic Signature, Block Protection Configuration, CFI or Status Register will be read in asynchronous mode regardless of the Burst Control Register settings. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

3.1 Asynchronous Bus operations

For asynchronous bus operations refer to Table 6 together with the following text. The read access will start at whichever of the three following events occurs last: valid address transition, Chip Enable, E, going Low, VIL or Latch Enable, L, going Low, VIL.

3.1.1 Asynchronous Bus Read

Asynchronous Bus Read operations read from the memory cells, or specific registers (Electronic Signature, Block Protection Configuration Register, Status Register, CFI and Burst Configuration Register) in the command interface. A valid bus operation involves setting the desired address on the Address inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable and Output Disable High, VIH. The Data inputs/outputs will output the value, see Figure 7: Asynchronous Bus Read AC waveforms, and Table 19: Asynchronous Bus Read AC characteristics, for details of when the output becomes valid. Asynchronous Read is the default read mode which the device enters on power-up or on return from Reset/Power-down.

3.1.2 Asynchronous Latch Controlled Bus Read

Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific registers in the command interface. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. A valid bus operation involves setting the desired address on the Address inputs, setting Chip Enable and Latch Enable Low, V IL and keeping Write Enable High, VIH; the address is latched on the rising edge of Latch Enable. Once latched, the Address inputs can change. Set Output Enable Low, V IL, to read the data on the Data inputs/outputs; see Figure 8: Asynchronous Latch Controlled Bus Read AC waveforms and Table 19: Asynchronous Bus Read AC characteristics, for details on when the output becomes valid. Note that, since the Latch Enable input is transparent when set Low, VIL, Asynchronous Bus Read operations can be performed when the memory is configured for Asynchronous Latch Enable bus operations by holding Latch Enable Low, V IL throughout the bus operation.

M58BW16F, M58BW32F Bus operations

3.1.3 Asynchronous Page Read

Asynchronous Page Read operations are used to read from several addresses within the same memory page. Each memory page is 4 double-words and is addressed by the address inputs A0 and A1. Data is read internally and stored in the page buffer. Valid bus operations are the same as Asynchronous Bus Read operations but with different timings. The first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. If the page changes then the normal, longer timings apply again. Page Read does not support Latched Controlled Read. See Figure 11: Asynchronous Page Read AC waveforms, and Table 20: Asynchronous Page Read AC characteristics, for details on when the outputs become valid.

3.1.4 Asynchronous Bus Write

Asynchronous Bus Write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don’t care during Bus Write operations. A valid Asynchronous Bus Write operation begins by setting the desired address on the Address inputs, and setting Chip Enable, Write Enable and Latch Enable Low, V IL, and Output Enable High, VIH, or Output Disable Low, VIL. The Address inputs are latched by the command interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Commands and input data are latched on the rising edge of Chip Enable, E , or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation. See Figure 12: Asynchronous Write AC waveforms, and Table 21: Asynchronous Write and Latch controlled Write AC characteristics, for details of the timing requirements.

3.1.5 Asynchronous Latch Controlled Bus Write

Asynchronous Latch Controlled Bus Write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is Don’t care during Bus Write operations. A valid Asynchronous Latch Controlled Bus Write operation begins by setting the desired address on the Address inputs and pulsing Latch Enable Low, V IL. The Address inputs are latched by the command interface on the rising edge of Latch Enable, Write Enable or Chip Enable, whichever occurs first. Commands and input data are latched on the rising edge of Chip Enable, E , or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation. See Figure 13: Asynchronous Latch controlled Write AC waveforms, and Table 21: Asynchronous Write and Latch controlled Write AC characteristics, for details of the timing requirements.

3.1.6 Output Disable

The data outputs are high impedance when the Output Enable, G, is at VIH or Output Disable, GD, is at VIL.

3.1.7 Standby

Write Enable or Output Disable inputs. Configuration Register to ‘1’ (see Table 18: DC characteristics).

3.1.8 Reset/Power-down

Table 6. Asynchronous Bus operations (1)

1. Data, Manufacturer code, Device code, Burst Configurati on Register, Standby Status and Block Protection Configuration

Register are read using the Asynchronous Bus Read command.

M58BW16F, M58BW32F Bus operations

3.2 Synchronous Bus operations

For Synchronous Bus Operations refer to Table 7 together with the following text. The read access will start at whichever of the three following events occurs last: valid address transition, Chip Enable, E, going Low, VIL or Latch Enable, L, going Low, VIL.

3.2.1 Synchronous Burst Read

Synchronous Burst Read operations are used to read from the memory at specific times synchronized to an external reference clock. The valid edge of the Clock signal is the rising edge. Once the Flash memory is configured in Burst mode, it is mandatory to have an active clock signal since the switching of the output buffer databus is synchronized to the rising edge of the clock. In the absence of clock, no data is output. The burst type, length and latency can be configured. The different configurations for Synchronous Burst Read operations are described in the Burst Configuration Register section. Refer to Figure 4 for examples of Synchronous Burst operations. A valid Synchronous Burst Read operation begins when the Burst Clock is active and Chip Enable and Latch Enable are Low, V IL. The burst start address is latched and loaded into the internal Burst Address counter on the valid Burst Clock K edge or on the rising edge of Latch Enable, whichever occurs first. After an initial memory latency time, the memory outputs data each clock cycle. The Burst Address Advance B input controls the memory burst output. The second burst output is on the next clock valid edge after the Burst Address Advance B has been pulled Low. Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst Controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low on the rising clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if Burst Address Advance, B , is Low. Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid immediately at the rising clock edge. Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, VIH. If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid. If Output Enable, G, is at VIH or Output Disable, GD, is at VIL, but the Burst Address Advance, B, is at VIL the internal Burst Address counter is incremented at each Burst Clock K rising edge. The Synchronous Burst Read timing diagrams and AC characteristics are described in the AC and DC parameters section. See Figures 14, 17, 18 and 19, and Table 22.

3.2.2 Synchronous Burst Read Suspend

the data bus for other higher priority devices. Synchronous Burst Read operation can be resumed by setting Output Enable Low.

3.3 Burst Configuration Register

selection of the Burst length, Burst type, Burst X and Y latencies and the Read operation. Refer to Figure 4 for examples of Synchronous Burst configurations.

3.3.1 Read Select bit (M15)

asynchronous; when the Read Select bit is set to ’0’, Bus Read operations are synchronous. On reset or power-up the Read Select bit is set to’1’ for asynchronous accesses.

3.3.2 Standby Disable bit (M14)

‘1’, the device will not enter Standby mode when Chip Enable goes High, VIH. Table 7. Synchronous Burst Read Bus operations (1)

1. X = Don't care, V IL or VIH.
2. M15 = 0, Bit M15 is in the Burst Configuration Register.

M58BW16F, M58BW32F Bus operations

3.3.3 X-Latency bits (M13-M11)

The X-Latency bits are used during Synchronous Bus Read operations to set the number of clock edges between the address being latched and the edge where the first data become available. For correct operation the X-Latency bits can only assume the values in Table 8: Burst Configuration Register.

3.3.4 Y-Latency bit (M9)

The Y -Latency bit is used during Synchronous Bus Read operations to set the number of clock cycles between consecutive reads. The Y -Latency value depends on both the X- Latency value and the setting in M9. When the Y -Latency is 1 the data changes each clock cycle.

3.3.5 Valid Data Ready bit (M8)

The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When the Valid Data Ready bit is ’0’ the Valid Data Ready output pin is driven Low for the rising clock edge when invalid data is output on the bus.

3.3.6 Wrap Burst bit (M3)

Burst Read can be confined inside the 4 double-word boundary (wrap) or overcome the boundary (no wrap). When the wrap burst bit is set to '1' the burst read does not wrap. The wrap mode is not available (M3 is always ‘1’).

3.3.7 Burst Length bit (M2-M0)

The Burst Length bits set the maximum number of double-words that can be output during a Synchronous Burst Read operation. Burst lengths of 4 or 8 are available. Table 8: Burst Configuration Register gives the valid combinations of the Burst Length bits that the memory accepts. If a Burst Read operation (no wrap) has been initiated the device will output data synchronously. Depending on the starting address, the device activates the Valid Data Ready output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 double word boundary, the 8-double-word burst mode will run without activating the Valid Data Ready output. If the starting address is not aligned to a 4 double word boundary, Valid Data Ready is activated to indicate that the device needs an internal delay to read the successive words in the array. M10, M7 to M4 are reserved for future use.

Table 8. Burst Configuration Register

0 Synchronous Burst Read

1 Asynchronous Read (default at power-on)

0 Standby mode enabled (default at power-up)

1 Standby mode disabled

000 Reserved (default value)

111 Reserved

0 Reserved (default value)

1 Reserved

1 Two Burst Clock cycle

0 R valid Low during valid Burst Clock edge (default

1 R valid Low 1 data cycle before valid Burst Clock

1 Rising Burst Clock edge

00 Reserved (default value)

01 Reserved

10 Reserved

11 Reserved

0 Wrap (default value)

011 Reserved

100 Reserved

101 Reserved

110 Reserved

111 Continuous

1. X latencies can be calculated as: (t AVQV – tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. X is an integer
2. Y latencies can be calculated as: t KHQV + tSYSTEM MARGIN + tQVKH < Y tK.
3. The M6 bit is Don’t care in the M58BW32F and t he device has the Rising Burst Clock edge set. To

maintain the compatibility this could be modified and read. Table 8. Burst Configuration Register (continued)

Figure 4. Example burst configuration X-1-1-1 Table 9. Burst type definition

M58BW16F, M58BW32F Command interface

4 Command interface

All Bus Write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential Bus Write operations. The commands are summarized in Table 10: Commands. Refer to Table 10 in conjunction with the text descriptions below.

4.1 Read Memory Array command

The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent Read operations will output the addressed memory array data. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read commands will access the memory array.

4.2 Read Electronic Signature command

The Read Electronic Signature command is used to read the Manufacturer code, the Device code, the Block Protection Configuration Register and the Burst Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued, subsequent Bus Read operations, depending on the address specified, read the Manufacturer code, the Device code, the Block Protection Configuration or the Burst Configuration Register until another command is issued; see Table 11: Read electronic signature.

4.3 Read Query command

The Read Query command is used to read data from the common Flash interface (CFI) memory area. One Bus Write cycle is required to issue the Read Query command. Once the command is issued subsequent Bus Read operations, depending on the address specified, read from the common Flash interface memory area.

Command interface M58BW16F, M58BW32F

4.4 Read Status Register command

The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. The Status Register information is present on the output data bus (DQ0-DQ7) when Chip Enable E and Output Enable G are at VIL and Output Disable is at VIH. An interactive update of the Status Register bits is possible by toggling Output Enable or Output Disable. It is also possible during a Program or Erase operation, by de-activating the device with Chip Enable at V IH and then reactivating it with Chip Enable and Output Enable at VIL and Output Disable at VIH. The content of the Status Register may also be read at the completion of a Program, Erase or Suspend operation. During a Block Erase or Program command, DQ7 indicates the Program/Erase controller status. It is valid until the operation is completed or suspended. See the section on the Status Register and Table 13 for details on the definitions of the Status Register bits.

4.5 Clear Status Register command

The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent Bus Read operations continue to output the same data. The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new Program, Erase, Block Protect or Block Unprotect command is issued. If any error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command.

4.6 Block Erase command

The Block Erase command can be used to erase a block. It sets all of the bits in the block to ‘1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write operations are required to issue the command; the first write cycle sets up the Block Erase command, the second write cycle confirms the Block Erase command and latches the block address in the Program/Erase controller and starts the Program/Erase controller. The sequence is aborted if the Confirm command is not given and the device will output the Status Register Data with bits 4 and 5 set to '1'. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. If PEN is at V IH, the operation can be performed. If PEN goes below VIH, the operation aborts, the PEN Status bit in the Status Register is set to ‘1’ and the command must be re- issued. Typical Erase times are given in Table 12. See Appendix A, Figure 28: Block Erase flowchart and pseudocode, for a suggested flowchart on using the Block Erase command.

M58BW16F, M58BW32F Command interface

4.7 Erase All Main Blocks command

The Erase All Main Blocks command is used to erase all 63 main blocks, without affecting the parameter blocks. Issuing the Erase All Main Blocks command sets every bit in each main block to '1'. All data previously stored in the main blocks are lost. Two Bus Write cycles are required to issue the Erase All Main Blocks command. The first cycle sets up the command, the second cycle confirms the command and starts the Program/Erase controller. If the Confirm command is not given the sequence is aborted, and Status Register bits 4 and 5 are set to '1'. If the address given in the second cycle is located in a protected block, the Erase All Main Blocks operation aborts. The data remains unchanged in all blocks and the Status Register outputs the error. Once the Erase All Main Blocks command has been issued, subsequent Bus Read operations output the Status Register. See the Status Register section for details. During an Erase All Main Blocks operation, only the Read Status Register command is accepted by the memory; any other command are ignored. Erase All Main Blocks, once started, cannot be suspended. If PEN is at V IH, the operation will be performed. If PEN is lower than VIH the operation aborts and the Status Register PEN bit (bit 3) is set to '1'.

4.8 Program command

The Program command is used to program the memory array. Two Bus Write operations are required to issue the command; the first write cycle sets up the Program command, the second write cycle latches the address and data to be programmed and starts the Program/Erase controller. A program operation can be aborted by writing FFFFFFFFh to any address after the program set-up command has been given. The Program command is also used to program the OTP block. Refer to Table 10: Commands, for details of the address. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. If Reset/Power-down, RP , falls to VIL during programming the operation will be aborted. If PEN is at VIH, the operation can be performed. If PEN goes below VIH, the operation aborts, the PEN Status bit in the Status Register is set to ‘1’ and the command must be re- issued. See Appendix A, Figure 26: Program flowchart and pseudocode, for a suggested flowchart on using the Program command.

Command interface M58BW16F, M58BW32F

4.9 Write to Buffer and Program command

The Write to Buffer and Program command makes use of the device’s double word (32 bit) Write Buffer to speed up programming. Up to eight double words can be loaded into the Write Buffer and programmed into the memory. Four successive steps are required to issue the command. 1. One Bus Write operation is required to set up the Write to Buffer and Program command. Any Bus Read operations will start to output the Status Register after the 1st cycle. 2. Use one Bus Write operation to write the selected memory block address (any address in the block where the values will be programmed can be used) along with the value N on the Data inputs/outputs, where N+1 is the number of words to be programmed. The maximum value of N+1 is 8 words. 3. Use N+1 Bus Write operations to load the address and data for each word into the write buffer. The address must be between Start address and Start address plus N, where Start address is the first word address. 4. Finally, use one Bus Write operation to issue the final cycle to confirm the command and start the Program operation. If any address is outside the block boundaries or if the correct sequence is not followed, Status Register bits 4 and 5 are set to ‘1’ and the operation will abort without affecting the data in the memory array. A protected block must be unprotected using the Blocks Unprotect command. During a Write to Buffer and Program operation the memory will only accept the Read Status Register and the Program/Erase Suspend commands. All other commands are ignored. If PEN is at V IH, the operation will be performed. If PEN is lower than VIH the operation aborts and the Status Register PEN bit (bit 3) is set to '1'. The Status Register should be cleared before re-issuing the command.

M58BW16F, M58BW32F Command interface

4.10 Program/Erase Suspend command

The Program/Erase Suspend command is used to pause a Program or Erase operation. The command will only be accepted during a Program or Erase operation. It can be issued at any time during a Program or Erase operation. The command is ignored if the device is already in suspend mode. One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the Program/Erase controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase controller has paused; no other commands will be accepted until the Program/Erase controller has paused. After the Program/Erase controller has paused, the memory will continue to output the Status Register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing it is possible for the operation to complete. Once the Program/Erase Controller Status bit (bit 7) indicates that the Program/Erase controller is no longer active, the Program Suspend Status bit (bit 2) or the Erase Suspend Status bit (bit 6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase controller pausing see Table 12. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Resume commands will be accepted by the command interface. Additionally, if the suspended operation was Erase then the Program, the Write to Buffer and Program, the Set/Clear Block Protection Configuration Register and the Program Suspend commands will also be accepted. When a program operation is completed inside a Block Erase Suspend the Read Memory Array command must be issued to reset the device in Read mode, then the Erase Resume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. Erase operations can be suspended in a systematic and periodical way, however, in order to ensure the effectiveness of erase operations and avoid infinite erase times, it is imperative to wait a minimum time between successive Erase Resume and Erase Suspend commands. This time, called the minimum effective erase time, is given in Table 12 on page 40. See Appendix A, Figure 27: Program Suspend & Resume flowchart and pseudocode, and Figure 29: Erase Suspend & Resume flowchart and pseudocode, for suggested flowcharts on using the Program/Erase Suspend command.

4.11 Program/Erase Resume command

The Program/Erase Resume command can be used to restart the Program/Erase controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. See Appendix A, Figure 27: Program Suspend & Resume flowchart and pseudocode, and Figure 29: Erase Suspend & Resume flowchart and pseudocode, for suggested flowcharts on using the Program/Erase Suspend command.

Command interface M58BW16F, M58BW32F

4.12 Set Burst Configurat ion Register command

The Set Burst Configuration Register command is used to write a new value to the Burst Configuration Register which defines the burst length, type, X and Y latencies, Synchronous/Asynchronous Read mode. Two Bus Write cycles are required to issue the Set Burst Configuration Register command. The first cycle writes the setup command. The second cycle writes the address where the new Burst Configuration Register content is to be written, and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to ‘1’. Once the command is issued the memory returns to Read mode as if a Read Memory Array command had been issued. The value for the Burst Configuration Register is always presented on A0-A15. M0 is on A0, M1 on A1, etc.; the other address bits are ignored.

4.13 Set Block Protection Configuration Register command

The Set Block Protection Configuration Register command is used to configure the Block Protection Configuration Register to ‘protected’, for a specific block. Protected blocks are fully protected from program or erase when WP pin is Low, VIL. The status of a protected block can be changed to ‘unprotected’ by using the Clear Block Protection Configuration Register command. At power-up, all block are configured as ‘protected’. Two bus operations are required to issue a Set Block Protection Configuration Register command:

• The first cycle writes the setup command
• The second write cycle specifies the address of the block to protect and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to ‘1’. To protect multiple blocks, the Set Block Protection Configuration Register command must be repeated for each block. Any attempt to re-protect a block already protected does not change its status.

4.14 Clear Block Protection Configuration Register command

The Clear Block Protection Configuration Register command is used to configure the Block Protection Configuration Register to ‘unprotected’, for a specific block thus allowing program/erase operations to this block, regardless of the WP pin status. Two bus operations are required to issue a Clear Block Protection Configuration Register command:

• The first cycle writes the setup command
• The second write cycle specifies the address of the block to unprotect and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to ‘1’. To unprotect multiple blocks, the Clear Block Protection Configuration Register command must be repeated for each block. Any attempt to unprotect a block already unprotected does not affect its status.

Table 10. Commands (1)

1. X Don’t care; RA Read Address, RD Read Data, ID Device Code, IDA Identifier Address, IDD Identifier Data, SRD Status

BCR Burst Configuration Register value, N+1 number of Words to program, BA Block address.

1. The Manufacturer code, the Device code, the Burst Configurat ion Register, and the Block Protection Configuration Register

of each block are read using the Read Electronic Signature command.

Table 11. Read electronic signature

1. BCR = Burst Configuration Register.
2. SBA is the start address of each block.

Table 12. Program, Erase times and endurance cycles (1)

512 Kbit Block Erase 1 2 1 2 s

1. The minimum effective erase time is defined as the minimum time required between the last Erase

controller to be able to execute its algorithm.

M58BW16F, M58BW32F Status Register

5 Status Register

The Status Register provides information on the current or previous Program, Erase or Block Protect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Program/Erase Resume commands. The Status Register can be read from any address. The contents of the Status Register can be updated during an erase or program operation by toggling the Output Enable or Output Disable pins or by de-activating (Chip Enable, V IH) and then reactivating (Chip Enable and Output Enable, VIL, and Output Disable, VIH.) the device. The Status Register bits are summarized in Table 13: Status Register bits. Refer to Table 13 in conjunction with the following text descriptions.

5.1 Program/Erase Controller Status (bit 7)

The Program/Erase Controller Status bit indicates whether the Program/Erase controller is active or inactive. When the Program/Erase Controller Status bit is set to ‘0’, the Program/Erase controller is active; when bit 7 is set to ‘1’, the Program/Erase controller is inactive. The Program/Erase Controller Status is set to ‘0’ immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is set to ‘1’. During Program and Erase operations the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase controller completes the operation and the bit is set to ‘1’. After the Program/Erase controller completes its operation the Erase Status (bit 5), Program Status (bit 4) bits should be tested for errors.

5.2 Erase Suspend Status (bit 6)

The Erase Suspend Status bit indicates that an Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to ‘1’ (Program/Erase controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is set to ‘0’, the Program/Erase controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to ‘0’.

Status Register M58BW16F, M58BW32F

5.3 Erase Status (bit 5)

The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase controller inactive). When the Erase Status bit is set to ‘0’, the memory has successfully verified that the block has erased correctly. When the Erase Status bit is set to ‘1’, the Program/Erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. Once set to ‘1’, the Erase Status bit can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

5.4 Program/Write to Buffer and Program Status (bit 4)

The Program/Write to Buffer and Program Status bit is used to identify a Program failure or a Write to Buffer and Program failure. Bit 4 should be read once the Program/Erase Controller Status bit is High (Program/Erase controller inactive). When bit 4 is set to ‘0’ the memory has successfully verified that the device has programmed correctly. When bit 4 is set to ‘1’ the device has failed to verify that the data has been programmed correctly. Once set to ‘1’, the Program Status bit can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

5.5 PEN Status (bit 3)

The PEN Status bit can be used to identify if a Program or Erase operation has been attempted when PEN is Low, VIL. When bit 3 is set to ‘0’ no Program or Erase operations have been attempted with PEN Low, VIL, since the last Clear Status Register command, or hardware reset. When bit 3 is set to ‘1’ a Program or Erase operation has been attempted with PEN Low, VIL. Once set to ‘1’, bit 3 can only be reset by a Clear Status Register command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

M58BW16F, M58BW32F Status Register

5.6 Program Suspend Status (bit 2)

The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is set to ‘0’, the Program/Erase controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to ‘0’.

5.7 Block Protection Status (bit 1)

The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is set to ‘0’, no Program or Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is set to ‘1’, a Program or Erase operation has been attempted on a protected block. Once set to ‘1’, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

5.8 Bit 0

Reserved bit (set to ‘1’).

Table 13. Status Register bits

7 Program/Erase Controller Status

6 Erase Suspend Status

5 Erase Status

4 Program Status,

3 PEN Status bit

2 Program Suspend Status

1 Erase/Program in a protected

0 Reserved ’1’ Reserved

6 Maximum rating

and other relevant quality documents. Table 14. Absolute maximum ratings Table 15. Data retention

0 V 20 7 Y ears

2.5 V – 25 Y ears

2.7 V – 15 Y ears

7 DC and AC parameters

Figure 5. AC measurement input/output waveform Figure 6. AC measurement load circuit Table 16. Operating and AC measurement conditions

Table 17. Device capacitance (1)(2)

1. Sampled only, not 100% tested.

Table 18. DC characteristics

1. I DDP-UP is the current needed from the device until RP goes to its logic high level when the power supply is

stable (tVDHPH). See Figure 22and Figure 23.

1. The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst Configuration

Table 19. Asynchronous Bus Read AC characteristics

1. Output Enable G may be delayed up to tELQV - tGLQV after the falling edge of Chip Enable E without

Figure 11. Asynchronous Page Read AC waveforms Table 20. Asynchronous Page Read AC characteristics (1)

1. For other timings see Table 19: Asynchronous Bus Read AC characteristics.

Figure 12. Asynchronous Write AC waveforms

Figure 13. Asynchronous Latch controlled Write AC waveforms

Table 21. Asynchronous Write and Latch controlled Write AC characteristics

Figure 14. Synchronous Burst Read, Latch Enable controlled (data valid from ’n’ Note: n depends on Burst X-Latency.

Figure 15. Synchronous Burst Read, Chip Enable controlled (data valid from ’n’ Note: n depends on Burst X-Latency.

Figure 16. Synchronous Burst Read, Valid Address transition controlled (data valid Note: n depends on Burst X-Latency.

Table 22. Synchronous Burst Read AC characteristics (1)(2)

1. Data output should be read on the valid clock edge.
2. For other timings see Table 19: Asynchronous Bus Read AC characteristics.

Figure 21. Power supply slope specification

1. Please refer to the application note AN2601.

Table 23. Power supply AC and DC characteristics

1. This threshold is 90% of the minimum value allowed to V DD.

Table 24. Reset, Power-down and Power-up AC characteristics

1. This time is t PHEL + tAVQV or tPHEL + tELQV.

8 Package mechanical

Figure 24. LBGA80 10 × 12 mm - 8 × 10 ball array, 1 mm pitch, bottom view package

Figure 25. PQFP80 - 80 lead plastic quad flat pack, package outline Table 26. PQFP80 - 80 lead plastic quad flat pack, package mechanical data

9 Ordering information

Devices are shipped from the factory with the memory content bits erased to ’1’. of this device, please contact the Numonyx Sales Office nearest to you. Table 27. Ordering information scheme

1. Qualified & characterized according to AEC Q100 & Q003 or equivalent, advanced screening

according to AEC Q001 & Q002 or equivalent.

Figure 26. Program flowchart and pseudocode

1. If an error is found, the Status Register must be cleared before further P/E operations.

Figure 27. Program Suspend & Resume flowchart and pseudocode

Figure 28. Block Erase flowchart and pseudocode

1. If an error is found, the Status Register must be cleared before further Program/Erase operations.

Figure 29. Erase Suspend & Resume flowchart and pseudocode (as if the Program/Erase Suspend was not issued).

Figure 30. Power-up sequence followed by Synchronous Burst Read

Figure 31. Command interface and Program/Erase controller flowchart (a)

Figure 32. Command interface and Program/Erase controller flowchart (b)

Figure 33. Command interface and Program/Erase controller flowchart (c)

Figure 34. Command interface and Program/Erase controller flowchart (d)

Figure 35. Command interface and Program/Erase controller flowchart (e)

software to upgrade itself when necessary. show the addresses used to retrieve the data. Table 28. Query structure overview

1. Offset 15h defines P which points to the pr imary algorithm extended query address table.
2. Offset 19h defines A which points to the al ternate algorithm extended query address table.

Table 29. CFI - Query address and data output (1)(2)

1. The x 8 or byte address and the x 16 or word address mode are not available.
2. Query data are always presented on DQ7-DQ0. DQ31-DQ8 are set to '0'.

Table 30. CFI - device voltage and timing specification

1. Bits are coded in binary code decimal, bit7 to bi t4 are scaled in Volts and bit3 to bit0 in mV.

Table 31. M58BW16F device geometry definition 29h 00h Organization sync./async. Async.

Table 32. M58BW16F extended query information

Table 33. M58BW32F device geometry definition 29h 00h Organization sync./async. Async.

Table 34. M58BW32F extended query information

Table 35. Protection register information

M58BW16F, M58BW32F Block protection Appendix C Block protection OTP protection The OTP protection is an user-enabled feature that permanently protects specific blocks, so called “OTP blocks”, against modify operations (program/erase). It is available:

• on one specific 128-kbit parameter block in the M58BW32F- block 1 (01000h-01FFFh) for bottom devices or block 72 (FE000h-FEFFFh) for top devices
• on two specific 64-kbit parameter blocks in the M58BW16F- block 2 and 3 (01000h- 01FFFh) for bottom devices or block 36 and 35 (7E000h-7EFFFh) for top devices. The default state is unprotected. However, once the protection has been enabled, it is impossible to disable it and the OTP blocks will remain “modify protected” for ever. Obviously, this information is stored in internal non volatile registers. Activation sequence If the user wants to make the OTP protection effective on a part, he has to issue the Lock OTP protection command. The Lock OTP protection requires 2 write cycles:
• write (ADD=000AAh, DATA=49h) - Lock OTP Protection command 1
• write (ADD=00003h, DATA=0000 0000h) - Lock OTP Protection command 2 This sequence of commands has to be given with the Tuning Protection unlocked (if this protection is enabled on the part) and with Write Protect Enable WP_N=’1’. The user can check its execution polling on the SR in the same way as a normal Program Word command. The program duration lasts about 35 µs like for a standard Program Word command. It is also possible to detect the end of the operation by polling the Status Register. Any Erase attempt returns A3h in the Status Register while any Program attempt returns 93h. Once the first write cycle of the Lock OTP protection command is issued, a wrong address on second write cycle will cause the activation sequence to fail. The Status Register allows detecting this event and its value is then B1h (invalid sequence). As a consequence, the protection is not active and the sequence must be restarted. The Lock OTP Protection command cannot be suspended.

Table 36. Document revision history 09-Jun-2006 1 Initial release. Table 9: Burst type definition). Notes removed below Table 8. controlled Write AC characteristics. IDD max modified and IDD4 added to Table 18: DC characteristics. Program, Erase times and endurance cycles. geometry definition updated. Synchronous Burst Read AC characteristics. Table 24: Reset, Power-down and Power-up AC characteristics. tPLRH removed from Table 24. Protection register information added. Section 2.7: Reset/Power-down (RP). Power supply AC and DC characteristics. 19-Mar-2008 5 Applied Numonyx branding.