M58BF008 STMICROELECTRONICS | Alldatasheet
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Technical content
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M58BF008
8 Mbit (256Kb x32, Burst) Flash Memory
–V DD = 5V Supply Voltage –V DDQ = 3.3V Input/Output Supply Voltage – Optional VPP = 12V for fast Program and Erase n CONFIGURABLE OPTIONS – Synchronous or Asynchronous write mode – Burst Wrap/No-wrap default – Critical Word X (3 or 4) and Burst Word Y (1 or 2) latency times n ACCESS TIME – Synchronous X-Y-Y-Y Burst Read up to 40MHz – Asynchronous Read: 100ns n PROGRAMMING TIME: 10 µs typical n MEMORY BLOCKS – 32 equal Main blocks of 256 Kbit – One Overlay block of 256 Kbit n ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: F0h – Version Code: 0-7h
DESCRIPTION
The M58BF008 is a family of 8 Mbit non-volatile Flash memories that can be erased electrically at the block level and programmed in-system. Family members are configured during product testing for a specific Synchronous or Asynchronous Write mode, a Burst default of Wrap or No-wrap and for Critical Word X = 3 or 4 and Burst Word Y = 1 or 2 latency times. The Main memory array matrix al- lows each of the 32 equal blocks of 256 Kbit to be erased separately and re-programmed without af- fecting other blocks. The memory features a
256 Kbit Overlay block having the same address
space asthe first Main memory block. The Overlay block provides a secure storage area that is con- trolled by special Instructions and an external in- put. A separate supply V DDQ allows the Input/ Output signals to be at 3.3V levels, while the main supply VDD is 5V. Figure 1. Logic Diagram
Figure 2. LBGA Connections (Top view through package)
Figure 3. PQFP Connections
and LBGA80 1.0mm ball pitch packages. Table 1. Signal Names Note: 1. Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device.
mands to the Command Interface. controlled by Burst Address Advance BAA. A17 is the MSB and A0 the LSB. IH or for a write operation when it is at VIL. impedance when System Reset RP is at VIL. Table 3. Block Addresses
System Clock (CLK).All synchronous signals are input and output relative to the System Clock. Synchronous input signals must respect the set- up and hold times relative to the System Clock ris- ing edge. Reset/Power-down (RP).The Reset/Power- down RP input provides a hardware reset for the memory. When Reset/Power-down RP is at V IL the memory is reset and in the Power-down mode. In this mode the outputs are high impedance and the current consumption is minimised. When Re- set/Power-down RP is at V IH the memory is in the normal operating mode. When leaving the Power- down mode the memory enters the Asynchronous Read Array mode. Reset/Power-down has a weak pull-up resistor to V DDQ and will assume a high level if not connect- ed. Chip Enable (E).When the Chip Enable E input is at VILit activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable E is at VIH the memory is deselected and the power consumption is reduced to the standby level. Output Enable (G).Output Enable G controls the data output buffers. In the Asynchronous mode data is output when Output Enable G is at VIL.I n the Synchronous mode, Output Enable G is sam- pled on the rising edge of the System Clock CLK. If Output Enable E is at VIL then valid output data on DQ0-DQ31 can be read at the next rising edge of the System Clock CLK. Output Disable (GD).In the Asynchronous mode the data outputs DQ0-DQ31 are high imped- ance when Output Disable GD is at V IL, irrespec- tive of the state of Output Enable G. In Synchronous mode Output Disable GD is sam- pled, together with Output Enable G, on the rising edge of the System Clock CLK. If Output Disable is at VILthen the data outputs DQ0-DQ31 are high impedance at the next rising edge of the System Clock CLK, irrespective of the state of Output En- able G. Output Disable has a weak pull-up resistor to VDDQ and will assume a high level if not externally connected. Write Enable (W).The Write Enable W input controls the writing of commands or input data. In the Asynchronous mode commands or data are written when Chip Enable E and Write Enable W are at V IL. In the Synchronous mode with Chip En- able E at VIL, input data is sampled if Write Enable Wi sa tVILon the rising edge of the System Clock CLK. Load Burst Address (LBA).In the Asynchro- nous mode Load Burst Address LBA is Don’t Care (but if it falls during an asynchronous read then a new read cycle is started). In the Synchronous mode Load Burst Address LBA enables latching of the burst starting address for Synchronous read or write. The address is latched on the rising edge of the System Clock CLK if Load Burst Address LBA is at V IL. Write/Read (WR).Write/Read WR is used in Synchronous mode to control write or read opera- tions. If Load Burst Address LBA is at V IL and Write/Read is at VIL then the rising edge of the System Clock CLK latches a write address. If Write/Read is at VIH then a read address is latched. Write/Read has a weak pull-up resistor to VDDQ and will assume a high level if not externally con- nected. Burst Address Advance (BAA).When Burst Address Advance BAA is at VIL, the rising edge of the System Clock CLK advances the burst ad- dress. When Burst Address Advance BAA is at VIH the advance is suspended. VDD Supply Voltage.The supply VDD provides the power to the internal circuits of the memory. The VDD supply voltage is 4.5 to 5.5V. VDDQ Input/Output Supply Voltage.The Input/ Output supply VDDQ provides the power for the in- put/outputs of the memory, independent from the supply V DD . The Input/Output supply VDDQ may be connected to the VDD supply or it can use a separate supply of 3.0 to 3.6V. VPP Program/Erase Supply Voltage.The Pro- gram/Erase supply VPP is used for programming and erase operations. The memory normally exe- cutes program and erase operations at the supply V PP1 voltage levels. In a manufacturing environment, programming may be speeded up by applying a higher VPPH lev- el to the VPP Program/Erase Supply. This is not in- tended for extended use. The VPPH supply may be applied for a total of 80 hours maximum and during program and erase for a maximum of 1000 cycles. Stressing the device beyond these limits could damage the device. When V PP Program/Erase supply is at VSS all blocks are protected from programming or erase. Leaving V PP floating is equivalent to connecting it to VSS due to an internal pull-down circuit. Ground (VSS and VSSQ ).The Ground VSS is the reference for the internal supply voltage VDD .T h e Ground VSSQ is the reference for the Input/Output supply VDDQ .
the previous Instruction given to the memory. edge will start a new read cycle. Table 4. Bus Operations Note: 1. See Device Operations, Instructions and Commands, sections for more details. Table 5. Read Electronic Signature Note: ”x” = version level. The first version is ”0” and it can have a value up to ”7”.
– Synchronous Single Read.To read a single data Double-Word in Synchronous mode Chip Enable E must be Low. Load Burst Address LBA must be Low for one System Clock CLK ris- ing edge with Write/Read WR High. This latches the read address, after which the address bus inputs are Don’t Care. The Output Enable G is Low for a single System Clock CLK cycle. The Double-Word of valid data is output on the next System Clock CLK rising edge. – Synchronous Burst Read.To read a burst of four Double-Words in Synchronous mode Chip Enable /E must be Low. Load Burst Address LBA must be Low for one System Clock CLK ris- ing edge with Write/Read WR High. This latches the first address of the burst sequence, after which the address bus inputs are Don’t Care. The Output Enable G is driven Low before the burst output sequence. Four Double-Words of data are output on the subsequent System Clock CLK rising edges if Burst Address Ad- vance BAA is maintained Low. The address ad- vance for synchronous burst read is suspended if Burst Address Advance BAA goes High and the output data remains constant. The data bus will go high impedance on the rising edge of the System Clock CLK after Output Enable G goes High. The burst timing depends on the device config- uration for the Critical Word X and Burst Word Y latency times and the choice of wrap or no-wrap for burst addresses. The operation burst wrap is shown in Table 13. The wrap sequence uses only the address bits A0 and A1 and does not repeat after the last Double-Word has been out- put. Read Overlay Block.The Overlay block can be read, as for a Main block, after it has been en- abled. To enable the Overlay block the Overlay Block Enable bit OBEB and the Overlay Block Sta- tus bit OBS in the Status Register must be set to ’1’ - see Table 9. The Overlay Block Enable bit OBEB can be set to ’1’ in three ways - see Table 10: – By Toggling the Reset/Power-Down signal RP with the V PP Program/Erase supply in the range VPP1 or VPPH .V PP out of range will reset the OBEB bit to ’0’. – By a leaving power-on reset with VPP Program/ Erase supply in the range VPP1 or VPPH .VPP out of range will reset the OBEB bit to ’0’. – By giving the Overlay Block Enable/Disable for Read Instruction OBT. The Overlay Block Status bit OBS monitors the VPP Program/Erase supply and will be set to ’1’ when in the range VPP1 or VPPH . The Overlay block is enabled with OBEB at ’1’ but will not be read unless OBS status bit is also at ’1’. If it is not then a read operation will read the contents of the Main block at the same address. When the Overlay block is enabled for reading, only this one block of 256 Kbit is accesible and none of the other Main blocks may be accessed, the address signals A13-A17 are Don’t Care. Read Electronic Signature.The memory con- tains three Electronic Signature codes identifying the manufacturer, device and version, which can be read after giving the Instruction RSIG. The manufacturer code 00000020h is read when the address inputs A0 and A1 are at VIL. The device code 000000F0h is read when A0 is at VIH and A1 is at VIL. The version code 0000000xh is read when A0 is at VILand A1 is at VIH. The codes are read on DQ0-DQ31, all other address signal inputs are Don’t Care. See Table 5. Write.Write operations are used to give com- mands to the memory that latch input data and ad- dresses to program or block addresses to erase. – Asynchronous Write.To write data in the Asynchronous mode the address inputs must be stable and Chip Enable E must be Low dur- ing the write cycle. Write W must be Low and in- put data valid on the rising edge is Write W. – Synchronous Write.To write input data in Synchronous mode Chip Enable E must be Low. Load Burst Address LBA must be Low for one System Clock CLK rising edge with Write/ Read WR Low. This latches the write address, after which the address bus inputs are Don’t Care. When Write Enable W is Low input data is latched on the next System Clock CLK rising edge. Output Disable.The data outputs are high im- pedance when the Output Enable G is High or when the Output Disable GD is Low, independent of the level on Output Enable G. Standby. The memory is in standby when the P/ E.C. is not running, the memory is in read mode and Chip Enable E is High. The power consump- tion is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. If Chip Enable goes High during a program or erase operation the device enters the standby mode when the internal algorithm has finished. Reset/Power-down. During power-down all in- ternal circuits are switched off, the memory is de- selected and the outputs are high impedance. The memory is in Power-down mode when Reset/Pow- er-down RP is Low. The power consumption is re- duced to the power-down level, independent of the Chip Enable E, Load Burst Address LBA, Output Enable G or Write Enable W inputs. If Reset/Power-down RP is pulled Low during a program or erase operation this is aborted and the memory content is no longer valid.
Table 6. Commands that toggle a mode or function. ation and exit status of the internal algorithms. bit VPP Status VPPS will be set to ’1’.
Table 7. Instructions lay memory block if it is enabled. a program or erase operation in progress.
Table 8. Status Register Bits P/ECS and PESS bits are set to ‘1’. Either ES bit or PS bit is set to ‘1’. until Erase Resume instruction is given. erasing the block to all ’1’s. it falls out of the ranges during erase execution. to clear the Status Register bits. Erase (EE) instruction of the Main memory array. to clear the Status Register bits.
Program (PG).The Program instruction consists of two write cycles, the first is the program set-up command 40h at the address 00000h. This is fol- lowed by a second write cycle to latch the address and data to be programmed. This second com- mand starts the P/E.C. A program operation can be aborted by writing FFFFFFFFh to any address after the program set-up command has been giv- en. While programming is in progress only the Read Status Register and Program Suspend in- structions are valid. Read operations output the Status Register after the program operation has started. The Status Register bit 7 is ’0’ while programming is in progress and is set to ’1’ when it is completed. Af- ter completion the Status Register bit 4 is set to ’1’ if there has been a programming failure. Programming should not be attempted when the V PP Program/Erase Supply Voltage is out of the range VPP1 or VPPH as the results will be uncer- tain. The Status Register bit 3 is set to ’1’ if VPP is not within the allowed ranges when programming is attempted or if it falls out of the ranges during program execution. The program operation aborts if V PP drops out of the allowed ranges or if Reset/Power-Down RP falls to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the mem- ory block must be erased and programming re- peated. A Clear Status Register instruction must be given to clear the Status Register bits. Overlay Block Program (OBPG).The Overlay Block Program instruction consists of two write cy- cles, the first is the program set-up command 04h at the address 00000h. This is followed by a sec- ond write cycle to latch the address and data to be programmed. This second command starts the P/ E.C. The operation is executed as described for the Program (PG) instruction of the Main memory ar- ray. While programming of the Overlay block in progress only the Read Status Register instruction is valid. Program/Erase Suspend (PES).As memory erasure takes of the order of seconds to complete and programming a few microseconds, a Pro- gram/Erase Suspend instruction is implemented. Program/Erase Suspend interrupts the operations to allow reading or programming in a block other than one in which program or erase is suspended. A Program/Erase Suspend instruction is accepted only during a Program or Erase instruction. When the Program/Erase Suspend command is written to the Command Interface, the P/E.C. freezes the program or erase operation. The suspended pro- gram or erase operation may be restarted by using the Program/Erase Resume instruction. Program/ Erase Suspend is not allowed during the Overlay block program/erase operation and the command is ignored. The Program/Erase Suspend instruction consists of one write cycle giving the command B0h at the address 00000h. If a program operation is in progress when the in- struction is given, the Status Register bits 4 and 6 are set to ’1’ after it has been suspended. If an erase operation is in progress when the instruction is given, the Status Register bits 5 and 6 are set to ’1’ after it has been suspended. The valid instructions that may be given to the memory while programing is suspended are – Read Memory Array (RD) – Read Status Register (RSR) – Read Electronic Signature (RSIG) – Program/Erase Resume (PER) In addition, while erasure is suspended, the Pro- gram (PG) instruction may be given. In Program/Erase Suspend mode the memory can be placed in a pseudo-standby mode by taking Chip Enable /E to VIH to reduce power consump- tion. Program/Erase Resume (PER).If a Program/ Erase Suspend instruction has previously been executed, then the operation may be resumed by giving the command D0h at the address 00000h. The Status Register bits 4, 5 and 6 are cleared when program or erase resumes. A Read Memory Array instruction will output the Status Register af- ter program or erase is resumed. Suggested flow charts for software that uses pro- gramming, erasure and program/erase suspend/ resume operations are shown in Figures 11, 12, 13 and 14. Asynchronous/Synchronous Read Toggle (ART). Asynchronous Read Memory Array is the memory default at power-up or when returning from Power- Down. To read data in Synchronous mode, either single or burst, the Asynchronous/Synchronous Read Toggle instruction must be used. The Asynchronous/Synchronous Read Toggle in- struction consists of one write cycle giving the command 60h at the address 00000h. Two con- secutive instructions are not recognised and an- other Instruction, for example the Read Memory Array, must be given before another Asynchro- nous/Synchronous Read Toggle will be recogn- ised.
to toggle the burst wrap operation. consecutive instructions are not recognised. Table 9. Read Access to Overlay Block or Main Block Table 10. Overlay Block Enable/Disable Bit (OBEB) Note: 1. Toggle H-L-H for tPLPH minimum.
1 In the range VPP1 or VPPH 1 Overlay Block
1 Out of the range
0 Main Block
0 X 0 Main Block
1 Unknown Not guaranteed Unknown
sets the default for the write and burst interface. chronous Read Toggle Instruction. using the Wrap/No-wrap Burst Toggle Instruction. Critical Word and Burst Word Latency Times. A burst sequence is described as X-Y-Y-Y. Table 11. Configuration Table 12. Wrap/No-wrap Burst Sequence
00 Double-Word 0 ⇒ 1 ⇒ 2 ⇒ 3 Double-Word 0 ⇒ 1 ⇒ 2 ⇒ 3
01 Double-Word 1 ⇒ 2 ⇒ 3 ⇒ 0 Double-Word 1 ⇒ 2 ⇒ 3
10 Double-Word 2 ⇒ 3 ⇒ 0 ⇒ 1 Double-Word 2 ⇒ 3
11 Double-Word 3 ⇒ 0 ⇒ 1 ⇒ 2 Double-Word 3
tics tables show the current consumption figures. Erase Supply Voltage can be applied in any order. Enable W or Write/Read WR to VIH.
Table 15. DC Characteristics
Table 16. Asynchronous Read AC Characteristics(1) Note: 1. See AC Testing Measurements Conditions for timing measurements.
- Sampled only, not 100% tested.
- G may be delayed up to tELQV -tGLQV after falling edge of E without increasing tELQV .
Figure 6. Asynchronous Read AC Waveforms
Table 17. Synchronous Read AC Characteristics(1) Note: 1. See AC Testing Measurement Conditions for timing measurements.
- Sampled only, not 100% tested.
Figure 7. Synchronous Single Read AC Waveforms
Figure 8. Synchronous Burst Read AC Waveforms
Table 18. Asynchronous Write AC Characteristics(1) Note: 1. See AC Testing Measurement conditions for timing measurements.
- Sampled only, not 100% tested.
- Time is measured to Status Register Read giving bit b7 = ’1’.
Figure 9. Asynchronous Write AC Waveforms
Table 19. Synchronous Write AC Characteristics(1) Note: 1. See AC Testing Measurement conditions for timing measurements.
- Sampled only, not 100% tested.
- Time is measured to Status Register Read giving bit b7 = ’1’.
Figure 10. Synchronous Write AC Waveforms
Figure 11. Reset/Power-down AC Waveforms Table 20. Reset/Power-down AC Characteristics Note: 1. The device Reset is possible but not guaranteed if tPLPH < 100ns. A Reset will complete within 100ns if RP is Low while not in Program or Erase.
Figure 12. Program Flowchart and Pseudo Code Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. Table 21. Program, Erase Times and Program/Erase Endurance Cycles
Figure 13. Program Suspend & Resume Flowchart and Pseudo Code Note: 1. PES instruction is not allowed during OBPG operation.
Figure 14. Erase Flowchart and Pseudo Code Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
Figure 15. Erase Suspend & Resume Flowchart and Pseudo Code Note: 1. PES instruction is not allowed during OBEE operation.
Figure 16. Command Interface and Program Erase Controller Flowchart (a) if VDD falls below VLKO , the Command Interface defaults to Read Array mode.
- P/E.C. status (Ready or Busy) is read on Status Register bit 7.
Figure 17. Command Interface and Program Erase Controller Flowchart (b) Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
Figure 18. Command Interface and Program Erase Controller Flowchart (c) Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
Table 22. Ordering Information Scheme Devices are shipped from the factory with the memory content bits erased to ’1’. this device, please contact the STMicroelectronics Sales Office nearest to you.
Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data Figure 19. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline
Table 24. LBGA80 - 10 x 8 balls, 1mm pitch, Package Mechanical Data Figure 20. LBGA80 - 10 x 8 balls, 1mm pitch, Bottom View Package Outline
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