M56Z8G32256A

Elite Semiconductor Mem...

32M x 32 Bit x 8 Banks May. 2023 - Revision: 1.2

Manufacturer: Elite Semiconductor Mem...

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Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 1/300 LPDDR4/LPDDR4X SDRAM 32M x 32 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM Feature  Ultra-low-voltage core and I/O power supply – VDD1 = 1.70–1.95V; 1.80V nominal – VDD2 = 1.06–1.17V; 1.10V nominal  Array configuration – 256 Meg × 32 (2 channels ×16 I/O)  Device configuration – 256M16 × 2 die in package  16n prefetch DDR architecture  8 internal banks per channel for concurrent operation  Single-data-rate CMD/ADR entry  Bidirectional/differential data strobe per byte lane  Programmable READ and WRITE latencies (RL/WL)  Programmable and on-the-fly burst lengths (BL = 16, 32)  Directed per-bank refresh for concurrent bank operation and ease of command scheduling  Up to 8.5 GB/s per die  On-chip temperature sensor to control self refresh rate  Partial-array self refresh (PASR)  Selectable output drive strength (DS)  Clock-stop capability  RoHS-compliant, “green” packaging  Programmable VSS (ODT) termination  Speed grade, cycle time – 535ps @ RL = 32/36  Operating temperature range – -25°C to +85°C

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 2/300

Ordering Information

(MHz) Data Rate (Mbps/pin) WRITE Latency READ Latency Package Comments Set A Set B DBI Disabled DBI Enabled M56Z8G32256A-SMBYG 1866 3733 16 30 32 36 200 ball BGA Pb-free SDRAM Addressing The table below shows 4 Gb single-channel die configuration used in the package. Device Configuration 256M x 32 (8 Gb/Package) Die configuration Channel A, rank 0 ×16 mode × 1 die Channel B, rank 0 ×16 mode × 1 die Die addressing Bank address BA[2:0] Row addresses R[14:0] Column addresses C[9:0] Note: 1. Refer to Block Diagrams section and Monolithic Device Addressing section.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 3/300 Block Diagram

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 4/300 Ball Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 A DNU DNU VSS VDD2 ZQ0 NC VDD2 VSS DNU DNU B DNU DQ0_A VDDQ DQ7_A VDDQ VDDQ DQ15_A VDDQ DQ8_A DNU C VSS DQ1_A DMI0_A DQ6_A VSS VSS DQ14_A DMI1_A DQ9_A VSS D VDDQ VSS DQS0 _t_A VSS VDDQ VDDQ VSS DQS1 _t_A VSS VDDQ E VSS DQ2_A DQS0 _c_A DQ5_A VSS VSS DQ13_A DQS1 _c_A DQ10_A VSS F VDD1 DQ3_A VDDQ DQ4_A VDD2 VDD2 DQ12_A VDDQ DQ11_A VDD1 G VSS ODT _CA_A VSS VDD1 VSS VSS VDD1 VSS NC VSS Power H VDD2 CA0_A NC CS0_A VDD2 VDD2 CA2_A CA3_A CA4_A VDD2 LPDDR4x_A (Channel A) J VSS CA1_A VSS CKE0_A NC CK_t_A CK_c_A VSS CA5_A VSS LPDDR4x_B (Channel B) K VDD2 VSS VDD2 VSS NC NC VSS VDD2 VSS VDD2 Ground L ZQ,ODT_CA, RESET M NC / DNU N VDD2 VSS VDD2 VSS NC NC VSS VDD2 VSS VDD2 P VSS CA1_B VSS CKE0_B NC CK_t_B CK_c_B VSS CA5_B VSS R VDD2 CA0_B NC CS0_B VDD2 VDD2 CA2_B CA3_B CA4_B VDD2 T VSS ODT _CA_B VSS VDD1 VSS VSS VDD1 VSS RESET_ n VSS U VDD1 DQ3_B VDDQ DQ4_B VDD2 VDD2 DQ12_B VDDQ DQ11_B VDD1 V VSS DQ2_B DQS0 _c_B DQ5_B VSS VSS DQ13_B DQS1 _c_B DQ10_B VSS W VDDQ VSS DQS0 _t_B VSS VDDQ VDDQ VSS DQS1 _t_B VSS VDDQ Y VSS DQ1_B DMI0_B DQ6_B VSS VSS DQ14_B DMI1_B DQ9_B VSS AA DNU DQ0_B VDDQ DQ7_B VDDQ VDDQ DQ15_B VDDQ DQ8_B DNU AB DNU DNU VSS VDD2 VSS VSS VDD2 VSS DNU DNU

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 5/300 Ball Descriptions Ball Name Type Function CK_t_A, CK_c_A, CK_t_B, CK_c_B Input Clock: CK_t and CK_c are differential clock inputs. All address, command and control input signals are sampled on positive edge of CK_t and the negative edge of CK_c. AC timings for CA parameters are referenced to clock. Each channel (A, B) has its own clock pair. CKE0_A, CKE1_A, CKE0_B, CKE1_B Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, input buffers, and output drivers. Power -saving modes are entered and exited via CKE transitions. CKE is sampled at the rising edge of CK. CS0_A, CS1_A, CS0_B, CS1_B Input Chip select: Each channel (A, B) has its own CS signals. CA[5:0]_A, CA[5:0]_B Input Command/Address inputs: Provide the command and address inputs according to the command truth table. Each channel (A, B) has its own CA signals. ODT_CA_A, ODT_CA_B Input LPDDR4 CA ODT control: The ODT_CA pin is used in conjunction with the mode register to turn on/off the on -die termination for CA pins. It is bonded to VDD2 within the package, or at the package ball, for the terminating rank, and the non -terminating ranks are bonded to VSS (or left floating with a weak pull-down on the DRAM die). The terminating rank is the DRAM that terminates the CA bus for all die on the same channel. LPDDR4X CA ODT Control: The ODT_CA pin is ignored by LPDDR4X devices. CA ODT is fully c ontrolled through MR11 and MR22. The ODT_CA pin shall be connected to a valid logic level. DQ[15:0]_A, DQ[15:0]_B Input / Output Data input/output: Bidirectional data bus. DQS[1:0]_t_A, DQS[1:0]_c_A, DQS[1:0]_t_B, DQS[1:0]_c_B Input / Output Data strobe: DQS_t and DQS_c are bi -directional differential output clock signals used to strobe data during a READ or WRITE. The data strobe is generated by the DRAM for a READ and is edge -aligned with data. The data strobe is generated by the SoC memory controller for a WRITE and is trained to precede data. Each byte of data has a data strobe signal pair. Each channel (A, B) has its own DQS_t and DQS_c strobes. DMI[1:0]_A, DMI[1:0]_B Input / Output Data mask/Data bus inversion: DMI is a dual use bi -directional signal used to indicate data to be masked, and data which is inverted on the bus. For data bus inversion (DBI), the DMI signal is driven HIGH when the data on the data bus is inverted, or driven LOW when the data is in its normal state. DBI can be disabled via a mode register setting. For data mask, the DMI signal is used in combination with the data lines to indicate data to be masked in a MASK WRITE command (see the Data Mask (DM) and Data Bus Inversion (DBI) sections for details). The data mask function can be disabled via a mode register setting. Each byte of data has a DMI signal. Each channel has its own DMI signals. ZQ0, ZQ1 Reference ZQ calibration reference: Used to calibrate the output drive strength and the termination resistance. The ZQ pin shall be connected to VDDQ through a 240Ω ±1% resistor. VDDQ, VDD1, VDD2 Supply Power supplies: Isolated on the die for improved noise immunity. VSS Supply Ground reference: Power supply ground reference. RESET_n Input RESET: When asserted LOW, the RESET pin resets all channels of the die. DNU - Do not use: Must be grounded or left floating. NC - No connect: Not internally connected.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 6/300 General Description The 8 Gb Mobile Low-Power DDR4 SDRAM with low VDDQ (LPDDR4X) is a high -speed CMOS, dynamic random -access memory. The device is internally configured with x16 I/O, 8-banks. Each of the x16’s 1,073,741,824-bit banks is organized as 65,536 rows by 1024 columns by 16 bits. General Note Throughout the data sheet, figures and text refer to DQs as “DQ.” DQ should be interpreted as any or all DQ collectively, unless specifically stated otherwise. “DQS” and “CK” should be interpreted as DQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise. “CA” includes all CA pins used for a given density. In timing diagrams, “CMD” is used as an indicator only. Actual signals occur on CA[5:0]. VREF indicates VREF(CA) and VREF(DQ). Complete functionality may be described throughout the entire document. Any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. Any specific requirement takes precedence over a general statement. Any functionality not specifically stated herein is considered undefined, illegal, is not supported, and will result in unkno wn operation.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 7/300 MR0, MR[6:5], MR8, MR13, MR24 Definition Mode Register Contents Note: 1. The contents of MR0, MR[6:5], MR8, MR13, and MR24 will reflect information specific to each die in these packages. 2. Other bits not defined above and other mode registers are referred to Mode Register A ssignments and Definitions section. Mode Register OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 MR0 Latency Mode REF OP[0] = 0b: Both legacy and modified refresh mode supported OP[1] = 0b: Device supports normal latency MR5 Manufacturer ID 1111 1111b MR6 0000 0011b MR8 I/O Width Density OP[7:6] =00b: x16/channel OP[5:2] = 0010b: 4Gb single channel die MR13 VRO OP[2] = 0b: Normal operation (default) 1b: Output the VREF(CA) value on DQ7 and VREF(DQ) value on DQ6 MR24 TRR Mode Unlimited MAC MAC Value OP[3:0] = 1000b: Unlimited MAC OP[7] = 0b: Disable (default) 1b: Reserved

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 8/300 IDD Parameters Refer to IDD Specification Parameters and Test Conditions section for detailed conditions. LPDDR4 IDD Parameters – Single-Die VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V; TC = -25°C to +85°C Symbol Supply Speed Grade Unit Note

3733 Mbps

IDD0Q VDDQ 0.75 IDD2P1 VDD1 0.9 mA IDD2P2 VDD2 1.3 IDD2PQ VDDQ 0.75 IDD2PS1 VDD1 0.9 mA IDD2PS2 VDD2 1.3 IDD2PSQ VDDQ 0.75 IDD2N1 VDD1 0.9 mA IDD2N2 VDD2 21 IDD2NQ VDDQ 0.75 IDD2NS1 VDD1 0.9 mA IDD2NS2 VDD2 15 IDD2NSQ VDDQ 0.75 IDD3P1 VDD1 0.9 mA IDD3P2 VDD2 8 IDD3PQ VDDQ 0.75 IDD3PS1 VDD1 0.9 mA IDD3PS2 VDD2 8 IDD3PSQ VDDQ 0.75 IDD3N1 VDD1 1.2 mA IDD3N2 VDD2 23 IDD3NQ VDDQ 0.75 IDD3NS1 VDD1 1.2 mA IDD3NS2 VDD2 17 IDD3NSQ VDDQ 0.75

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 9/300 LPDDR4 IDD Parameters – Single-Die (Continued) VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V; TC = -25°C to +85°C Note: 1. Published IDD values except IDD4RQ are the maximum of the distribution of the arithmetic mean. Refer to the following note for IDD4RQ; refer to IDD6 Full-Array Self Refresh Current table for IDD6. 2. IDD4RQ value is reference only. Typical value. DBI disabled, VOH = VDDQ/3, TC = 25°C. LPDDR4 IDD6 Full-Array Self Refresh Current VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V Note: 1. IDD6 25°C is the typical, and IDD6 85°C is the maximum of the distribution of the arithmetic mean. Symbol Supply Speed Grade Unit Note IDD4R1 VDD1 2.1 mA 2 IDD4R2 VDD2 322 IDD4RQ VDDQ 137 IDD4W1 VDD1 1.9 mA IDD4W2 VDD2 265 IDD4WQ VDDQ 0.75 IDD51 VDD1 9 mA IDD52 VDD2 68 IDD5Q VDDQ 0.75 IDD5AB1 VDD1 1.2 mA IDD5AB2 VDD2 25 IDD5ABQ VDDQ 0.75 IDD5PB1 VDD1 1.2 mA IDD5PB2 VDD2 25 IDD5PBQ VDDQ 0.75 Temperature Supply Full-Array Self Refresh Current Unit 25°C VDD1 0.19 mA VDD2 0.47 VDDQ 0.01 85°C VDD1 1 mA VDD2 3.8 VDDQ 0.75

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 10/300 LPDDR4X IDD Parameters – Single-Die Symbol Supply Speed Grade Unit Note IDD0Q VDDQ 0.75 IDD2P1 VDD1 0.9 mA IDD2P2 VDD2 1.3 IDD2PQ VDDQ 0.75 IDD2PS1 VDD1 0.9 mA IDD2PS2 VDD2 1.3 IDD2PSQ VDDQ 0.75 IDD2N1 VDD1 0.9 mA IDD2N2 VDD2 21 IDD2NQ VDDQ 0.75 IDD2NS1 VDD1 0.9 mA IDD2NS2 VDD2 15 IDD2NSQ VDDQ 0.75 IDD3P1 VDD1 0.9 mA IDD3P2 VDD2 8 IDD3PQ VDDQ 0.75 IDD3PS1 VDD1 0.9 mA IDD3PS2 VDD2 8 IDD3PSQ VDDQ 0.75 IDD3N1 VDD1 1.2 mA IDD3N2 VDD2 23 IDD3NQ VDDQ 0.75 IDD3NS1 VDD1 1.2 mA IDD3NS2 VDD2 17 IDD3NSQ VDDQ 0.75

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 11/300 LPDDR4X IDD Parameters – Single-Die (Continued) Note: 1. Published IDD values except IDD4RQ are the maximum of the distribution of the arithmetic mean. Refer to the following note for IDD4RQ; refer to IDD6 Full-Array Self Refresh Current table for IDD6. LPDDR4X IDD6 Full-Array Self Refresh Current Note: 1. IDD6 25°C is the typical, and IDD6 85°C is the maximum of the distribution of the arithmetic mean. Symbol Supply Speed Grade Unit Note IDD4R1 VDD1 1.9 mA 2 IDD4R2 VDD2 310 IDD4RQ VDDQ 91 IDD4W1 VDD1 1.9 mA IDD4W2 VDD2 265 IDD4WQ VDDQ 0.75 IDD51 VDD1 9 mA IDD52 VDD2 68 IDD5Q VDDQ 0.75 IDD5AB1 VDD1 1.2 mA IDD5AB2 VDD2 25 IDD5ABQ VDDQ 0.75 IDD5PB1 VDD1 1.2 mA IDD5PB2 VDD2 25 IDD5PBQ VDDQ 0.75 Temperature Supply Full-Array Self Refresh Current Unit 25°C VDD1 0.19 mA VDD2 0.47 VDDQ 0.01 85°C VDD1 1 mA VDD2 3.8 VDDQ 0.75

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 12/300 Functional Description The Mobile Low -Power DDR4 SDRAM (LPDDR4) is a high -speed CMOS, dynamic random -access memory internally configured with either 1 or 2 channels. Each channel is comprised of 16 DQs and 8 banks. LPDDR4 uses a 2-tick, single-data-rate (SDR) protocol on the CA bus to reduce the number of input signals in the system. The term "2-tick" means that the command/ address is decoded across two transactions, such that half of the command/address is captured with each of two consecutive rising edges of CK. The 6-bit CA bus contains command, address, and bank information. Some commands such as READ, WRITE,MASKED WRITE, and ACTIVATE require two consecutive 2-tick SDR commands to complete the instruction. LPDDR4 uses a double-data-rate (DDR) protocol on the DQ bus to achieve high-speed operation. The DDR interface transfers two data bits to each DQ lane in one clock cycle and is matched to a 16n -prefetch DRAM architecture. A write/read access consists of a single 16n-bit-wide data transfer to/from the DRAM core and 16 corresponding n -bitwide data transfers at the I/O pins. Read and write accesses to the device are burst -oriented. Accesses start at a selected column address and continue for a programmed number of columns in a programmed sequence. Accesses begin with the registration of an ACTIVATE command to open a row in the memory core, followed by a WRITE or READ command to access column data within the open row. The address and bank address (BA) bits registered by the ACTIVATE command are used to select the bank and row to be opened. The address and BA bits registered with the WRITE or READ command are used to select the bank and the starting column address for the burst access. Prior to normal operation, the LPDDR4 SDRAM must be initialized. Foll owing sections provide detailed information about device initialization, register definition, command descriptions and device operations. Functional Block Diagram

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 13/300 Monolithic Device Addressing The table below includes all monolithic device addressing options defined by JEDEC. Under the SDRAM Addressing heading near the beginning of this data sheet are addressing details for this product data sheet. Monolithic Device Addressing – Dual-Channel Die Note: 1. The lower two column addresses (C[1:0]) are assumed to be zero and are not transmitted on the CA bus. 2. Row and column address values on the CA bus that are not used for a particular density should be at valid logic levels. 3. For non-binary memory densities, only a quarter of the row address space is invalid. When the MSB address bit is HIGH, then the MSB - 1 address bit must be LOW. Memory Density (Per Die) 8Gb Memory density (per channel) 4Gb Configuration 32Mb × 16DQ × 8 banks × 2 channels Number of channels (per die) 2 Number of banks (per channel) 8 Array prefetch (bits, per channel) 256 Number of rows (per channel) 32,768 Number of columns (fetch boun- daries) 64 Page size (bytes) 2048 Channel density (bits per channel) 4,294,967,296 Total density (bits per die) 8,589,934,592 Bank address BA[2:0] ×16 Row add R[14:0] Col. add C[9:0] Burst starting address boundary 64 bit

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 14/300 Simplified Bus Interface State Diagram The state diagram provides a simplified illustration of the bus interface, supported state transitions, and the commands that control them. For a complete description of device behavior, use the information provided in the state diagram with the truth tables and timing specifications. The truth tables describe device behavior and applicable restrictions whe n considering the actual state of all banks. For command descriptions, see the Commands and Timing section. Simplified State Diagram

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 15/300 Note: 1. From the self refresh state, the device can enter power-down, MRR, MRW, or any of the training modes initiated with the MPC command. See the Self Refresh section. 2. All banks are precharged in the idle state. 3. In the case of using an MRW command to enter a training mode, the state machine will not automatically return to the idle state at the conclusion of training. See the applicable training section for more information. 4. In the case of an MPC command to enter a training mode, the state machine may not automatically return to the idle state at the conclusion of training. See the applicable training section for more information. 5. This diagram is intended to provide an overview of the possible state transitions and commands to control them; however, it does not contain the details necessary to operate the device. In particular, situations involving more than one bank are not captured in complete detail. 6. States that have an "automatic return" and can be accessed from more than one prior state (that is, MRW from either idle or active states) will return to the state where they were initiated (that is, MRW from idle will return to idle). 7. The RESET pin can be asserted from any state and will cause the device to enter the reset state. The diagram shows RESET applied from the power -on and idle states as an example,but this should not be construed as a restriction on RESET. 8. MRW commands from the active state cannot change operating parameters of the device that affect timing. Mode register fields which may be changed via MRW from the active state include: MR1 -OP[3:0], MR1 -OP[7], MR3 -OP[7:6], MR10-OP[7:0], MR11 -OP[7:0], MR13 -OP[5], MR15 -OP[7:0], MR16 -OP[7:0], MR17 -OP[7:0], MR20 -OP[7:0], and MR22-OP[4:0]. Simplified State Diagram

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 16/300 Power-Up and Initialization To ensure proper functionality for power-up and reset initialization, default values for the MR settings are provided in the table below. Mode Register Default Settings The following sequence must be used to power up the device. Unless specified otherwise,this procedure is mandatory. The power-up sequence of all channels must proceed simultaneously. Item Mode Register Setting Default Setting Description FSP-OP/WR MR13 OP[7:6] 00b FSP-OP/WR[0] are enabled WLS MR2 OP[6] 0b WRITE latency set A is selected WL MR2 OP[5:3] 000b WL = 4 RL MR2 OP[2:0] 000b RL = 6, nRTP = 8 nWR MR1 OP[6:4] 000b nWR = 6 DBI-WR/RD MR3 OP[7:6] 00b Write and read DBI are disabled CA ODT MR11 OP[6:4] 000b CA ODT is disabled DQ ODT MR11 OP[2:0] 000b DQ ODT is disabled VREF(CA) setting MR12 OP[6] 1b VREF(CA) range[1] is enabled VREF(CA) value MR12 OP[5:0] 011101b Range1: 50.3% of VDDQ VREF(DQ) setting MR14 OP[6] 1b VREF(DQ) range[1] enabled VREF(DQ) value MR14 OP[5:0] 011101b Range1: 50.3% of VDDQ

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 17/300 Voltage Ramp While applying power (after Ta), RESET_n should be held LOW (≦0.2 × VDD2), and all other inputs must be between VIL,min and VIH,max. The device outputs remain at High -Z while RESET_n is held LOW. Power supply voltage ramp requirements are provided in the table below. VDD1 must ramp at the same time or earlier than V DD2. VDD2 must ramp at the same time or earlier than VDDQ. Voltage Ramp Conditions Note: 1. Ta is the point when any power supply first reaches 300mV. 2. Voltage ramp conditions in above table apply between Ta and power-off (controlled or uncontrolled). 3. Tb is the point at which all supply and reference voltages are within their defined operating ranges. 4. Power ramp duration tINIT0 (Tb–Ta) must not exceed 20ms. 5. The voltage difference between any VSS and VSSQ must not exceed 100mV. Following completion of the of the voltage ramp (Tb), RESET_n must be held LOW for tINIT1. DQ, DMI, DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latch-up. CK_t and CK_c, CS, and CA input levels must be between VSS and VDD2 during voltage ramp to avoid latch-up. Voltage ramp power supply requirements are provided in the table below. Beginning at Tb, RESET_n must remain LOW for at least tINIT1(Tc), after which RESET_n can be de-asserted to HIGH(Tc). At least 10ns before CKE de-assertion, CKE is required to be set LOW. All other input signals are "Don't Care." Voltage Ramp and Initialization Sequence Note: 1. Training is optional and may be done at the system designer's discretion. The order of training may be different than what is shown here. After... Applicable Conditions Ta is reached VDD1 must be greater than VDD2 VDD2 must be greater than VDDQ - 200mV

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 18/300 After RESET_n is de -asserted (Tc), wait at least tINIT3 before activating CKE. CK_t, CK_c must be started and stabilized for tINIT4 before CKE goes active (Td). CS must remain LOW when the controller activates CKE. After CKE is set to HIGH, wait a minimum of tINIT5 to issue any MRR or MRW commands (Te). For MRR and MRW commands, the clock frequency must be within the range defined for tCKb. Some AC parameters (for example, tDQSCK) could have relaxed timings (such as tDQSCKb) before the system is appropriately configured. After completing all MRW commands to set the pull -up, pull-down, and Rx termination values, the controller can issue the ZQCAL START command to the memory (Tf). This command is used to calibrate the VOH level and the output impedance over process,voltage, and temperature. In systems where more than one device share one external ZQ resistor, the controller must not overlap the ZQ calibration sequence of each device.The ZQ calibration sequence is com pleted after tZQCAL (Tg). The ZQCAL LATCH command must be issued to update the DQ drivers and DQ + CA ODT to the calibrated values. After tZQLAT is satisfied (Th), the command bus (internal V REF(CA), CS, and CA) should be trained for high -speed operation by issuing an MRW command (command bus training mode). This command is used to calibrate the device's internal V REF and align CS/CA with CK for high-speed operation. The device will power-up with receivers configured for low-speed operations and with VREF(CA) set to a default factory setting. Normal device operation at clock speeds higher than tCKb may not be possible until command bus training is complete. The command bus training MRW command uses the CA bus as inputs for the calibration data stream, and it outputs the results asynchro-nously on the DQ bus. See command bus training in the MRW section for information on how to enter/exit the training mode. After command bus training, the controller must perform write leveling. Write leveling mode is enabled when MR2 OP[7] is HIGH (Ti). See the Write Leveling section for a detailed description of the write leveling entry and exit sequence. In write leveling mode, the controller adjusts write DQS timing to the point where the device recognizes the start of write DQ data bu rst with desired WRITE latency. After write leveling, the DQ bus (internal V REF(DQ), DQS, and DQ) should be trained for high -speed operation using the MPC TRAINING commands and by issuing MRW commands to adjust V REF(DQ). The device will power -up with receivers configured for low-speed operations and with VREF(DQ) set to a default factory setting. Normal device operation at clock speeds higher than tCKb should not be attempted until DQ bus training is complete. The MPC[READ DQ CALIBRATION] command is used together with MPC[READ -FIFO] or MPC[WRITE -FIFO] commands to train the DQ bus wi thout disturbing the memory array contents. See the DQ Bus Training section for more information on the DQ bus training sequence. At Tk, the device is ready for normal operation and is ready to accept any valid command. Any mode registers that have not previously been configured for normal operation should be written at this time. Initialization Timing Parameters Note: 1. Minimum tCKb guaranteed by DRAM test is 18ns. 2. The system may boot at a higher frequency than dictated by minimum tCKb. The higher boot frequency is system dependent. Parameter Min Max Unit Comment tINIT0 – 20 ms Maximum voltage ramp time tINIT1 200 – µs Minimum RESET_n LOW time after completion of voltage ramp tINIT2 10 – ns Minimum CKE LOW time before RESET_n goes HIGH tINIT3 2 – ms Minimum CKE LOW time after RESET_n goes HIGH tINIT4 5 – tCK Minimum stable clock before first CKE HIGH tINIT5 2 – μs Minimum idle time before first MRW/MRR command tCKb Note1, 2 Note1, 2 ns Clock cycle time during boot

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 19/300 Reset Initialization with Stable Power The following sequence is required for RESET at no power interruption initialization. 1. Assert RESET_n below 0.2 × V DD2 anytime when reset is needed. RESET_n needs to be maintained for minimum tPW_RESET. CKE must be pulled LOW at least 10ns before de-asserting RESET_n. 2. Repeat steps 4–10 in Voltage Ramp section. Reset Timing Parameter Parameter Value Unit Comment Min Max tPW_RESET 100 – ns Minimum RESET_n LOW time for reset initialization with stable power

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 20/300 Power-Off Sequence Controlled Power-Off While powering off, CKE must be held LOW (≤0.2 × V DD2); all other inputs must be between V IL,min and VIH,max. The device outputs remain at High-Z while CKE is held LOW. DQ, DMI, DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during the power-off sequence to avoid latch-up. CK_t, CK_c, CS, and CA input levels must be between VSS and VDD2 during the power-off sequence to avoid latch-up. Tx is the point where any power supply drops below the minimum value specified in the minimum DC Operating Condition. Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off. Power Supply Conditions The voltage difference between VSS and VSSQ must not exceed 100mV Uncontrolled Power-Off When an uncontrolled power-off occurs, the following conditions must be met.  At Tx, when the power supply drops below the minimum values specified in the Recommended DC Operating Conditions table, all power supplies must be turned off and all power supply current capacity must be at zero, except for any static charge remaining in the system.  After Tz (the point at which all power supplies first reach 300mV ), the device must power off. During this period, the relative voltage between power supplies is uncontrolled. V DD1 and VDD2 must decrease with a slope lower than 0.5 V/µs between Tx and Tz. An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device. Power-Off Timing Between... Applicable Conditions Tx and Tz VDD1 must be greater than VDD2 VDD2 must be greater than VDDQ - 200mV Parameter Symbol Min Max Unit Power-off ramp time tPOFF – 2 sec

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 21/300 Mode Registers Mode Register Assignments and Definitions Mode register definitions are provided in the Mode Register Assignments table. In the access column of the table, R indicates read-only; W indicates write-only; R/W indicates read- or write-capable or enabled. The MRR command is used to read from a register. The MRW command is used to write to a register. Mode Register Assignments Note 1–5 apply to entire table MR# MA[5:0] Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 0 00h Device info R RFU RZQI RFU Latency mode REF 1 01h Device feature 1 W RD-PST nWR (for AP) RD-PRE WR-PRE BL 2 02h Device feature 2 W WR Lev WLS WL RL 3 03h I/O config-1 W DBI-WR DBI-RD PDDS PPRP WR-PST PU-CAL 4 04h Refresh and training R /W TUF Thermal offset PPRE SR abort Refresh rate 5 05h Basic config-1 R Manufacturer ID 6 06h Basic config-2 R Revision ID1 7 07h Basic config-3 R Revision ID2 8 08h Basic config-4 R I/O width Density Type 9 09h Test mode W Vendor-specific test mode 10 0Ah I/O calibration W RFU ZQ RST 11 0Bh ODT W RFU CA ODT RFU DQ ODT 12 0Ch VREF(CA) R/W RFU VRCA VREF(CA) 13 0Dh Register control W FSP-OP FSP-WR DMD RRO VRCG VRO RPT CBT 14 0Eh VREF(DQ) R/W RFU VRDQ VREF(DQ) 15 0Fh DQI-LB W Lower-byte invert register for DQ calibration 16 10h PASR_Bank W PASR bank mask 17 11h PASR_Seg W PASR segment mask 18 12h IT-LSB R DQS oscillator count – LSB 19 13h IT-MSB R DQS oscillator count – MSB 20 14h DQI-UB W Upper-byte invert register for DQ calibration 21 15h Vendor use W RFU 22 16h ODT feature 2 W ODTD for x8_2ch ODTD -CA ODTE -CS ODTE -CK SoC ODT

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 22/300 Mode Register Assignments (Continued) Note 1–5 apply to entire table Note: 1. RFU bits must be set to 0 during MRW commands. 2. RFU bits are read as 0 during MRR commands. 3. All mode registers that are specified as RFU or write-only shall return undefined data when read via an MRR command. 4. RFU mode registers must not be written. 5. Writes to read-only registers will not affect the functionality of the device. MR0 Device Feature 0 (MA[5:0] = 00h) MR# MA[5:0] Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 23 17h DQS oscillator stop W DQS oscillator run-time setting 24 18h TRR control R/W TRR mode TRR mode BAn Unltd MAC MAC value 25 19h PPR resources R B7 B6 B5 B4 B3 B2 B1 B0 26–29 1Ah~1Dh – – Reserved for future use 30 1Eh Reserved for test W SDRAM will ignore 31 1Fh – – Reserved for future use 32 20h DQ calibration pattern A W See DQ calibration section 33–38 21h≈26h Do not use – Do not use 39 27h Reserved for test W SDRAM will ignore 40 28h DQ calibration pattern B W See DQ calibration section 41–47 29h≈2Fh Do not use – Do not use 48–63 30h≈3Fh Reserved – Reserved for future use OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU RZQI RFU Latency mode REF

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 23/300 MR0 Op-Code Bit Definitions Note: 1. RZQI MR value, if supported, will be valid after the following sequence:  Completion of MPC[ZQCAL START] command to either channel  Completion of MPC[ZQCAL LATCH] command to either channel then tZQLAT is satisfied RZQI value will be lost after reset. 2. If ZQ is connected to V SSQ to set default calibration, OP[4:3] must be set to 01b. If ZQ is not connected to V SSQ, either OP[4:3] = 01b or OP[4:3] = 10b might indicate a ZQ pin assembly error. It is recommended that the assembly error be corrected. 3. In the case o f possible assembly error, the device will default to factory trim settings for R ON, and will ignore ZQ CALIBRATION commands. In either case, the device may not function as intended. 4. If the ZQ pin self -test returns OP[4:3] = 11b, the device has detected a resistor connected to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor meets the specified limits (that is, 240Ω 1%). 5. See byte mode addendum spec for byte mode latency details. 6. Byte mode latency for 2Ch. x16 device is only allowed when it is stacked in a same package with byte mode device. Register Information Type OP Definition Note Refresh mode Read-only OP[0] 0b: Both legacy and modified refresh mode supported 1b: Only modified refresh mode supported Latency mode Read-only OP[1] 0b: Device supports normal latency 1b: Device supports byte mode latency 5, 6 Built-in self-test for RZQ information Read-only OP[4:3] 00b: RZQ self-test not supported 01b: ZQ may connect to VSSQ or float 10b: ZQ may short to VDDQ 11b: ZQ pin self-test completed, no error condition detected (ZQ may not connect to VSSQ, float, or short to VDDQ) 1–4

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 24/300 MR1 Device Feature 1 (MA[5:0] = 01h) MR1 Op-Code Bit Definitions Note: 1. Burst length on-the-fly can be set to either BL = 16 or BL = 32 by setting the BL bit in the command operands. See the Command Truth Table. 2. The programmed value of nWR is the number of clock cycles the device uses to deter - mine the starting point of an internal precharge after a write burst with auto precharge (AP) enabl ed. See Frequency Ranges for RL, WL, and nWR Settings table. 3. For READ operations, this bit must be set to select between a toggling preamble and a non -toggling preamble. (See the Preamble section.) 4. OP[7] provides an optional read postamble with an addition al rising and falling edge of DQS_t. The optional postamble cycle is provided for the benefit of certain memory con- trollers. 5. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP ‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address. 6. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Th e device will operate only according to the values stored in the registers for the active set point, that is, the set point determined by the state of the FSP ‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation. OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RD-PST nWR (for AP) RD-PRE WR-PRE BL Feature Type OP Definition Note BL Burst length Write-only OP[1:0] 00b: BL = 16 sequential (default) 01b: BL = 32 sequential 10b: BL = 16 or 32 sequential (on-the-fly) 11b: Reserved WR-PRE Write preamble length Write-only OP[2] 0b: Reserved 1b: WR preamble = 2 × tCK 5, 6 RD-PRE Read preamble type Write-only OP[3] 0b: RD preamble = Static (default) 1b: RD preamble = Toggle 3, 5, 6 nWR Write-recovery for AUTO PRECHARGE command Write-only OP[6:4] 000b: nWR = 6 (default) 001b: nWR = 10 010b: nWR = 16 011b: nWR = 20 100b: nWR = 24 101b: nWR = 30 110b: nWR = 34 2, 5, 6 RD-PST Read postamble length Write-only OP[7] 0b: RD postamble = 0.5 × tCK (default) 1b: RD postamble = 1.5 × tCK 4, 5, 6

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 25/300 Burst Sequence for Read 16-Bit READ Operation 32-Bit READ Operation F B E A D C B F A E D C B F A E D C B F A E D C F B F B E A E A D D C C B F B F A E A E D D C C B F B F A E A E D D C C B F B F A E A E D D C C V V V V Note: 1. C[1:0] are not present on the CA bus; they are implied to be zero. 2. The starting burst address is on 64-bit (4n) boundaries.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 26/300 Burst Sequence for Write 16-Bit WRITE Operation 32-Bit WRITE Operation F F E E D D C C B B A A V Note: 1. C[1:0] are not present on the CA bus; they are implied to be zero. 2. The starting burst address is on 256-bit (16n) boundaries for burst length 16. 3. The starting burst address is on 512-bit (32n) boundaries for burst length 32. 4. C[3:2] must be set to 0 for all WRITE operations.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 27/300 MR2 Device Feature 2 (MA[5:0] = 02h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 WR Lev WLS WL RL MR2 Op-Code Bit Definitions Feature Type OP Definition Note RL READ latency Write-only OP[2:0] RL and nRTP for DBI-RD disabled (MR3 OP[6] = 0b) 000b: RL = 6, nRTP = 8 (default) 001b: RL = 10, nRTP = 8 010b: RL = 14, nRTP = 8 011b: RL = 20, nRTP = 8 100b: RL = 24, nRTP = 10 101b: RL = 28, nRTP = 12 110b: RL = 32, nRTP = 14 1, 3, 4 RL and nRTP for DBI-RD enabled (MR3 OP[6] = 1b) 000b: RL = 6, nRTP = 8 001b: RL = 12,nRTP = 8 010b: RL = 16, nRTP = 8 011b: RL = 22, nRTP = 8 100b: RL = 28, nRTP = 10 101b: RL = 32, nRTP = 12 110b: RL = 36, nRTP = 14 WL WRITE latency Write- only OP[5:3] WL set A (MR2 OP[6] = 0b) 000b: WL = 4 (default) 001b: WL = 6 010b: WL = 8 011b: WL = 10 100b: WL = 12 101b: WL = 14 110b: WL = 16 1, 3, 4 WL set B (MR2 OP[6] = 1b) 000b: WL = 4 001b: WL = 8 010b: WL = 12 011b: WL = 18 100b: WL = 22 101b: WL = 26 110b: WL = 30 WLS WRITE latency set Write- only OP[6] 0b: Use WL set A (default) 1b: Use WL set B 1, 3, 4 WR Lev Write leveling Write- only OP[7] 0b: Disable write leveling (default) 1b: Enable write leveling 2

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 28/300 Note: 1. See Latency Code Frequency Table for allowable frequency ranges for RL/WL/nWR. 2. After an MRW command to set the write leveling enable bit (OP[7] = 1b), the device re - mains in the MRW state until another MRW command clears the bit (OP[7] = 0b). No other com mands are allowed until the write leveling enable bit is cleared. 3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP ‐WR bit (MR13 OP[6]) will be written to with an MRW command this MR address, or read from with an MRR command to this address. 4. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, that is, the set point determined by the state of the FSP ‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation. 5. nRTP is valid for BL16 only. For BL32, the SDRAM will add 8 clocks to the nRTP value be- fore starting a precharge.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 29/300 Frequency Ranges for RL, WL, nWR, and nRTP Settings READ Latency WRITE Latency nWR nRTP Lower Frequency Limit (>) Upper Frequency Limit (≤) Units Note No DBI w/DBI Set A Set B 6 6 4 4 6 8 10 266 MHz 1–6 10 12 6 8 10 8 266 533 14 16 8 12 16 8 533 800 20 22 10 18 20 8 800 1066 24 28 12 22 24 10 1066 1333 28 32 14 26 30 12 1333 1600 32 36 16 30 34 14 1600 1866 Note: 1. The device should not be operated at a frequency above the upper frequency limit or below the lower frequency limit shown for each RL, WL, or nWR value. 2. DBI for READ operations is enabled in MR3 OP[ 6]. When MR3 OP[6] = 0, then the "No DBI" column should be used for READ latency. When MR3 OP[6] = 1, then the "w/DBI" column should be used for READ latency. 3. WRITE latency set A and set B are determined by MR2 OP[6]. When MR2 OP[6] = 0, then WRITE latency set A should be used. When MR2 OP[6] = 1, then WRITE latency set B should be used. 4. The programmed value for nRTP is the number of clock cycles the device uses to determine the starting point of an internal PRECHARGE operation after a READ burst with AP (auto precharge) enabled. It is determined by RU(tRTP/tCK). 5. The programmed value of nWR is the number of clock cycles the device uses to deter - mine the starting point of an internal PRECHARGE operation after a WRITE burst with AP (auto precharge) enabled. I t is determined by RU(tWR/tCK). 6. nRTP shown in this table is valid for BL16 only. For BL32, the device will add 8 clocks to the nRTP value before starting a precharge. MR3 I/O Configuration 1 (MA[5:0] = 03h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DBI-WR DBI-RD PDDS PPRP WR-PST PU-CAL

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 30/300 MR3 Op-Code Bit Definitions Feature Type OP Definition Note PU-CAL (Pull-up calibration point) Write-only OP[0] 0b: VDDQ × 0.6 1–4 1b: VDDQ × 0.5 (default) WR-PST (WR postamble length) OP[1] 0b: WR postamble = 0.5 × tCK (default) 2, 3, 5 1b: WR postamble = 1.5 × tCK PPRP (Post-package repair protection) OP[2] 0b: PPR protection disabled (default) 1b: PPR protection enabled PDDS (Pull-down drive strength) OP[5:3] 000b: RFU 1, 2, 3 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 (default) 111b: Reserved DBI-RD (DBI-read enable) OP[6] 0b: Disabled (default) 2, 3 1b: Enabled DBI-WR (DBI-write enable) OP[7] 0b: Disabled (default) 2, 3 1b: Enabled Note: 1. All values are typical. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Recalibration may be required as voltage and temperature vary. 2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP ‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1.The device will operate only according to the values stored in the registers for the active set point, for example, the s et point determined by the state of the FSP ‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be determined by the state of the FSP ‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. 4. For dual-channel device, PU‐CAL (MR3‐OP[0]) must be set the same for both channels on a die. The SDRAM will read the value of only one register (Ch.A or Ch.B); the choice is vendor-specific, so both channels must be set the same. 5. 1.5 × tCK apply > 1.6 GHz clock. 6. If MR3 OP[2] is set to 1b, PPR protection mode is enabled. The PPR protection bit is a sticky bit and can only be set to 0b by a power on reset. MR4 OP[4] controls entry to PPR mod e. If PPR protection is enabled then the DRAM will not allow writing of 1b to MR4 OP[4].

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 31/300 MR4 Device Temperature (MA[5:0] = 04h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 TUF Thermal offset PPRE SR abort Refresh rate MR4 Op-Code Bit Definitions Feature Type OP Definition Note Refresh rate Read-only OP[2:0] 000b: SDRAM low temperature operating limit exceeded 001b: 4x refresh 010b: 2x refresh 011b: 1x refresh (default) 100b: 0.5x refresh 101b: 0.25x refresh, no derating 110b: 0.25x refresh, with derating 111b: SDRAM high temperature operating limit exceeded 1–4, 7–9 SR abort (Self refresh abort) Write OP[3] 0b: Disable (default) 1b: Device dependent 9 PPRE (Post-package repair entry/ exit) Write OP[4] 0b: Exit PPR mode (default) 1b:Enter PPR mode (Reference MR25 OP[7:0] for available PPR resources) 5, 9 Thermal offset-controller offset to TCSR Write OP[6:5] 00b: No offset, 0~5°C gradient (default) 01b: 5°C offset, 5~10°C gradient 10b: 10°C offset, 10~15°C gradient 11b: Reserved TUF (Temperature update flag) Read-only OP7 0b: OP[2:0] No change in OP[2:0] since last MR4 read (default) 1b: Change in OP[2:0] since last MR4 read 6–8 Note: 1. The refresh rate for each MR4 OP[2:0] setting applies to tREFI, tREFIpb, and tREFW. MR4 OP[ 2:0] = 011b corresponds to a device temperature of 85°C. Other values require either a longer (2x, 4x) refresh interval at lower temperatures or a shorter (0.5x, 0.25x) refresh interval at higher temperatures. If MR4 OP[2] = 1b, the device temperature is g reater than 85°C. 2. At higher temperatures (>85°C), AC timing derating may be required. If derating is required the device will set MR4 OP[2:0] = 110b. See derating timing requirements in the AC Timing section. 3. DRAM vendors may or may not report all of the possible settings over the operating temperature range of the device. Each vendor guarantees that their device will work at any temperature within the range using the refresh interval requested by their device. 4. The device may not operate properly when MR4 OP[2:0 ] = 000b or 111b. 5. Post‐package repair can be entered or exited by writing to MR4 OP[4]. 6. When MR4 OP[7] = 1b, the refresh rate reported in MR4 OP[2:0] has changed since the last MR4 read. A mode register read from MR4 will reset MR4 OP[7] to 0b. 7. MR4 OP[7] = 0b at power‐up. MR4 OP[2:0] bits are valid after initialization sequence (Te). 8. See the Temperature Sensor section for information on the recommended frequency of reading MR4. 9. MR4 OP[6:3] can be written in this register. All other bits will be ignor ed by the device during an MRW command to this register.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 32/300 MR5 Basic Configuration 1 (MA[5:0] = 05h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Manufacturer ID MR5 Op-Code Bit Definitions Feature Type OP Definition Manufacturer ID Read-only OP[7:0] 1111 1111b All others: Reserved MR6 Basic Configuration 2 (MA[5:0] = 06h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Note: MR6 is vendor-specific. MR6 Op-Code Bit Definitions Feature Type OP Definition Note: MR6 is vendor-specific. MR7 Basic Configuration 3 (MA[5:0] = 07h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 MR7 Op-Code Bit Definitions Feature Type OP Definition Note: MR7 is vendor-specific.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 33/300 MR8 Basic Configuration 4 (MA[5:0] = 08h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 I/O width Density Type MR8 Op-Code Bit Definitions Feature Type OP Definition Type Read-only OP[1:0] 00b: S16 SDRAM (16n prefetch) All others: Reserved Density Read-only OP[5:2] 0000b: 4Gb dual-channel die/2Gb single-channel die 0001b: 6Gb dual-channel die/3Gb single-channel die 0010b: 8Gb dual-channel die/4Gb single-channel die 0011b: 12Gb dual-channel die/6Gb single-channel die 0100b: 16Gb dual-channel die/8Gb single-channel die 0101b: 24Gb dual-channel die/12Gb single-channel die 0110b: 32Gb dual-channel die/16Gb single-channel die 1100b: 2Gb dual-channel die/1Gb single-channel die All others: Reserved I/O width Read-only OP[7:6] 00b: x16/channel 01b: x8/channel All others: Reserved MR9 Test Mode (MA[5:0] = 09h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Vendor-specific test mode MR9 Op-Code Definitions Feature Type OP Definition Test mode Write-only OP[7:0] 0000000b; Vendor-specific test mode disabled (default) MR10 Calibration (MA[5:0] = 0Ah) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU ZQ RESET

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 34/300 MR10 Op-Code Bit Definitions Feature Type OP Definition ZQ reset Write-only OP[0] 0b: Normal operation (default) 1b: ZQ reset Note: 1. See AC Timing table for calibration latency and timing. 2. If ZQ is connected to V DDQ through RZQ, either the ZQ CALIBRATION function or default calibration (via ZQ reset) is supported. If ZQ is connected to V SS, the device operates with default calibration and ZQ CALIBRATION comman ds are ignored. In both cases, the ZQ connection must not change after power is supplied to the device. MR11 ODT Control (MA[5:0] = 0Bh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU CA ODT RFU DQ ODT MR11 Op-Code Bit Definitions Feature Type OP Definition Note DQ ODT DQ bus receiver on-die termination Write-only OP[2:0] 000b: Disable (default) 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 111b: RFU 1, 2, 3 CA ODT CA bus receiver on-die termination Write-only OP[6:0] 000b: Disable (default) 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 111b: RFU 1, 2, 3 Note: 1. All values are typical. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Re‐calibration may be required as voltage and temperature vary. 2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Th e device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP ‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 35/300 MR12 Register Information (MA[5:0] = 0Ch) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU VRCA VREF(CA) MR12 Op-Code Bit Definitions Feature Type OP Data Note VREF(CA) VREF(CA) settings Read/ Write OP[5:0] 000000b–110010b: See VREF Settings table All others: Reserved 1–3,5,6 VRCA VREF(CA) range Read/ Write OP[6] 0b: VREF(CA) range[0] enabled 1b: VREF(CA) range[1] enabled (default) 1,2,4,5,6 Note: 1. This register controls the V REF(CA) levels for frequency set point[1:0]. Values from either VR(ca)[0] or VR(ca)[1] may be selected by setting MR12 OP[6] appropriately. 2. A read to MR12 places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ will be set to 0. See the MRR Operation section. 3. A write to MR12 OP[5:0] sets the internal V REF(CA) level for FSP[0] when MR13 OP[6] = 0b or sets the internal V REF(CA) level for FSP[1] when MR13 OP[6] = 1b. The time required for V REF(CA) to reach the set level depends on the step size from the current level to the new level. See the VREF(CA) training section. 4. A write to MR12 OP[6] switches the device between two internal V REF(CA) ranges. The range (range[0] or range[1]) must be selected when setting the V REF(CA) register. The value, once set, w ill be retained until overwritten or until the next power‐on or reset event. 5. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 6. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Th e device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP ‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. MR13 Register Control (MA[5:0] = 0Dh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 FSP-OP FSP-WR DMD RRO VRCG VRO RPT CBT

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 36/300 MR13 Op-Code Bit Definition Feature Type OP Definition Note CBT Command bus training Write-only OP[0] 0b: Normal operation (default) 1b: Command bus training mode enabled 1 RPT Read preamble training OP[1] 0b: Disabled (default) 1b: Read preamble training mode enabled VRO VREF output OP[2] 0b: Normal operation (default) 1b: Output the VREF(CA) and VREF(DQ) values on DQ bits 2 VRCG VREF current generator OP[3] 0b: Normal operation (default) 1b: Fast response (high current) mode 3 RRO Refresh rate option OP[4] 0b: Disable codes 001 and 010 in MR4 OP[2:0] 1b: Enable all codes in MR4 OP[2:0] 4,5 DMD Data mask disable OP[5] 0b: DATA MASK operation enabled (default) 1b: DATA MASK operation disabled 6 FSP-WR Frequency set point write/ read OP[6] 0b: Frequency set point[0] (default) 1b: Frequency set point[1] 7 FSP-OP FREQUENCY SET POINT operation mode OP[7] 0b: Frequency set point[0] (default) 1b: Frequency set point[1] 8 Note: 1. A write to set OP[0] = 1 causes the LPDDR4 SDRAM to enter the command bus training mode. When OP[0] = 1 and CKE goes LOW, commands are ignored and the contents of CA[5:0] are mapped to the DQ bus. CKE must be brought HIGH before doing a MRW to clear this bit (OP[0] = 0) and return to normal operation. See the Command Bus Training section for more information. 2. When set, the device will out put the VREF(CA) and VREF(DQ) voltage on DQ pins. Only the "active" frequency set point, as defined by MR13 OP[7], will be output on the DQ pins. This function allows an external test system to measure the internal VREF levels. The DQ pins used for VREF output are vendor-specific. 3. When OP[3] = 1, the VREF circuit uses a high current mode to improve VREF settling time. 4. MR13 OP[4] RRO bit is valid only when MR0 OP[0] = 1. For LPDDR4 SDRAM with MR0 OP[0] = 0, MR4 OP[2:0] bits are not dependent on MR13 OP[4]. 5. When OP[4] = 0, only 001b and 010b in MR4 OP[2:0] are disabled. LPDDR4 SDRAM must report 011b instead of 001b or 010b in this case. Controller should follow the refresh mode reported by MR4 OP[2:0], regardless of RRO setting. TCSR function does not depend on RRO setting. 6. When enabled (OP[5] = 0b) data masking is enabled for the device. When disabled (OP[5] = 1b), the device will ignore any mask patterns issued during a MASKED WRITE command. See the Data Mask section for more information. 7. FSP‐WR determines which frequency set point registers are accessed with MRW and MRR commands for the following functions such as V REF(CA) setting, V REF(CA) range, V REF(DQ) setting, V REF(DQ) range. For more information, refer to Frequency Set Point section. 8. FSP‐OP determines w hich frequency set point register values are currently used to specify device operation for the following functions such as VREF(CA) setting, VREF(CA) range, VREF(DQ) setting, VREF(DQ) range. For more information, refer to Frequency Set Point section.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 37/300 Mode Register 14 (MA[5:0] = 0Eh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU VRDQ VREF(DQ) MR14 Op-Code Bit Definition Feature Type OP Definition Note VREF(DQ) VREF(DQ) setting Read/ Write OP[5:0] 000000b–110010b: See VREF Settings table All others: Reserved 1–3,5,6 VRDQ VREF(DQ) range OP[6] 0b: VREF(DQ) range[0] enabled 1b: VREF(DQ) range[1] enabled (default) 1,2,4–6 Note: 1. This register controls the V REF(DQ) levels for frequency set point[1:0]. Values from either VR DQ[0] (vendor defined) or VRDQ[1] (vendor defined) may be selected by setting OP[6] appropriately. 2. A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ shall be set to 0. See the MRR Operation section. 3. A write to OP[5:0] sets the internal VREF(DQ) level for FSP[0] when MR13 OP[6] = 0b, or sets FSP[1] when MR13 OP[6] = 1b. The time required for V REF(DQ) to reach the set level depends on the step size from the current level to the new level. See the VREF(DQ) training section. 4. A write to OP[6] swi tches the device between two internal V REF(DQ) ranges. The range (range[0] or range[1]) must be selected when setting the V REF(DQ) register. The value, once set, will be retained until overwritten, or until the next power‐on or reset event. 5. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP ‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 6. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active se t point, for example, the set point determined by the state of the FSP ‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 38/300 VREF Setting for Range[0] and Range[1] Note 1-3 apply to entire table Function OP Range[0] Values Range[1] Values VREF(CA) (% of VDDQ) VREF(DQ) (% of VDDQ) VREF(CA) (% of VDDQ) VREF(DQ) (% of VDDQ) VREF setting for MR12 and MR14 OP[5:0] 000000b: 15.0% 011010b: 30.5% 000000b: 32.9% 011010b: 48.5% 000001b: 15.6% 011011b: 31.1% 000001b: 33.5% 011011b: 49.1% 000010b: 16.2% 011100b: 31.7% 000010b: 34.1% 011100b: 49.7% 000011b: 16.8% 011101b: 32.3% 000011b: 34.7% 011101b: 50.3% (default) 000100b: 17.4% 011110b: 32.9% 000100b: 35.3% 011110b: 50.9% 000101b: 18.0% 011111b: 33.5% 000101b: 35.9% 011111b: 51.5% 000110b: 18.6% 100000b: 34.1% 000110b: 36.5% 100000b: 52.1% 000111b: 19.2% 100001b: 34.7% 000111b: 37.1% 100001b: 52.7% 001000b: 19.8% 100010b: 35.3% 001000b: 37.7% 100010b: 53.3% 001001b: 20.4% 100011b: 35.9% 001001b: 38.3% 100011b: 53.9% 001010b: 21.0% 100100b: 36.5% 001010b: 38.9% 100100b: 54.5% 001011b: 21.6% 100101b: 37.1% 001011b: 39.5% 100101b: 55.1% 001100b: 22.2% 100110b: 37.7% 001100b: 40.1% 100110b: 55.7% 001101b: 22.8% 100111b: 38.3% 001101b: 40.7% 100111b: 56.3% 001110b: 23.4% 101000b: 38.9% 001110b: 41.3% 101000b: 56.9% 001111b: 24.0% 101001b: 39.5% 001111b: 41.9% 101001b: 57.5% 010000b: 24.6% 101010b: 40.1% 010000b: 42.5% 101010b: 58.1% 010001b: 25.1% 101011b: 40.7% 010001b: 43.1% 101011b: 58.7% 010010b: 25.7% 101100b: 41.3% 010010b: 43.7% 101100b: 59.3% 010011b: 26.3% 101101b: 41.9% 010011b: 44.3% 101101b: 59.9% 010100b: 26.9% 101110b: 42.5% 010100b: 44.9% 101110b: 60.5% 010101b: 27.5% 101111b: 43.1% 010101b: 45.5% 101111b: 61.1% 010110b: 28.1% 110000b: 43.7% 010110b: 46.1% 110000b: 61.7% 010111b: 28.7% 110001b: 44.3% 010111b: 46.7% 110001b: 62.3% 011000b: 29.3% 110010b: 44.9% 011000b: 47.3% 110010b: 62.9% 011001b: 29.9% All others: Reserved 011001b: 47.9% All others: Reserved Note: 1. These values may be used for MR14 OP[5:0] and MR12 OP[5:0] to set the VREF(CA) or VREF(DQ) levels in the device. 2. The range may be selected in each of the MR14 or MR12 registers by setting OP[6] appropriately. 3. Each of the MR14 or MR12 registers represents either FSP[0] or FSP[1]. Two frequency set points each for CA and DQ are provided to allow for faster switching be tween terminated and unterminated operation or between different high‐frequency settings, which may use different terminations values.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 39/300 MR15 Register Information (MA[5:0] = 0Fh) OP[7] OP[6] OP[5] OP[4] OP[3] OP[2] OP[1] OP[0] Lower-byte invert register for DQ calibration MR15 Op-code Bit Definition Feature Type OP Definition Note Lower-byte invert for DQ calibration Write-only OP[7:0] The following values may be written for any operand OP[7:0] and will be applied to the corresponding DQ locations DQ[7:0] within a byte lane 0b: Do not invert 1b: Invert the DQ calibration patterns in MR32 and MR40 Default value for OP[7:0] = 55h 1–3 Note: 1. This register will invert the DQ calibration pattern found in MR32 and MR40 for any single DQ or any combination of DQ. Example: If MR15 OP[7:0] = 00010101b, then the DQ calibration patterns transmitted on DQ[7, 6, 5, 3, 1] will not be inverted, but the DQ calibration patterns transmitted on DQ[4, 2, 0] will be inverted. 2. DM[0] is not inverted and always transmits the "true" data contained in MR32 and MR40. 3. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3-OP[6]. MR15 Invert Register Pin Mapping PIN DQ0 DQ1 DQ2 DQ3 DMIO DQ4 DQ5 DQ6 DQ7 MR15 OP0 OP1 OP2 OP3 No invert OP4 OP5 OP6 OP7 MR16 PASR Bank Mask (MA[5:0] = 010h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 PASR bank mask

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 40/300 MR16 Op-Code Bit Definitions Feature Type OP Definition Bank[7:0] mask Write-only OP[7:0] 0b: Bank refresh enabled (default) 1b: Bank refresh disabled OP[n] Bank Mask 8-Bank SDRAM 0 xxxxxxx1 Bank 0 1 xxxxxx1x Bank 1 2 xxxxx1xx Bank 2 3 xxxx1xxx Bank 3 4 xxx1xxxx Bank 4 5 xx1xxxxx Bank 5 6 x1xxxxxx Bank 6 7 1xxxxxxx Bank 7 Note: 1. When a mask bit is asserted (OP[n] = 1), refresh to that bank is disabled. 2. PASR bank masking is on a per-channel basis; the two channels on the die may have different bank masking in dual-channel devices. MR17 PASR Segment Mask Definitions Feature Type OP Definition Segment[7:0] mask Write-only OP[7:0] 0b: Segment refresh enabled (default) 1b: Segment refresh disabled MR17 PASR Segment Mask Segment OP Segment Mask Density (per channel) 1Gb 2Gb 3Gb 4Gb 6Gb 8Gb 12Gb 16Gb 0 0 XXXXXXX1 000b 1 1 XXXXXX1X 001b 2 2 XXXXX1XX 010b 3 3 XXXX1XXX 011b 4 4 XXX1XXXX 100b 5 5 XX1XXXXX 101b 6 6 X1XXXXXX 110b 110b Not allowed 110b Not allowed 110b Not allowed 110b 7 7 1XXXXXXX 111b 111b 111b 111b 111b Note: 1. This table indicates the range of row addresses in each masked segment. "X" is “Don’t Care” for a particular segment. 2. PASR segment-masking is on a per-channel basis. The two channels on the die may have different segment masking in dual-channel devices. 3. For 3Gb, 6Gb, and 12Gb density per channel, OP[7:6] must always be LOW (= 00b).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 41/300 MR18 Register Information (MA[5:0] = 12h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS oscillator count - LSB MR18 LSB DQS Oscillator Count Note 1–3 apply to entire table Feature Type OP Definition DQS oscillator count (WR training DQS oscillator) Read-only OP[7:0] 0h–FFh LSB DRAM DQS oscillator count Note: 1. MR18 reports the LSB bits of the DRAM DQS oscillator count. The DRAM DQS oscillator count value is used to train DQS to the DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust the phase of DQS relative to DQ. 2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS oscillator count. 3. The value in this register is reset each time an MPC command is issued to start in the DQS oscillator counter. MR19 Register Information (MA[5:0] = 13h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS oscillator count - MSB MR19 DQS Oscillator Count Note 1–3 apply to the entire table Feature Type OP Definition DQS oscillator count – MSB (WR training DQS oscillator) Read-only OP[7:0] 0h–FFh MSB DRAM DQS oscillator count Note: 1. MR19 reports the MSB bits of the DRAM DQS oscillator count. The DRAM DQS oscillator count value is used to train DQS to the DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust the phase of DQS relative to DQ. 2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS oscillator count. 3. A new MPC[START DQS OSCILLATOR] should be issued to reset the contents of MR18/ MR19.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 42/300 MR20 Register Information (MA[5:0] = 14h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Upper-byte invert register for DQ calibration MR20 Register Information Note 1–3 apply to entire table Feature Type OP Definition Upper-byte invert for DQ calibration Write-only OP[7:0] The following values may be written for any operand OP[7:0] and will be applied to the corresponding DQ locations DQ[15:8] within a byte lane 0b: Do not invert 1b: Invert the DQ calibration patterns in MR32 and MR40 Default value for OP[7:0] = 55h Note: 1. This register will invert the DQ calibration pattern found in MR32 and MR40 for any single DQ or any combination of DQ. For example, if MR20 OP[7:0] = 00010101b, the DQ calibration patterns transmitted on DQ[15, 14, 13, 11, 9] will not be inverted, but the DQ calibration patterns transmitted on DQ[12, 10, 8] will be inverted. 2. DM[1] is not inverted and always transmits the true data contained in MR32 and MR40. 3. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3 OP[6]. MR20 Invert Register Pin Mapping Pin DQ8 DQ9 DQ10 DQ11 DMI1 DQ12 DQ13 DQ14 DQ15 MR20 OP0 OP1 OP2 OP3 No invert OP4 OP5 OP6 OP7 MR21 Register Information (MA[5:0] = 15h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 43/300 MR22 Register Information (MA[5:0] = 16h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 ODTD for x8_2ch ODTD-CA ODTE-CS ODTE-CK SOC ODT MR22 Register Information Feature Type OP Definition Note SOC ODT (controller ODT value for VOH calibration) Write-only OP[2:0] 000b: Disable (default) 001b: RZQ/1 (Illegal if MR3 OP[0] = 0b) 010b: RZQ/2 011b: RZQ/3 (Illegal if MR3 OP[0] = 0b) 100b: RZQ/4 101b: RZQ/5 (Illegal if MR3 OP[0] = 0b) 110b: RZQ/6 (Illegal if MR3 OP[0] = 0b) 111b: RFU 1, 2, 3 ODTE-CK (CK ODT enabled for non-terminating rank) Write-only OP[3] ODT bond PAD is ignored 0b: ODT-CK enable (default) 1b: ODT-CK disable 2, 3 ODTE-CS (CS ODT enabled for non-terminating rank) Write-only OP[4] ODT bond PAD is ignored 0b: ODT-CS enable (default) 1b: ODT-CS disable 2, 3 ODTD-CA (CA ODT termination disable) Write-only OP[5] ODT bond PAD is ignored 0b: CA ODT enable (default) 1b: CA ODT disable 2, 3 ODTD for x8_2ch (Byte) mode Write-only OP[7:6] See Byte Mode section Note: 1. All values are typical. 2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP -WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers fo r the active set point, for example, the set point determined by the state of the FSP -OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device oper- ation.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 44/300 MR23 Register Information (MA[5:0] = 17h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS interval timer run-time setting MR23 Register Information Note 1–2 apply to entire table Feature Type OP Definition DQS interval timer run-time Write-only OP[7:0] 00000000b: Disabled (default) 00000001b: DQS timer stops automatically at the 16th clock after timer start 00000010b: DQS timer stops automatically at the 32nd clock after timer start 00000011b: DQS timer stops automatically at the 48th clock after timer start 00000100b: DQS timer stops automatically at the 64th clock after timer start 00111111b: DQS timer stops automatically at the (63 × 16)th clock after timer start 01XXXXXXb: DQS timer stops automatically at the 2048th clock after timer start 10XXXXXXb: DQS timer stops automatically at the 4096th clock after timer start 11XXXXXXb: DQS timer stops automatically at the 8192nd clock after timer start Note: 1. MPC command with OP[6:0] = 1001101b (STOP DQS INTERVAL OSCILLATOR) stops the DQS interval timer in the case of MR23 OP[7:0] = 00000000b. 2. MPC command with OP[6:0] = 1001101b (STOP DQS INTERVAL OSCILLATOR) is illegal with valid nonzero values in MR23 OP[7:0].

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 45/300 MR24 Register Information (MA[5:0] = 18h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 TRR mode TRR mode BAn Unlimited MAC MAC value MR24 Register Information Feature Type OP Definition Note MAC value Read OP[2:0] 000b: Unknown (OP[3] = 0) or unlimited (OP[3] = 1) 001b: 700K 010b: 600K 011b: 500K 100b: 400K 101b: 300K 110b: 200K 111b: Reserved 1, 2 Unlimited MAC Read OP[3] 0b: OP[2:0] defines the MAC value 1b: Unlimited MAC value 2, 3 TRR mode BAn Write OP[6:4] 000b: Bank 0 001b: Bank 1 010b: Bank 2 011b: Bank 3 100b: Bank 4 101b: Bank 5 110b: Bank 6 111b: Bank 7 TRR mode Write OP[7] 0b: Disabled (default) 1b: Enabled Note: 1. Unknown means that the device is not tested for tMAC and pass/fail values are unknown. Unlimited means that there is no restriction on the number of activates between refresh windows. 2. There is no restriction to the number of activates. 3. MR24 OP[2:0] set to 000b.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 46/300 MR25 Register Information (MA[5:0] = 19h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 MR25 Register Information Feature Type OP Definition PPR resources Read-only OP[7:0] 0b: PPR resource is not available 1b: PPR resource is available Note: 1. When OP[n] = 0, there is no PPR resource available for that bank. When OP[n] = 1, there is a PPR resource available for that bank, and PPR can be initiated by the controller. MR26:29 Register Information (MA[5:0] = 1Ah–1Dh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Reserved for future use

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 47/300 MR30 Register Information (MA[5:0] = 1Eh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Valid 0 or 1 MR30 Register Information Feature Type OP Definition SDRAM will ignore Write-only OP[7:0] Don't care Note: 1. This register is reserved for testing purposes. The logical data values written to OP[7:0] will have no effect on SDRAM operation; however, timings need to be observed as for any other MR access command. MR31 Register Information (MA[5:0] = 1Fh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Reserved for future use MR32 Register Information (MA[5:0] = 20h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQ calibration pattern A (default = 5Ah) MR32 Register Information Feature Type OP Definition Note Return DQ calibration pattern MR32 + MR40 Write-only OP[7:0] Xb: An MPC command issued with OP[6:0] = 1000011b causes the device to return the DQ calibration pattern contained in this register and (followed by) the contents of MR40. A default pattern 5Ah is loaded at power-up or reset, or the pattern may be overwritten with a MRW to this register. The contents of MR15 and MR20 will invert the R32/MR40 data pattern for a given DQ (see MR15/ MR20 for more information). 1–3 Note: 1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0] when read DQ calibration is initiated via an MPC command. The pattern is transmitted serially on each data lane and organized little endian such that the low-order bit in a byte is transmitted first. If the data pattern is 27H, the first bit transmitted is a 1 followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111. 2. MR15 and MR20 may be used to invert the MR32/MR40 d ata pattern on the DQ pins. See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins. 3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3 OP[6]. 4. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3 OP[6].

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 48/300 MR33:38 Register Information (MA[5:0] = 21h–26h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Do not use MR39 Register Information (MA[5:0] = 27h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Valid 0 or 1 MR39 Register Information Feature Type OP Definition SDRAM will ignore Write-only OP[7:0] Don't care Note: 1. This register is reserved for testing purposes. The logical data values written to OP[7:0] will have no effect on SDRAM operation; however, timings need to be observed as for any other MR access command. MR40 Register Information (MA[5:0] = 28h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQ calibration pattern B (default = 3Ch) MR40 Register Information Feature Type OP Definition Note Return DQ calibration pattern MR32 + MR40 Write-only OP[7:0] Xb: A default pattern 3Ch is loaded at power-up or reset, or the pattern may be overwritten with a MRW to this register. See MR32 for more information. 1, 2, 3 Note: 1. The pattern contained in MR40 is concatenated to the end of MR32 and transmitted on DQ[15:0] and DMI[1:0] when read DQ calibration is initiated via an MPC command. The pattern is transmitted serially on each data lane and organized little endian such that the low-order bit in a byte is transmitted first. If the data pattern in MR40 is 27H, the first bit transmitted will be a 1, followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111. 2. MR15 and MR20 may be used to invert the MR32/MR40 data patter ns on the DQ pins. See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins. 3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3 OP[6]. 4. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3 OP[6].

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 49/300 MR41:47 Register Information (MA[5:0] = 29h–2Fh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Do not use MR48:63 Register Information (MA[5:0] = 30h–3Fh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Reserved for future use Commands and Timing Commands transmitted on the CA bus are encoded into two parts and are latched on two consecutive rising edges of the clock. This is called 2-tick CA capture because each command requires two clock edges to latch and decode the entire command. Truth Tables Truth tables provide complementary information to the state diagram. They also clarify device behavior and applicable restrictions when considering the actual state of the banks. Unspecified operations and timings are illegal. To ensure proper operation after an illegal event, the device must be either reset by asserting the RESET_n command or powered down and then restarted using the specified initialization sequence before normal operation can continue. CKE signal has to be held HIGH when the commands listed in the command truth table input.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 50/300 Command Truth Table Commands are transmitted to the device across a six -lane interface and use CK, CKE, and CS to control the capture of transmitted data OP7 OP6 SDR CA Pins CK Edge Note CA0 CA1 CA2 CA3 CA4 CA5 MRW-1 H L H H L L OP7 1,11 L MA0 MA1 MA2 MA3 MA4 MA5 MRW-2 H L H H L H OP6 1,11 L OP0 OP1 OP2 OP3 OP4 OP5 MRR-1 H L H H H L V 1,2,12 L MA0 MA1 MA2 MA3 MA4 MA5 REFRESH (all/per bank) H L L L H L AB 1,2,3,4 L BA0 BA1 BA2 V V V ENTER SELF REFRESH H L L L H H V 1,2 L V ACTIVATE-1 H H L R12 R13 R14 R15 1,2,3,11 L BA0 BA1 BA2 R16 R10 R11 ACTIVATE-2 H H H R6 R7 R8 R9 1,11 L R0 R1 R2 R3 R4 R5 WRITE-1 H L L H L L BL 1,2,3,6,7,9 L BA0 BA1 BA2 V C9 AP EXIT SELF REFRESH H L L H L H V 1, 2 L V MASK WRITE-1 H L L H H L BL 1, 2, 3, 5, 6, 7, 9 L BA0 BA1 BA2 V C9 AP RFU H L L H H H V 1, 2 L V RFU H L H L H L V 1, 2 L V RFU H L H L H H V 1, 2 L V READ-1 H L H L L L BL 1, 2, 3, 6, 7, 9 L BA0 BA1 BA2 V C9 AP CAS-2 (WRITE-2, MASKED WRITE-2, READ-2, MRR-2, MPC (except NOP) H L H L L H C8 1,8,9 L C2 C3 C4 C5 C6 C7 PRECHARGE (all/per bank) H L L L L H AB 1, 2, 3, 4 L BA0 BA1 BA2 V V V MPC (TRAIN, NOP) H L L L L L OP6 1, 2,13 L OP0 OP1 OP2 OP3 OP4 OP5 DESELECT L X 1,2

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 51/300 Note: 1. All commands except for DESELECT are two clock cycles and are defined by the current state of CS and CA[5:0] at the rising edge of the clock. DESELECT command is one clock cycle and is not latched by the device. 2. V = H or L (a defined logic level); X = "Don't Care," in which case CS, CK_t, CK_c, and CA[5:0] can be floated. 3. Bank addresses BA[2:0] determine which bank is to be operated upon. 4. AB HIGH during PRECHARGE or REFRESH commands indicate the command must be ap plied to all banks, and the bank addresses are "Don't Care." 5. MASK WRITE-1 command only supports BL16. For MASK WRITE -1 commands, CA5 must be driven LOW on the first rising clock cycle (R1). 6. AP HIGH during a WRITE -1, MASK WRITE -1, or READ -1 command indicate s that an auto precharge will occur to the bank the command is operating on. AP LOW indicates that no auto precharge will occur and the bank will remain open upon completion of the command. 7. When enabled in the mode register, BL HIGH during a WRITE -1, MASK-WRITE-1, or READ -1 command indicates the burst length should be set on-the-fly to BL = 32; BL LOW during one of these commands indicates the burst length should be set on-the-fly to BL = 16. If on-the-fly burst length is not enabled in the mode register, this bit should be driven to a valid level and is ignored by the device. 8. For CAS -2 commands (WRITE -2, MASK WRITE -2, READ -2, MRR-2, or MPC (only WRITE - FIFO, READ -FIFO, and READ DQ CALIBRATION)), C[1:0] are not transmitted on the CA [5:0] bus and are assumed to be zero. Note that for CAS-2 WRITE-2 or CAS-2 MASK WRITE-2 command, C[3:2] must be driven LOW. 9. WRITE-1, MASK-WRITE-1, READ-1, MODE REGISTER READ-1, or MPC (only WRITE -FIFO, READ-FIFO, and READ DQ CALIBRATION) command must be immediately followed by CAS -2 command consecutively without any other command in between. WRITE-1, MASK WRITE-1, READ-1, MRR-1, or MPC (only WRITE-FIFO, READ-FIFO, and READ DQ CALIBRA- TION) command must be issued first before issuing CAS-2 command. MPC (only START and STOP DQS OSCILLATOR, ZQCAL START and LATCH) commands do not require CAS-2 command; they require two additional DES or NOP commands consecutively before issuing any other commands. 10. The ACTIVATE-1 command must be followed by the ACTIVATE -2 command consecutively without a ny other command between them. The ACTIVATE-1 command must be issued prior to the ACTIVATE -2 command. When the ACTIVATE-1 command is issued, the ACTIVATE-2 command must be issued before issuing another ACTIVATE-1 command. 11. The MRW-1 command must be followed by the MRW -2 command consecutively without any other command between them. The MRW-1 command must be issued prior to the MRW-2 command. 12. The MRR-1 command must be followed by the CAS -2 command consecutively without any other commands between them. The MRR-1 command must be issued prior to the CAS-2 command. 13. The MPC command for READ or WRITE TRAINING operations must be followed by the CAS -2 command consecutively without any other commands between them. The MPC command must be issued prior to the CAS-2 command.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 52/300 ACTIVATE Command The ACTIVATE command must be executed before a READ or WRITE command can be issued. The ACTIVATE command is issued in two parts: The bank and upper-row ad- dresses are entered with activate-1 and the lower-row addresses are entered with ACTIVATE-2. ACTIVATE-1 and ACTIVATE-2 are executed by strobing CS HIGH while setting CA[5:0] at valid levels (see Command table) at the rising edge of CK. The bank addresses (BA[2:0]) are used to select the desired bank. The row addresses (R[15:0]) are u sed to determine which row to activate in the selected bank. The ACTIVATE-2 command must be applied before any READ or WRITE operation can be executed. The device can accept a READ or WRITE command at time tRCD after the ACTIVATE-2 command is sent. After a bank has been activated, it must be precharged to close the active row before another ACTIVATE-2 command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP , respectively. The minimum time interval between successive ACTIVATE-2 commands to the same bank is determined by the row cycle time of the device ( tRC). The minimum time interval between ACTIVATE-2 commands to different banks is tRRD. Certain restrictions must be observed for bank ACTIVATE and REFpb operations.  Four-activate window (tFAW): No more than 4 banks may be activated (or refreshed, in the case of REFpb) per channel in a rolling tFAW window. Convert to clocks by dividing tFAW[ns] by tCK[ns] and rounding up to the next integer value. As an example of the rolling window, if RU[(tFAW/tCK)] is 64 clocks, and an ACTIVATE command is issued on clock N, no more than three additional ACTIVATE commands may be issued between clock N + 1 and N + 63. REFpb also counts as bank activation for the purposes of tFAW.  8-bank per channel, precharge all banks (AB) allowance: tRP for a PRECHARGE ALL BANKS command for an 8 -bank device must equal tRPab, which is greater than tRPpb. ACTIVATE Command Note: 1. APRECHARGE command uses tRPab timing for all -bank precharge and tRPpb timing for single -bank precharge. In this figure, tRP is used to denote either all-bank precharge or a single-bank precharge. tCCD = MIN, 1.5nCK postamble, 533 MHz < clock frequency ≤ 800 MHz, ODT worst timing case.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 53/300 tFAW Timing Note: 1. REFpb may be substituted for one of the ACTIVATE commands for the purposes of tFAW. Read and Write Access Modes After a bank has been activated, a READ or WRITE command can be executed. This is accomplished by asserting CKE asynchronously, with CS and CA[5:0] set to the proper state (see Command Truth Table) on the rising edge of CK. The device provides a fast colum n access operation. A single READ or WRITE command will initiate a burst READ or WRITE operation, where data is transferred to/from the device on successive clock cycles. Burst interrupts are not allowed; however , the optimal burst length may be set on-the-fly (see Command Truth Table). Preamble and Postamble The DQS strobe for the device requires a preamble prior to the first latching edge (the rising edge of DQS_t with data valid), and it requires a postamble after the last latching edge. The preamble and postamble options are set via MODE REGISTER WRITE commands. The read preamble is two tCK in length and is either static or has one clock toggle before the first latching edge. The read preamble option is enabled via MRW to MR1 OP[3] (0 = Static; 1 = Toggle). The read postamble has a programmable option to extend the postamble by 1nCK (tRPSTE). The extended postamble option is enabled via MRW to MR1 OP[7] (0 = 0.5nCK; 1 = 1.5nCK).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 54/300 DQS Read Preamble and Postamble – Toggling Preamble and 0.5nCK Postamble Note: 1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK. 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tRPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tRPRE. DQS Read Preamble and Postamble – Static Preamble and 1.5nCK Postamble Note: 1. BL = 16, Preamble = Static, Postamble = 1.5nCK (extended). 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tRPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tRPRE.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 55/300 DQS Write Preamble and Postamble – 0.5nCK Postamble Note: 1. BL = 16, Postamble = 0.5nCK. 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tWPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tWPRE.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 56/300 DQS Write Preamble and Postamble – 1.5nCK Postamble Note: 1. BL = 16, Postamble = 1.5nCK. 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tWPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tWPRE.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 57/300 Burst READ Operation A burst READ command is initiated with CKE, CS, and CA[5:0] asserted to the proper state on the rising edge of CK, as defined by the Command Truth Table. The command address bus inputs determine the starting column address for the burst. The two loworder address bits are not transmitted on the CA bus and are implied to be 0; therefore, the starting burst address is always a multiple of four (that is, 0x0, 0x4, 0x8, 0xC). The READ latency (RL) is defined from the last rising edge of the clock that completes a READ command (for example, the second rising edge of the CAS-2 command) to the rising edge of the clock from which the tDQSCK delay is measured. The first valid data is available RL × tCK + tDQSCK + tDQSQ after the rising edge of clock that completes a READ command. The data strobe output is driven tRPRE before the first valid rising strobe edge. The first data bit of the burst is synchronized with the first valid (post -preamble) rising edge of the data strobe. Each subsequent data -out appears on each DQ pin, edge-aligned with the data strobe. At the end of a burst, the D QS signals are driven for another half cycle postamble, or for a 1.5-cycle postamble if the programmable postamble bit is set in the mode register. The RL is programmed in the mode registers. Pin timings for the data strobe are measured relative to the cross-point of DQS_t and DQS_c. Burst Read Timing Note: 1. BL = 32 for column n, BL = 16 for column m, RL = 14, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: V SSQ termination. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 58/300 Burst Read Followed by Burst Write or Burst Mask Write Note: 1. BL = 16, Read preamble = Toggle, Read postamble = 0.5nCK, Write preamble = 2nCK, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DOUT n = data-out from column n and DIN n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Seamless Burst Read Note: 1. BL = 16, tCCD = 8, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 59/300 Read Timing Read Timing Note: 1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK. 2. DQS, DQ, and DMI terminated VSSQ. 3. Output driver does not turn on before an endpoint of tLZ(DQS) and tLZ(DQ). 4. Output driver does not turn off before an endpoint of tHZ(DQS) and tHZ(DQ).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 60/300 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ). This section shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single ended. tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) tLZ(DQS) Method for Calculating Transitions and Endpoint Note: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 2. Termination condition for DQS_t and DQS_C = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual V OH value for tHZ and tLZ measurements.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 61/300 tHZ(DQS) Method for Calculating Transitions and Endpoint Note: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 2. Termination condition for DQS_t and DQS_C = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 62/300 Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements Measured Parameter Measured Parameter Symbol Vsw1 Vsw2 Unit DQS_c Low-Z time from CK_t, CK_c tLZ(DQS) 0.4 × VOH 0.6 × VOH V DQS_c High-Z time from CK_t, CK_c tHZ(DQS) 0.4 × VOH 0.6 × VOH tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) tLZ(DQ) Method for Calculating Transitions and Endpoint Note: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 2. Termination condition for DQ and DMI = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 63/300 tHZ(DQ) Method for Calculating Transitions and Endpoint Note: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ × 0.5. 1. Termination condition for DQ and DMI = 50 ohms to VSSQ. 2. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual V OH value for tHZ and tLZ measurements. Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements Measured Parameter Measured Parameter Symbol Vsw1 Vsw2 Unit DQ Low-Z time from CK_t, CK_c tLZ(DQ) 0.4 × VOH 0.6 × VOH V DQ High-Z time from CK_t, CK_c tHZ(DQ) 0.4 × VOH 0.6 × VOH

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 64/300 Burst WRITE Operation A burst WRITE command is initiated with CKE, CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the Command Truth Table. Column addresses C[3:2] should be driven LOW for burst WRITE commands, and column addresses C[1:0] are not transmitted on the CA bus and are assumed to be ze ro so that the starting column burst address is always aligned with a 32 -byte boundary. The WRITE latency (WL) is defined from the last rising edge of the clock that completes a WRITE command (for example, the second rising edge of the CAS-2 command) to the rising edge of the clock from which tDQSS is measured. The first valid latching edge of DQS must be driven WL × tCK + tDQSS after the rising edge of clock that completes a WRITE command. The device uses an unmatched DQS DQ path for lower power, so the DQS strobe must arrive at the SDRAM ball prior to the DQ signal by tDQS2DQ. The DQS strobe output must be driven tWPRE before the first valid rising strobe edge. The tWPRE preamble is require d to be 2 × tCK at any speed ranges. The DQS strobe must be trained to arrive at the DQ pad latch center-aligned with the DQ data. The DQ data must be held for TdiVW, and the DQS must be periodically trained to stay roughly centered in the TdiVW. Burst data is captured by the SDRAM on successive edges of DQS until the 16 - or 32-bit data burst is complete. The DQS strobe must remain active (toggling) for tWPST (write postamble) after the completion of the burst WRITE. After a burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the same bank can be issued. Signal input timings are measured relative to the cross point of DQS_t and DQS_c.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 65/300 Burst WRITE Operation Note: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n. 3. tWR starts at the rising edge of CK after the last latching edge of DQS. 4. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 66/300 Burst Write Followed by Burst Read Note: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n. 3. The minimum number of clock cycles from the burst WRITE command to the burst READ command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)]. 4. tWTR starts at the rising edge of CK after the last latching edge of DQS. 5. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 67/300 Write Timing Write Timing Note: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 68/300 tWPRE Calculation for ATE (Automatic Test Equipment) Method for Calculating tWPRE Transitions and Endpoints Note: 1. Termination condition for DQS_t, DQS_c, DQ, and DMI = 50 ohms to VSSQ. Method for Calculating tWPRE Transitions and Endpoints Measured Parameter Measured Parameter Symbol Vsw1 Vsw2 Unit DQS_t, DQS_c differential write preamble tWPRE VIHL_AC × 0.3 VIHL_AC × 0.7 V

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 69/300 tWPST Calculation for ATE (Automatic Test Equipment) Method for Calculating tWPST Transitions and Endpoints Note: 1. Termination condition for DQS_t, DQS_c, DQ, and DMI = 50 ohms to VSSQ. 2. Write postamble: 0.5tCK 3. The method for calculating differential pulse widths for 1.5tCK postamble is same as 0.5tCK postamble. Method for Calculating tWPRE Transitions and Endpoints Measured Parameter Measured Parameter Symbol Vsw1 Vsw2 Unit DQS_t, DQS_c differential write preamble tWPST -(VIHL_AC × 0.7) -(VIHL_AC × 0.3) V

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 70/300 MASK WRITE Operation The device requires that WRITE operations that include a byte mask anywhere in the burst sequence must use the MASK WRITE command. This allows the device to implement efficient data protection schemes based on larger data blocks. The MASK WRITE-1 command is used to begin the operation, followed by a CAS-2 command. A MASKED WRITE command to the same bank cannot be issued until tCCDMW later, to allow the device to finish the internal READ -MODIFY-WRITE operation. One data- mask-invert (DMI) pin is provided per byte lane, and the data -mask-invert timings match data bit (DQ) timing. See Data Mask Invert for more information on the use of the DMI signal. MASK WRITE Command – Same Bank Note: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n. 3. Mask-write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16 -bit wide data for MASKED WRITE operation. 4. DES commands are shown for ease of illustration; other commands may be valid at these time.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 71/300 MASK WRITE Command – Different Bank Note: 1. BL = 16, DQ/DQS/DMI: VSSQ termination. 2. DIN n = data-in to column n. 3. Mask-write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16 -bit wide data for MASKED WRITE operation. 4. DES commands are shown for ease of illustration; other commands may be valid at these time.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 72/300 Mask Write Timing Constraints for BL16 Same Bank (ODT Disabled) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE ACTIVE Illegal RU(tRCD/tCK) RU(tRCD/tCK) RU(tRCD/tCK) RU(tRAS/tCK) READ (with BL = 16) Illegal 81 RL + RU (tDQSCK(MAX)/ tCK) + BL/2 - WL + tWPRE + RD(tRPST) RL + RU (tDQSCK(MAX)/ tCK) + BL/2 - WL + tWPRE + RD(tRPST) BL/2 + MAX{(8,RU(tRTP/ tCK)} - 8 READ (with BL = 32) Illegal 162 RL + RU (tDQSCK(MAX)/ tCK) + BL/2 - WL + tWPRE + RD(tRPST) RL + RU (tDQSCK(MAX)/ tCK) + BL/2 - WL + tWPRE + RD(tRPST) BL/2 + MAX{(8,RU(tRTP/ tCK)} - 8 WRITE (with BL = 16) Illegal WL + 1+ BL/2 + RU(tWTR/tCK) 81 tCCDMW3 WL + 1 + BL/2 + RU(tWR/tCK) WRITE (with BL = 32) Illegal WL + 1 + BL/2 + RU(tWTR/tCK) 162 tCCDMW + 84 WL + 1 + BL/2 + RU(tWR/tCK) MASK WRITE Illegal WL + 1 + BL/2 + RU(tWTR/tCK) tCCD tCCDMW3 WL + 1 + BL/2 + RU(tWR/tCK) PRECHARGE RU(tRP/tCK), RU(tRPab/tCK) Illegal Illegal Illegal 4 Note: 1. In the case of BL = 16, tCCD is 8 × tCK. 2. In the case of BL = 32, tCCD is 16 × tCK. 3. tCCDMW = 32 × tCK (4 × tCCD at BL = 16). 4. WRITE with BL = 32 operation is 8 × tCK longer than BL = 16.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 73/300 Different Bank (ODT Disabled) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE ACTIVE RU(tRRD/tCK) 4 4 4 22 READ (with BL = 16) 4 81 RL + RU (tDQSCK(MAX)/ tCK) + BL/2 - WL + tWPRE + RD(tRPST) RL + RU (tDQSCK(MAX)/ tCK) + BL/2 - WL + tWPRE + RD tRPST) READ (with BL = 32) 4 162 RL + RU (tDQSCK(MAX)/ tCK) + BL/2 - WL + tWPRE + RD(tRPST) RL + RU (tDQSCK(MAX)/ tCK) + BL/2 - WL + tWPRE + RD(tRPST) WRITE (with BL = 16) 4 WL + 1+ BL/2 + RU(tWTR/tCK) 81 81 22 WRITE (with BL = 32) 4 WL + 1 + BL/2 + RU(tWTR/tCK) 162 162 22 MASK WRITE 4 WL + 1 + BL/2 + RU(tWTR/tCK) 81 81 22 PRECHARGE 4 4 4 4 4 Note: 1. In the case of BL = 16, tCCD is 8 × tCK 2. In the case of BL = 32, tCCD is 16 × tCK

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 74/300 Same Bank (ODT Enabled) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE ACTIVE Illegal RU(tRCD/tCK) RU(tRCD/tCK) RU(tRCD/tCK) RU(tRAS/tCK) READ (with BL = 16) Illegal 81 RL + RU( tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) - ODTLon - RD( tODTon(MIN)/ tCK) RL + RU( tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) - ODTLon - RD( tODTon(MIN)/ tCK) BL/2 + MAX{(8,RU(tRTP/ tCK)} - 8 READ (with BL = 32) Illegal 162 RL + RU( tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) - ODTLon - RD( tODTon(MIN)/ tCK) RL + RU( tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) - ODTLon - RD( tODTon(MIN)/ tCK) BL/2 + MAX{(8,RU(tRTP/ tCK)} - 8 WRITE (with BL = 16) Illegal WL + 1+ BL/2 + RU(tWTR/tCK) 81 tCCDMW3 WL + 1 + BL/2 + RU(tWR/tCK) WRITE (with BL = 32) Illegal WL + 1 + BL/2 + RU(tWTR/tCK) 162 tCCDMW + 84 WL + 1 + BL/2 + RU(tWR/tCK) MASK WRITE Illegal WL + 1 + BL/2 + RU(tWTR/tCK) tCCD tCCDMW3 WL + 1 + BL/2 + RU(tWR/tCK) PRECHARGE RU(tRP/tCK), RU(tRPab/tCK) Illegal Illegal Illegal 4 Note: 1. In the case of BL = 16, tCCD is 8 × tCK. 2. In the case of BL = 32, tCCD is 16 × tCK. 3. tCCDMW = 32 × tCK (4 × tCCD at BL = 16). 4. WRITE with BL = 32 operation is 8 × tCK longer than BL = 16.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 75/300 Different Bank (ODT Enabled) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE ACTIVE RU(tRRD/tCK) 4 4 4 22 READ (with BL = 16) 4 81 RL + RU (tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) RL + RU (tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) READ (with BL = 32) 4 162 RL + RU( tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) - ODTLon - RD( tODTon(MIN)/ tCK) RL + RU( tDQSCK(MAX)/ tCK) + BL/2 + RD(tRPST) - ODTLon - RD( tODTon(MIN)/ tCK) WRITE (with BL = 16) 4 WL + 1+ BL/2 + RU(tWTR/tCK) 81 81 22 WRITE (with BL = 32) 4 WL + 1 + BL/2 + RU(tWTR/tCK) 162 162 22 MASK WRITE 4 WL + 1 + BL/2 + RU(tWTR/tCK) 81 81 22 PRECHARGE 4 4 4 4 4 Note: 1. In the case of BL = 16, tCCD is 8 × tCK. 2. In the case of BL = 32, tCCD is 16 × tCK.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 76/300 Data Mask and Data Bus Inversion (DBI [DC]) Function Data mask (DM) is supported for WRITE operations and the data bus inversion DBI (DC) is supported for READ, WRITE, MASK WRITE, MRR, and MRW operations. DM and DBI (DC) functions are supported with byte granularity. DBI (DC) for READ operations (READ, MRR) can be enabled or disabled via MR3 OP[6]. DBI (DC) for WRITE operations (WRITE, MASK WRITE, MRW) can be enabled or disabled via MR3 OP[7]. DM for MASK WRITE operations can be enabled or disabled via MR13 OP[5]. The device has one data mask inversion (DMI) pin per byte and a total of two DMI pins per channel. The DMI signal is a bidirectional DDR signal, is sampled with the DQ signals, and is electrically identical to a DQ signal. There are eight possible states for the device with the DM and DBI (DC) functions. Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations DM Function Write DBI (DC) Read DBI (DC) DMI Signal During WRITE During MASKED WRITE During READ During MPC[WRIT E-FIFO] During MPC[READ- FIFO] During MPC[READ DQ CAL] Disabled Disabled Disabled Don't Care1 Illegal1, 3 High-Z2 Don't Care1 High-Z2 High-Z2 Disabled Enabled Disabled DBI (DC)4 Illegal3 High-Z2 Train9 Train10 Train11 Disabled Disabled Enabled Don't Care1 Illegal3 DBI (DC)5 Train9 Train10 Train11 Disabled Enabled Enabled DBI (DC)4 Illegal3 DBI (DC)5 Train9 Train10 Train11 Enabled Disabled Disabled Don't Care6 DM7 High-Z2 Train9 Train10 Train11 Enabled Enabled Disabled DBI (DC)4 DBI (DC)8 High-Z2 Train9 Train10 Train11 Enabled Disabled Enabled Don't Care6 DM7 DBI (DC)5 Train9 Train10 Train11 Enabled Enabled Enabled DBI (DC)4 DBI (DC)8 DBI (DC)5 Train9 Train10 Train11 Note: 1. The DMI input signal is "Don’t Care." DMI input receivers are turned off. 2. DMI output drivers are turned off. 3. The MASK WRITE command is not allowed and is considered an illegal command when the DM function is disabled. 4. The DMI signal is treated as DBI and indicates whether the device needs to invert the write data received on DQ within a byte. The device inverts write data received on the DQ inputs if DMI is sampled HIGH and leaves the write data non-inverted if DMI is sampled LOW. 5. The device inverts read data on its DQ outputs associated within a byte and drives the DMI signal HIGH when more than four data bits = 1 within a given byte lane; otherwise, the device does not invert the read data and drives DMI signal LOW. 6. The device does not perform a MASK operation when it receives a WRITE (or MRW) command. During the WRITE burst, the DMI signal must be driven LOW. 7. The device requires an e xplicit MASKED WRITE command for all MASKED WRITE opera - tions. The DMI signal is treated as a data mask (DM) and indicates which bytes within a burst will be masked. When the DMI signal is sampled HIGH, the device masks that beat of the burst for the give n byte lane. All DQ input signals within a byte are "Don't Care" (either HIGH or LOW) when DMI is HIGH. When the DMI signal is sampled LOW, the device does not perform a MASK operation and data received on the DQ inputs is written to the array. 8. The device requires an explicit MASKED WRITE command for all MASKED WRITE operations. The device masks the write data received on the DQ inputs if five or more data bits = 1 on DQ[2:7] or DQ[10:15] (for lower byte or upper byte respectively) and the DMI signal is LOW . Otherwise, the device does not perform the MASK operation and treats it as a legal DBI pattern. The DMI signal is treated as a DBI signal, and data received on the DQ input is written to the array. 9. The DMI signal is treated as a training pattern. The device does not perform any MASK operation and does not invert write data received on the DQ inputs. 10. The DMI signal is treated as a training pattern. The device returns the data pattern written to the WRITE-FIFO. 11. The DMI signal is treated as a training pattern. For more information, see the Read DQ Calibration Training section.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 77/300 MASKED WRITE Command with Write DBI Enabled; DM Enabled Note: 1. N: Input data is written to DRAM cell. 2. I: Input data is inverted, then written to DRAM cell. 3. M: Input data is masked. The total count of 1 data bits on DQ[7:2] is equal to or greater than five. 4. Data mask (DM) is enable: MR13 OP [5] = 0, Data bus inversion (DBI) write is enable: MR3 OP[7] = 1.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 78/300 WRITE Command with Write DBI Enabled; DM Disabled Note: 1. N: Input data is written to DRAM cell. 2. I: Input data is inverted, then written to DRAM cell. 3. Data mask (DM) is disable: MR13 OP [5] = 1, Data bus inversion (DBI) write is enable: MR3 OP[7] = 1.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 79/300 WRITE and MASKED WRITE Operation DQS Control (WDQS Control) The device su pports WRITE and MASKED WRITE operations with the following DQS controls. Before and after WRITE and MASKED WRITE operations, DQS_t, and DQS_c are required to have sufficient voltage gap to make sure the write buffers operating normally without any risk of meta-stability. The device is supported by either of the two WDQS control modes below.  Mode 1: Read based control  Mode 2: WDQS_on / WDQS_off definition based control Regardless of ODT enable/disable, WDQS related timing described here does not allow any change of existing command timing constraints for all READ/WRITE operations. In case of any conflict or ambiguity on the command timing constraints caused by the specification here, the specification defined in the Timing Constraints for Training Commands table should have higher priority than WDQS control requirements. In order to prevent write preamble related failure, it is strongly recommended to support either of the two WDQS controls to the device. WDQS Control Mode 1 – Read-Based Control The device needs to be guaranteed the differential WDQS, but the differential WDQS can be controlled as described below. WDQS control requirements here can be ignored while differential read DQS is operated or while DQS hands over from read to write or vice versa. 1. When WRITE/MASKED WRITE command is issued, SoC makes the transition from driving DQS_c HIGH to driving differential DQS_t/DQS_c, followed by normal differential burst on DQS pins. 2. At the end of post amble of WRITE/MASKED WRITE burst, SoC resumes driving DQS_c HIGH through the subsequent states except for DQS toggling and DQS turn around time of WT-RD and RD-WT as long as CKE is HIGH. 3. When CKE is LOW, the state of DQS_t/DQS_c is allowed to be “Don’t Care.” WDQS Control Mode 1

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 80/300 WDQS Control Mode 2 – WDQS_On/Off After WRITE/MASKED WRITE command is issued, DQS_t and DQS_c required to be differential from WDQS_on, and DQS_t and DQS_c can be “Don’t Care” status from WDQS_off of WRITE/MASKED WRITE command. When ODT is enabled, WDQS_on and WDQS_off timing i s located in the middle of the operations. When host disables ODT, WDQS_on and WDQS_off constraints conflict with tRTW. The timing does not conflict when ODT is enabled because WDQS_on and WDQS_off timing is covered in ODTLon and ODTLoff. However, regardless of ODT on/off, WDQS_on/off timing below does not change any command timing constraints for all read and write operations. In order to prevent the conflict, WDQS_on/off requirement can be ignored where WDQS_on/off timing is overlapped with read operation period including READ burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD). In addition, the period during DQS toggling caused by read and write can be counted as WDQS_on/ off. Parameters  WDQS_on: The maximum delay from WRITE/MASKED WRITE command to differen- tial DQS_t and DQS_c  WDQS_off: The minimum delay for DQS_t and DQS_c differential input after the last WRITE/MASKED WRITE command  WDQS_Exception: The period where WDQS_on and WDQS_off timing is overlapped with READ operation or with DQS turn around (RD-WT, WT-RD) WDQS_Exception @ ODT disable = MAX(WL -WDQS_on + tDQSTA - tWPRE - n tCK, 0 tCK) where RD to WT command gap = tRTW(MIN)@ODT disable + n tCK WDQS_Exception @ ODT enable = tDQSTA WDQS_On/WDQS_Off Definition WRITE Latency nWR nRTP WDQS_On (Max) WDQS_Off (Min) Lower Frequency Limit (>) Upper Frequency Limit (≤) Set A Set B Set A Set B Set A Set B 4 4 6 8 0 0 15 15 10 266 6 8 10 8 0 0 18 20 266 533 8 12 16 8 0 6 21 25 533 800 10 18 20 8 4 12 24 32 800 1066 12 22 24 10 4 14 27 37 1066 1333 14 26 30 12 6 18 30 42 1333 1600 16 30 34 14 6 20 33 47 1600 1866 Note: 1. WDQS_on/off requirement can be ignored when WDQS_on/off timing is overlapped with READ operation period including READ burst period and tRPST or overlapped with turn-around time (RD-WT or WT-RD). 2. DQS toggling period caused by read and write can be counted as WDQS_on/off. WDQS_On/WDQS_Off Allowable Variation Range Min Max Unit WDQS_on –0.25 0.25 tCK(avg) WDQS_off –0.25 0.25 tCK(avg)

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 81/300 DQS Turn-Around Parameter Parameter Description Value Unit Note tDQSTA Turn-around time RDQS to WDQS for WDQS control case TBD – 1 Note: 1. tDQSTA is only applied to WDQS_exception case when WDQS Control. Except for WDQS Control, tDQSTA can be ignored. Burst WRITE Operation Note: 1. BL=16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DI n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. DRAM RTT is only applied when ODT is enabled (MR11 OP[2:0] is not 000b).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 82/300 Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Disable) Note: 1. BL = 16, Read preamble = Toggle, Read postamble = 0.5nCK, Write preamble = 2nCK, Write postamble = 0.5nCK. 2. DO n = data-out from column n, DI n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. WDQS_on and WDQS_off requirement can be ignored where WDQS_on/off timing is overlapped with READ operation period including READ burst period and tRPST or over- lapped with turn-around time (RD-WT or WT-RD).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 83/300 Burst READ Followed by Burst WRITE or Burst MASKED WRITE (ODT Enable) Note: 1. BL = 16, Read preamble = Toggle, Read postamble = 0.5nCK, Write preamble = 2nCK, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DO n = data-out from column n, DI n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. WDQS_on and WDQS_off requirement can be ignored where WDQS_on/off timing is overlapped with READ operation period including READ burst period and tRPST or over- lapped with turn-around time (RD-WT or WT-RD).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 84/300 Preamble and Postamble Behavior Preamble, Postamble Behavior in READ-to-READ Operations The following illustrations show the behavior of the device's read DQS_t and DQS_c pins during cases where the preamble, postamble, and/or data clocking overlap. DQS will be driven with the following priority 1. Data clocking edges will always be driven 2. Postamble 3. Preamble Essentially the data clocking, preamble, and postamble will be ordered such that all edges will be driven. Additional examples of seamless and borderline non-overlapping cases have been included for clarity.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 85/300 READ-to-READ Operations – Seamless READ Operations: tCCD = MIN, Preamble = Toggle, 1.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 86/300 READ-to-READ Operations – Consecutive Seamless READ: tCCD = MIN + 1, Preamble = Toggle, 1.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Consecutive READ: tCCD = MIN + 1, Preamble = Toggle, 0.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 87/300 Consecutive READ: tCCD = MIN + 1, Preamble = Static, 1.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Consecutive READ: tCCD = MIN + 1, Preamble = Static, 0.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 88/300 Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 1.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 0.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 89/300 Consecutive READ: tCCD = MIN + 2, Preamble = Static, 1.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Consecutive READ: tCCD = MIN + 2, Preamble = Static, 0.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 90/300 Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 1.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 0.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 91/300 Consecutive READ: tCCD = MIN + 3, Preamble = Static, 1.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Consecutive READ: tCCD = MIN + 3, Preamble = Static, 0.5nCK Postamble Note: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 92/300 WRITE-to-WRITE Operations – Seamless Seamless WRITE: tCCD = MIN, 0.5nCK Postamble Note: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n/m = data-in from column n and column m. 3. The minimum number of clock cycles from the burst WRITE command to the burst WRITE command for any bank is BL/2. 4. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 93/300 Seamless WRITE: tCCD = MIN, 1.5nCK Postamble, 533 MHz < Clock Frequency ≤ 800 MHz, ODT Worst Timing Case Note: 1. Clock frequency = 800 MHz, tCK(AVG) = 1.25ns. 2. BL = 16, Write postamble = 1.5nCK. 3. DIN n/m = data-in from column n and column m. 4. The minimum number of clock cycles from the burst WRITE command to the burst WRITE command for any bank is BL/2. 5. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 94/300 Seamless WRITE: tCCD = MIN, 1.5nCK Postamble Note: 1. BL = 16, Write postamble = 1.5nCK. 2. DIN n/m = data-in from column n and column m. 3. The minimum number of clock cycles from the burst WRITE command to the burst WRITE command for any bank is BL/2. 4. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 95/300 WRITE-to-WRITE Operations – Consecutive Consecutive WRITE: tCCD = MIN + 1, 0.5nCK Postamble Note: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Consecutive WRITE: tCCD = MIN + 1, 1.5nCK Postamble Note: 1. BL = 16, Write postamble = 1.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 96/300 Consecutive WRITE: tCCD = MIN + 2, 0.5nCK Postamble Note: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Consecutive WRITE: tCCD = MIN + 2, 1.5nCK Postamble Note: 1. BL = 16, Write postamble = 1.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 97/300 Consecutive WRITE: tCCD = MIN + 3, 0.5nCK Postamble Note: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Consecutive WRITE: tCCD = MIN + 3, 1.5nCK Postamble Note: 1. BL = 16, Write postamble = 1.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 98/300 Consecutive WRITE: tCCD = MIN + 4, 1.5nCK Postamble Note: 1. BL = 16, Write postamble = 1.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 99/300 PRECHARGE Operation The PRECHARGE command is used to precharge or close a bank that has been activated. The PRECHARGE command is initiated with CKE, CS, and CA[5:0] in the proper state (see Command Truth Table). The PRECHARGE command can be used to precharge each bank independently or all banks simultaneously. The all banks (AB) flag and the bank address bit are used to determine which bank(s) to precharge. The precharged bank(s) will be available for subsequent row access tRPab after an all-bank PRECHARGE command is issued, or tRPpb after a single-bank PRECHARGE command is issued. To ensure that the device can meet the instantaneous current demands, the row precharge time for an all -bank PRECHARGE ( tRPab) is longer than the per-bank precharge time (tRPpb). Precharge Bank Selection AB (CA[5], R1) BA2 (CA[2], R2) BA1 (CA[1], R2) BA0 (CA[0], R2) Precharged Bank 0 0 0 0 Bank 0 only 0 0 0 1 Bank 1 only 0 0 1 0 Bank 2 only 0 0 1 1 Bank 3 only 0 1 0 0 Bank 4 only 0 1 0 1 Bank 5 only 0 1 1 0 Bank 6 only 0 1 1 1 Bank 7 only

1 Don't Care Don't Care Don't Care All banks

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 100/300 Burst READ Operation Followed by Precharge The PRECHARGE command can be issued as early as BL/2 clock cycles after a READ command, but the PRECHARGE command cannot be issued until after tRAS is satisfied. A new bank ACTIVATE command can be issued to the same bank after the row precharge time (tRP) has elapsed. The minimum read-to-precharge time must also satisfy a minimum analog time from the second rising clock edge of the CAS-2 command. tRTP begins BL/2 - 8 clock cycles after the READ command. Burst READ Followed by Precharge – BL16, Toggling Preamble, 0.5nCK Postamble Burst READ Followed by Precharge – BL32, 2tCK, 0.5nCK Postamble

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 101/300 Burst WRITE Followed by Precharge A write recovery time (tWR) must be provided before a PRECHARGE command may be issued. This delay is referenced from the next rising edge of CK after the last valid DQS clock of the burst. Devices write data to the memory array in prefetch multiples (prefetch = 16). An internal WRITE operation can only begin after a prefetch group has been clocked; therefore, tWR starts at the prefetch boundaries. The minimum write -to-precharge time for commands to the same bank is WL + BL/2 + 1 + RU(tWR /tCK) clock cycles. Burst WRITE Followed by PRECHARGE – BL16, 2nCK Preamble, 0.5nCK Postamble

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 102/300 Auto Precharge Before a new row can be opened in an active bank, the active bank must be precharged using e ither the PRECHARGE command or the auto precharge (AP) function. When a READ or a WRITE command is issued to the device, the AP bit (CA5) can be set to enable the active bank to automatically begin precharge at the earliest possible moment during the burst READ or WRITE cycle. If AP is LOW when the READ or WRITE command is issued, the normal READ or WRITE burst operation is executed, and the bank remains active at the completion of the burst. If AP is HIGH when the READ or WRITE command is issued, the auto PRECHARGE function is engaged. This feature enables the PRECHARGE operation to be partially or completely hidden during burst READ cycles (dependent upon READ or WRITE latency), thus improving system performance for random data access.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 103/300 Burst READ With Auto Precharge If AP is HIGH when a READ command is issued, the READ with AUTO PRECHARGE function is engaged. The devices start an AUTO PRECHARGE operation on the rising edge of the clock at BL/2 after the second beat of the READ w/AP command, or BL/4 - 4 + RU(tRTP/tCK) clock cycles after the second beat of the READ w/AP command, whichever is greater. Following an AUTO PRECHARGE operation, an ACTIVATE command can be issued to the same bank if the following two conditions are both satisfied: 1. The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge began, and 2. The RAS cycle time (tRC) from the previous bank activation has been satisfied. Burst READ With Auto Precharge – BL16, Non-Toggling Preamble, 0.5nCK Postamble Burst READ With Auto Precharge – BL32, Toggling Preamble, 1.5nCK Postamble

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 104/300 Burst WRITE With Auto Precharge If AP is HIGH when a WRITE command is issued, the WRITE with AUTO PRECHARGE function is engaged. The device starts an auto precharge on the rising edge tWR cycles after the completion of the burst WRITE. Following a WRITE with AUTO PRECHARGE, an ACTIVATE command can be issued to the same bank if the following conditions are met: 1. The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge began, and 2. The RAS cycle time (tRC) from the previous bank activation has been satisfied. Burst WRITE With Auto Precharge – BL16, 2nCK Preamble, 0.5nCK Postamble

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 105/300 Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable From Command To Command Minimum Delay Between "From Command" and "To Command" Unit Note READ BL = 16 PRECHARGE (to same bank as READ) tRTP tCK 1, 6 PRECHARGE ALL tRTP tCK 1, 6 READ BL = 32 PRECHARGE (to same bank as READ) 8tCK + tRTP tCK 1, 6 PRECHARGE ALL 8tCK + tRTP tCK 1, 6 READ w/AP BL = 16 PRECHARGE (to same bank as READ w/AP) nRTP tCK 1, 10 PRECHARGE ALL nRTP tCK 1, 10 ACTIVATE (to same bank as READ w/AP) nRTP + tRPpb tCK 1, 8, 10 WRITE or WRITE w/AP (same bank) Illegal – MASK-WR or MASK-WR w/AP (same bank) Illegal – WRITE or WRITE w/AP (different bank) RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - WL + tWPRE tCK 3, 4, 5 MASK-WR or MASK-WR w/AP (different bank) RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - WL + tWPRE tCK 3, 4, 5 READ or READ w/AP (same bank) Illegal – READ or READ w/AP (different bank) BL/2 tCK 3 READ w/AP BL = 32 PRECHARGE (to same bank as READ w/AP) 8tCK + nRTP tCK 1, 10 PRECHARGE ALL 8tCK + nRTP tCK 1, 10 ACTIVATE (to same bank as READ w/AP) 8tCK + nRTP + tRPpb tCK 1, 8, 10 WRITE or WRITE w/AP (same bank) Illegal – MASK-WR or MASK-WR w/AP (same bank) Illegal – WRITE or WRITE w/AP (different bank) RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - WL + tWPRE tCK 3, 4, 5 MASK-WR or MASK-WR w/AP (different bank) RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - WL + tWPRE tCK 3, 4, 5 READ or READ w/AP (same bank) Illegal – READ or READ w/AP (different bank) BL/2 tCK 3 WRITE BL = 16 and 32 PRECHARGE (to same bank as WRITE) WL + BL/2 + tWR + 1 tCK 1, 7 PRECHARGE ALL WL + BL/2 + tWR + 1 tCK 1, 7

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 106/300 Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable (Continued) From Command To Command Minimum Delay Between "From Command" and "To Command" Unit Note MASK-WR BL = 16 PRECHARGE (to same bank as MASK-WR) WL + BL/2 + tWR + 1 tCK 1, 7 PRECHARGE ALL WL + BL/2 + tWR + 1 tCK 1, 7 WRITE w/AP BL = 16 and 32 PRECHARGE (to same bank as WRITE w/AP) WL + BL/2 + nWR + 1 tCK 1, 11 PRECHARGE ALL WL + BL/2 + nWR + 1 tCK 1, 11 ACTIVATE (to same bank as WRITE w/AP) WL + BL/2 + nWR + 1 + tRPpb tCK 1, 8, 11 WRITE or WRITE w/AP (same bank) Illegal – READ or READ w/AP (same bank) Illegal – WRITE or WRITE w/AP (different bank) BL/2 tCK 3 MASK-WR or MASK-WR w/AP (different bank) BL/2 tCK 3 READ or READ w/AP (different bank) WL + BL/2 + tWTR + 1 tCK 3, 9 MASK-WR w/AP BL = 16 PRECHARGE (to same bank as MASK-WR w/AP) WL + BL/2 + nWR +1 tCK 1, 11 PRECHARGE ALL WL + BL/2 + nWR + 1 tCK 1, 11 ACTIVATE (to same bank as MASK-WR w/AP) WL + BL/2 + nWR + 1 + tRPpb tCK 1, 8, 11 WRITE or WRITE w/AP (same bank) Illegal – 3 MASK-WR or MASK-WR w/AP (same bank) Illegal – 3 WRITE or WRITE w/AP (different bank) BL/2 tCK 3 MASK-WR or MASK-WR w/AP (different bank) BL/2 tCK 3 READ or READ w/AP (same bank) Illegal – 3 READ or READ w/AP (different bank) WL + BL/2 + tWTR + 1 tCK 3, 9 PRECHARGE PRECHARGE (to same bank as PRECHARGE) 4 tCK 1 PRECHARGE ALL 4 tCK 1 PRECHARGE ALL PRECHARGE 4 tCK 1 PRECHARGE ALL 4 tCK 1

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 107/300 Note: 1. For a given bank, the precharge period should be counted from the latest PRECHARGE command, whether per -bank or all-bank, issued to that bank. The precharge period is satisfied tRP after that latest PRECHARGE command. 2. Any command issued during the minimum delay time as specified in the table above is illegal. 3. After READ w/AP, seamless READ operations to different banks are supported. After WRITE w/AP or MASK -WR w/AP, seamless WRITE operations to different banks are supported. READ, WRITE, and MASK -WR operations may not be truncated or interrupted. 4. tRPST values depend on MR1 OP[7] respectively. 5. tWPRE values depend on MR1 OP[2] respectively. 6. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tRTP (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup(tRTP [ns]/tCK [ns]). 7. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup(tWR [ns]/tCK [ns]). 8. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tRPpb (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup(tRPpb [ns]/tCK [ns]). 9. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tWTR (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup(tWTR [ns]/tCK [ns]). 10. For READ w/AP the value is nRTP , which is defined in mode register 2. 11. For WRITE w/AP the value is nWR, which is defined in mode register 1. Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Enable From Command To Command Minimum Delay Between "From Command" and "To Command" Unit Note READ w/AP BL = 16 WRITE or WRITE w/AP (different bank) RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1 tCK 2, 3 MASK-WR or MASK-WR w/AP (different bank) RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1 tCK 2, 3 READ w/AP BL = 32 WRITE or WRITE w/AP (different bank) RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1 tCK 2, 3 MASK-WR or MASK-WR w/AP (different bank) RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1 tCK 2, 3 Note: 1. The rest of the timing about PRECHARGE and AUTO PRECHARGE is same as DQ ODT is disable case. 2. After READ w/AP, seamless read operations to different banks are supported. READ, WRITE, and MASK -WR operations may not be truncated or interrupted. 3. tRPST values depend on MR1 OP[7] respectively.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 108/300 RAS Lock Function READ with AUTO PRECHARGE or WRITE/MASK WRITE with AUTO PRECHARGE commands may be issued after tRCD has been satisfied. The LPDDR4 SDRAM RAS lockout feature will schedule the internal precharge to assure that tRAS is satisfied. tRC needs to be satisfied prior to issuing subsequent ACTIVATE commands to the same bank. The figure below shows example of RAS lock function. Command Input Timing with RAS Lock Note: 1. tCK (AVG) = 0.938ns, Data rate = 2133 Mbps, tRCD(MIN) = MAX(18ns, 4nCK), tRAS(MIN) = MAX(42ns, 3nCK), nRTP = 8nCK, BL = 32. 2. tRCD = 20nCK comes from roundup(18ns/0.938ns). 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 109/300 Delay Time From WRITE-to-READ with Auto Precharge In the case of WRITE command followed by READ with AUTO PRECHARGE, controller must satisfy tWR for the WRITE command before initiating the device internal auto -precharge. It means that ( tWTR + nRTP) should be equal or longer than (tWR) when BL setting is 1 6, as well as ( tWTR + nRTP + 8nCK) should be equal or longer than (tWR) when BL setting is 32. Refer to the following figure for details. Delay Time From WRITE-to-READ with Auto Precharge Note: 1. Burst length at read = 16. 2. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 110/300 REFRESH Command The REFRESH command is initiated with CS HIGH, CA0 LOW, CA1 LOW, CA2 LOW, CA3 HIGH and CA4 LOW at the first rising edge of clock. Per bank REFRESH is initiated with CA5 LOW at the first rising edge of the clock. The all-bank REFRESH is initiated with CA5 HIGH at the first rising edge of clock. A per bank REFRESH command (REFpb) is performed to the bank address as transferred on CA0, CA1, and CA2 on the second rising edge of the clock. Bank address BA0 is transferred on CA0, bank address BA1 is transferred on CA1, and bank address BA2 is transferred on CA2. A per bank REFRESH command (REFpb) to the eight banks can be issued in any order. For example, REFpb commands may be issue d in the following or - der: 1 -3-0-2-4-7-5-6. After the eight banks have been refreshed using the per bank REFRESH command, the controller can send another set of per bank REFRESH commands in the same order or a different order. One possible order can be a sequential round robin: 0-1-2-3-4-5-6-7. It is illegal to send a per bank REFRESH command to the same bank unless all eight banks have been refreshed using the per bank REFRESH com- mand. The count of eight REFpb commands starts with the first REFpb command after a synchronization event. The bank count is synchronized between the controller and the device by resetting the bank count to zero. Synchronization can occur upon reset procedure or at every exit from self refresh. The REFab command also synchronizes the counter between the controller and the device to zero. The device can be placed in self refresh, or a REFab command can be issued at any time without cycling through all eight banks using per bank REFRESH command. After the bank count is synchronized to zero, the controller can issue per bank REFRESH commands in any order, as described above. A REFab command issued when the bank counter is not zero will reset the bank counter to zero and the device will perform refreshes to all banks as indicated by t he row counter. If another REFRESH command (REFab or REFpb) is issued after the REFab command then it uses an incremented value of the row counter. The table below shows examples of both bank and refresh counter increment behavior.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 111/300 Bank and Refresh Counter Increment Behavior # Command BA2 BA1 BA1 Refresh Bank # Bank Counter # Ref. Conter # (Row Address #)

0 Reset, SRX, or REFab To 0 –

1 REFpb 0 0 0 0 0 to 1

2 REFpb 0 0 1 1 1 to 2

3 REFpb 0 1 0 2 2 to 3

4 REFpb 0 1 1 3 3 to 4

5 REFpb 1 0 0 4 4 to 5

6 REFpb 1 0 1 5 5 to 6

7 REFpb 1 1 0 6 6 to 7

8 REFpb 1 1 1 7 7 to 0

9 REFpb 1 1 0 6 0 to 1

10 REFpb 1 1 1 7 1 to 2

11 REFpb 0 0 1 1 2 to 3

12 REFpb 0 1 1 3 3 to 4

13 REFpb 1 0 1 5 4 to 5

14 REFpb 0 1 0 2 5 to 6

15 REFpb 0 0 0 0 6 to 7

16 REFpb 1 0 0 4 7 to 0

17 REFpb 0 0 0 0 0 to 1

n + 2 18 REFpb 0 0 1 1 1 to 2

19 REFpb 0 1 0 2 2 to 3

20 REFab V V V 0 to 7 To 0 n + 2

21 REFpb 1 1 0 6 0 to 1

22 REFpb 1 1 1 7 1 to 2

A bank must be idle before it can be refreshed. The controller must track the bank being refreshed by the per bank REFRESH command. The REFpb command must not be issued to the device until the following conditions have been met:  tRFCab has been satisfied after the prior REFab command  tRFCpb has been satisfied after the prior REFpb command  tRP has been satisfied after the prior PRECHARGE command to that bank  tRRD has been satisfied after the prior ACTIVATE command (for example, after activating a row in a different bank than the one affected by the REFpb command) The target bank is inaccessible during per bank REFRESH cycle time ( tRFCpb). However, other banks within the device are accessible and can be addressed during the cycle. During the REFpb operation, any of the banks other than the one be ing refreshed can be maintained in an active state or accessed by a READ or a WRITE command. When the per bank REFRESH cycle has completed, the affected bank will be in the idle state. After issuing REFpb, the following conditions must be met:  tRFCpb must be satisfied before issuing a REFab command  tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank  tRRD must be satisfied before issuing an ACTIVATE command to a different bank  tRFCpb must be satisfied before issuing another REFpb command

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 112/300 An all-bank REFRESH command (REFab) issues a REFRESH command to every bank in a channel. All banks must be idle when REFab is issued (for example, by issuing a PRECHARGE ALL command prior to issuing an all -bank REFRESH command). The REFab command must not be issued to the device until the following conditions have been met:  tRFCab has been satisfied following the prior REFab command  tRFCpb has been satisfied following the prior REFpb command  tRP has been satisfied following the prior PRECHARGE command When an all-bank REFRESH cycle has completed, all banks will be idle. After issuing REFab:  RFCab latency must be satisfied before issuing an ACTIVATE command,  RFCab latency must be satisfied before issuing a REFab or REFpb command REFRESH Command Timing Constraints Symbol Minimum Delay From... To Note tRFCab REFab REFab ACTIVATE command to any bank REFpb tRFCpb REFpb REFab ACTIVATE command to same bank as REFpb REFpb tRRD REFpb ACTIVATE command to a different bank than REFpb ACTIVATE REFpb 1 ACTIVATE command to a different bank than the prior ACTIVATE command Note: 1. A bank must be in the idle state before it is refreshed; therefore, REFab is prohibited following an ACTIVATE command. REFpb is supported only if it affects a bank that is in the idle state. All-Bank REFRESH Operation

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 113/300 Per Bank REFRESH Operation Note: 1. In the beginning of this example, the REFpb bank is pointing to bank 0. 2. Operations to banks other than the bank being refreshed are supported during the tRFCpb period. In general, a REFRESH command needs to be issued to the device regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be postponed during operation of the device, but at no point in time are more than a total of eight REFRESH commands allowed to be postponed. And a maximum number of pulled -in or postponed REF command is dependent on refresh rate. It is described in the table below. In the case where eight REFRESH commands are postponed in a row, the resulting maximum interval between the surrounding REFRESH commands is limited to 9 × tREFI. A maximum of eight additional REFRESH commands can be issued in advance (pulled in), with each one reducing the number of regular REFRESH commands required later by one. Note that pulling in more than eight REFRESH commands in advance does not reduce the number of regular REFRESH commands required la ter; therefore, the resulting maximum interval between two surrounding REFRESH commands is limited to 9 × tREFI. At any given time, a maximum of 16 REFRESH commands can be issued within 2 × tREFI. Self refresh mode may be entered with a maximum of eight RE FRESH commands being postponed. After exiting self refresh mode with one or more REFRESH commands postponed, additional REFRESH commands may be postponed to the extent that the total number of postponed REFRESH commands (before and after self refresh) will never exceed eight. During self refresh mode, the number of postponed or pulled-in REFRESH commands does not change. And for per bank refresh, a maximum of 8 x 8 per bank REFRESH commands can be postponed or pulled in for scheduling efficiency. At any given time, a maximum of 2 x 8 x 8 per bank REFRESH commands can be issued within 2 × tREFI.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 114/300 Legacy REFRESH Command Timing Constraints MR4 OP[2:0] Refresh rate Max. No. of pulled-in or postponed REFab Max. Interval between two REFab Max. No. of REFab1 Per-bank REFRESH 000b Low temp. limit N/A N/A N/A N/A 001b 4 × tREFI 8 9 × 4 × tREFI I 16 1/8 of REFab 010b 2 ×tREFI 8 9 × 2 × tREFI 16 1/8 of REFab 011b 1 ×tREFI 8 9 ×tREFI 16 1/8 of REFab 100b 0.5 ×tREFI 8 9 × 0.5 × tREFI 16 1/8 of REFab 101b 0.25 ×tREFI 8 9 × 0.25 × tREFI 16 1/8 of REFab 110b 0.25 ×tREFI 8 9 × 0.25 × tREFI 16 1/8 of REFab 111b High temp. limit N/A N/A N/A N/A Note: 1. Maximum number of REFab within MAX(2 × tREFI × refresh rate multiplier, 16 × tRFC). Modified REFRESH Command Timing Constraints MR4 OP[2:0] Refresh Rate Max. No. of Pulled-in or Postponed REFab Max. Interval between Two REFab Max. No. of REFab1 Per-bank REFRESH 000B Low temp. limit N/A N/A N/A N/A 001B 4 ×tREFI 2 3 × 4 × tREFI 4 1/8 of REFab 010B 2 ×tREFI 4 5 × 2 ×tREFI 8 1/8 of REFab 011B 1 ×tREFI 8 9 ×tREFI 16 1/8 of REFab 100B 0.5 ×tREFI 8 9 × 0.5 × tREFI 16 1/8 of REFab 101B 0.25 ×tREFI 8 9 × 0.25 × tREFI 16 1/8 of REFab 110B 0.25 ×tREFI 8 9 × 0.25 × tREFI 16 1/8 of REFab 111B High temp. limit N/A N/A N/A N/A Note: 1. For any thermal transition phase where refresh mode is transitioned to either 2 × tREFI or 4 × tREFI, LPDDR4 devices will support the previous postponed refresh requirement provided the number of postponed refreshes is monotonically reduced to meet the new requirement. However, the pulled-in REFRESH commands in the previous thermal phase are not applied in the new thermal phase. Entering a new thermal phase, the controller must count the number of pulled -in REFRESH commands as zero, regardless of the number of remaining pulled-in REFRESH commands in the previous thermal phase. 2. LPDDR4 devices are refreshed properly if the memory controller issues REFRESH commands with same or shorter refresh period than reported by MR4 OP[2:0]. If a shorter refres h period is applied, the corresponding requirements from this table apply. For ex- ample, when MR4 OP[2:0] = 001b, the controller can be in any refresh rate from 4 × tREFI to 0.25 ×tREFI. When MR4 OP[2:0] = 010b, the only prohibited refresh rate is 4 ×tREFI.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 115/300 Postponing REFRESH Commands (Example) Pulling in REFRESH Commands (Example)

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 116/300 Burst READ Operation Followed by Per Bank Refresh Burst READ Operation Followed by Per Bank Refresh Note: 1. The per bank REFRESH command can be issued after tRTP + tRPpb from READ command. 2. BL = 16; Preamble = Toggle; Postamble = 0.5nCK; DQ/DQS: VSSQ termination. 3. DOUT n = data-out from column n. 4. In the case of BL = 32, delay time from read to per bank precharge is 8nCK + tRTP . 5. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 117/300 Burst READ With AUTO PRECHARGE Operation Followed by Per Bank Refresh Note: 1. BL = 16; Preamble = Toggle; Postamble = 0.5nCK; DQ/DQS: VSSQ termination. 2. DOUT n = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. tRC needs to be satisfied prior to issuing a subsequent per bank REFRESH command.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 118/300 Refresh Requirement Between the SRX command and SRE command, at least one extra REFRESH command is required. After the SELF REFRESH EXIT command, in addition to the normal REFRESH command at tREFI interval, the device requires a minimum of one extra REFRESH command prior to the SELF REFRESH ENTRY command. Refresh Requirement Parameters Parameter Symbol Density (per channel) Unit 2Gb 3Gb 4Gb 6Gb 8Gb 12Gb 16Gb Number of banks per channel – 8 - – Refresh window (tREFW): (1 × Refresh)3 tREFW 32 ms ms Required number of REFRESH commands in tREFW window R 8192 - – Average refresh interval (1 × Refresh)3 REFab tREFI 3.904 us REFpb tREFIpb 488 ns REFRESH cycle time (all banks) tRFCab 130 180 280 380 ns REFRESH cycle time (per bank) tRFCpb 60 90 140 190 ns Per bank refresh to per bank refresh time (different bank) tPBR2PBR 60 90 90 90 ns Note: 1. Refresh for each channel is independent of the other channel on the die, or other channels in a package. Power delivery in the user’s system should be verified to make sure the DC operating conditions are maintained when multiple channels are refreshed simultaneously. 2. Self refresh abort feature is available for higher density devices starting with 6Gb density per channel device and tXSR_abort(MIN) is defined as tRFCpb + 17.5ns. 3. Refer to MR4 OP[2:0] for detailed refresh rate and its multipliers.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 119/300 SELF REFRESH Operation Self Refresh Entry and Exit The SELF REFRESH command can be used to retain data in the device without external REFRESH commands. The device has a built -in timer to accommodate SELF REFRESH operation. Self refresh is entered by the SELF REFRESH ENTRY command defined by having CS HIGH, CA0 LOW, CA1 LOW, CA2 LOW, CA3 HIGH, CA4 HIGH, and CA5 valid (valid meaning that it is at a logic level HIGH or LOW) for the first rising edge, and CS LOW, CA0 valid, CA1 valid , CA2 valid, CA3 valid, CA4 valid, and CA5 valid at the second rising edge of clock. The SELF REFRESH command is only allowed when READ DATA burst is completed and the device is in the idle state. During self refresh mode, external clock input is needed an d all input pins of the device are activated. The device can accept the following commands: MRR -1, CAS-2, DES, SRX, MPC, MRW -1, and MRW -2, except PASR bank/segment mask setting and SR abort setting. The device can operate in self refresh mode within the standard and elevated temperature ranges. It also manages self refresh power consumption when the operating temperature changes: lower at low temperatures and higher at high temperatures. For proper SELF REFRESH operation, power supply pins (VDD1, VDD2, and VDDQ) must be at valid levels. VDDQ can be turned off during self refresh with power -down after tCKELCK is satisfied. (Refer to the Self Refresh Entry/Exit Timing with Power -Down Entry/Exit figure.) Prior to exiting self refresh with power-down, VDDQ must be within specified limits. The minimum time that the device must remain in self refresh mode is tSR(MIN). After self refresh exit is registered, only MRR -1, CAS-2, DES, MPC, MRW-1, and MRW-2 except PASR bank/segment mask setting and SR abort setting are allowed until tXSR is satisfied. The use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when self refres h exit is registered. Upon exit from self refresh, it is required that at least one REFRESH command (8 per-bank or 1 all-bank) is issued before entry into a subsequent self refresh. This REFRESH command is not included in the count of regular REFRESH commands required by the tREFI interval, and does not modify the postponed or pulled -in refresh counts; the REFRESH command does count toward the maximum refreshes permitted within 2 × tREFI. Self Refresh Entry/Exit Timing Note: 1. MRR-1, CAS-2, DES, SRX, MPC, MRW -1, and MRW-2 commands (except PASR bank/ segment mask setting and SR abort setting) are allowed during self refresh. 2. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 120/300 Power-Down Entry and Exit During Self Refresh Entering/exiting power-down mode is allowed during self refresh mode. The related timing parameters between self refresh entry/exit and power-down entry/exit are shown below. Self Refresh Entry/Exit Timing with Power-Down Entry/Exit Note: 1. MRR-1, CAS-2, DES, SRX, MPC, MRW -1, and MRW-2 commands (except PASR bank/ segment mask setting and SR abort setting) are allowed during self refresh. 2. Input clock frequency can be changed, or the input clock can be stopped, or floated after tCKELCK satisfied and during power-down, provided that upon exiting power -down, the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior to power -down exit and the clock frequency is between the minimum and maximum specified frequency for the speed grade in use. 3. Two clock command for example.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 121/300 Command Input Timing After Power-Down Exit Command input timings after power-down exit during self refresh mode are shown below. Command Input Timings after Power-Down Exit During Self Refresh Note: 1. MRR-1, CAS-2, DES, SRX, MPC, MRW -1, and MRW -2 commands (except PASR bank/ segment setting) are allowed during self refresh. 2. Input clock frequency can be changed or the input clock can be stopped or floated after tCKELCK satisfied and during power-down, provided that upon exiting power -down, the clock is stable and within specified limi ts for a minimum of tCKCKEH of stable clock prior to power -down exit and the clock frequency is between the minimum and maximum specified frequency for the speed grade in use. 3. Two clock command for example. Self Refresh Abort If MR4 OP[ 3] is enabled, the device aborts any ongoing refresh during self refresh exit and does not increment the internal refresh counter. The controller can issue a valid command after a delay of tXSR_abort instead of tXSR. The value of tXSR_abort(MIN) is defined as tRFCpb + 17.5ns. Upon exit from self refresh mode, the device requires a minimum of one extra refresh (eight per bank or one for the entire bank) before entering a subsequent self refresh mode. This requirement remains the same irrespective of the setting of the MR bit for self refresh abort. Self refresh abort feature is valid for 6Gb density per channel and larger densities only.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 122/300 MRR, MRW, MPC Commands During tXSR, tRFC MODE REGISTER READ (MRR), MULTI PURPOSE (MPC), and MODE REGISTER WRITE (MRW) comm and except PASR bank/segment mask setting and SR abort setting can be issued during tXSR period. MRR, MRW, and MPC Commands Issuing Timing During tXSR Note: 1. MPC and MRW commands are shown. Any combination of MRR, MRW, and MPC is allowed during tXSR period. 2. "Any command" includes MRR, MRW, and all MPC commands. MRR, MRW, and MPC can be issued during tRFC period.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 123/300 MRR, MRW, and MPC Commands Issuing Timing During tRFC Note: 1. MPC and MRW commands are shown. Any combination of MRR, MRW, and MPC is allowed during tRFCab or tRFCpb period. 2. REFRESH cycle time depends on REFRESH command. In the case of per bank REFRESH command issued, REFRESH cycle time will be tRFCpb. 3. "Any command" includes MRR, MRW, and all MPC commands.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 124/300 Power-Down Mode Power-Down Entry and Exit Power-down is asynchronously entered when CKE is driven LOW. CKE must not go LOW while the following operations are in progress:

Mode register read
Mode register write
Read
Write
VREF(CA) range and value setting via MRW
VREF(DQ) range and value setting via MRW
Command bus training mode entering/exiting via MRW
VRCG HIGH current mode entering/exiting via MRW CKE can go LOW while any other operations such as row activation, precharge, auto precharge, or refresh are in progress. The power-down IDD specification will not be applied until such operations are complete. Power -down entry and exit are shown below. Entering power-down deactivates the input and output buffers, excluding CKE and RESET_n. To ensure that there is enough time to account for internal delay on the CKE signal path, CS input is required stable LOW level and CA input level is "Don’t Care" after CKE is driven LOW, this timing period is defined as tCKELCS. Clock input is required after CKE is driven LOW, this timing period is defined as tCKELCK. CKE LOW will result in deactivation of all input receivers except RESET_n after tCKELCK has expired. In powerdown mode, CKE must be held LOW; all other input signals except RESET_n are "Don't Care." CKE LOW must be maintained until tCKE(MIN) is satisfied. VDDQ can be turned off during power -down after tCKELCK is satisfied. Prior to exiting power -down, VDDQ must be within its minimum/maximum operating range. No REFRESH operations are performed in power -down mode except self refresh power-down. The maximum duration in non -self-refresh power -down mode is only limited by the refresh requirements outlined in the REFRESH command section. The power-down state is asynchronously exited when CKE is driven HIGH. CKE HIGH must be maintained until tCKE(MIN) is satisfied. A valid, executable command can be applied with power -down exit latency tXP after CKE goes HIGH. Power -down exit latency is defined in the AC timing parameter table. Clock frequency change or clock stop is inhibited during tCMDCKE, tCKELCK, tCKCKEH, tXP , tMRWCKEL, and tZQCKE periods. If power-down occurs when all banks are idle, this mode is referred to as idle powerdown. if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. And If power-down occurs when self refresh is in progress, this mode is referred to as self refresh power -down in which the internal refresh is continuing in the same way as self refresh mode. When CA, CK, and/or CS ODT is enabled via MR11 OP[6:4] and also via MR22 or CAODT pad setting, the rank providing ODT will continue to terminate the command bus in all DRAM states including power -down when V DDQ is stable and within its minimum/maximum operating range. The LPDDR4 DRAM cannot be placed in power-down state during start DQS interval oscillator operation.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 125/300 Basic Power-Down Entry and Exit Timing Note: 1. Input clock frequency can be changed or the input clock can be stopped or floated during power -down, provided that upon exiting power-down, the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior to power-down exit and the clock frequency is between the minimum and maximum specified frequency for the speed grade in use.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 126/300 Read and Read with Auto Precharge to Power-Down Entry Note: 1. CKE must be held HIGH until the end of the burst operation. 2. Minimum delay time from READ command or READ with AUTO PRECHARGE command to falling edge of CKE signal is as follows: When read postamble = 0.5nCK (MR1 OP[7] = [0]), (RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 1tCK When read postamble = 1.5nCK (MR1 OP[7] = [1]), (RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 2tCK

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 127/300 Write and Mask Write to Power-Down Entry Note: 1. CKE must be held HIGH until the end of the burst operation. 2. Minimum delay time from WRITE command or MASK WRITE command to falling edge of CKE signal is as follows: (WL × tCK) + tDQSS(MAX) + tDQS2DQ(MAX) + ((BL/2) × tCK) + tWR 3. This timing is applied regardless of DQ ODT disable/enable setting: MR11 OP[2:0]. 4. This timing diagram only applies to the WRITE and MASK WRITE commands without auto precharge.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 128/300 Write With Auto Precharge and Mask Write With Auto Precharge to Power-Down Entry Note: 1. CKE must be held HIGH until the end of the burst operation. 2. Delay time from WRITE with AUTO PRECHARGE command or MASK WRITE with AUTO PRECHARGE command to falling edge of CKE signal is more than (WL × tCK) + tDQSS(MAX) + tDQS2DQ(MAX) + ((BL/2) × tCK) + (nWR × tCK) + (2 × tCK) 3. This timing is applied regardless of DQ ODT disable/enable setting: MR11 OP[2:0].

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 129/300 Refresh Entry to Power-Down Entry Note: 1. CKE must be held HIGH until tCMDCKE is satisfied. ACTIVATE Command to Power-Down Entry Note: 1. CKE must be held HIGH until tCMDCKE is satisfied.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 130/300 PRECHARGE Command to Power-Down Entry Note: 1. CKE must be held HIGH until tCMDCKE is satisfied.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 131/300 Mode Register Read to Power-Down Entry Note: 1. CKE must be held HIGH until the end of the burst operation. 2. Minimum delay time from MODE REGISTER READ command to falling edge of CKE signal is as follows: When read postamble = 0.5nCK ( MR1 OP[7] = [0]), (RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 1tCK When read postamble = 1.5nCK (MR1 OP[7] = [1]), (RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 2tCK

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 132/300 Mode Register Write to Power-Down Entry Note: 1. CKE must be held HIGH until tMRWCKEL is satisfied. 2. This timing is the general definition for power -down entry after MODE REGISTER WRITE command. When a MODE REGISTER WRITE command changes a parameter or starts an operation that requires special timing longer than tMRWCKEL, that timing must be satisfied before CKE is driven LOW. Changing the VREF(DQ) value is one example, in this case the appropriate tVREF-SHORT/MIDDLE/LONG must be satisfied.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 133/300 MULTI PURPOSE Command for ZQCAL Start to Power-Down Entry Note: 1. ZQ calibration continues if CKE goes LOW after tZQCKE is satisfied.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 134/300 Input Clock Stop and Frequency Change Clock Frequency Change – CKE LOW During CKE LOW, the device supports input clock frequency changes under the following conditions:  tCK(abs)min is met for each clock cycle  Refresh requirements apply during clock frequency change  During clock frequency change, only REFab or REFpb commands may be executing  Any ACTIVATE or PRECHARGE commands have completed prior to changing the frequency  Related timing conditions, tRCD and tRP , have been met prior to changing the frequency  The initial clock frequency must be maintained for a minimum of tCKELCK after CKE goes LOW  The clock satisfies tCH(abs) and tCL(abs) for a minimum of tCKCKEH prior to CKE going HIGH After the input clock frequency changes and CKE is held HIGH, additional MRW commands may be required to set the WR, RL, and so forth. These settings may require adjustment to meet minimum timing requirements at the target clock frequency. Clock Stop – CKE LOW During CKE LOW, the device supports clock stop under the following conditions:  CK_t and CK_c are don't care during clock stop  Refresh requirements apply during clock stop  During clock stop, only REFab or REFpb commands may be executing  Any ACTIVATE or PRECHARGE commands have completed prior to stopping the clock  Related timing conditions, tRCD and tRP , have been met prior to stopping the clock  The initial clock frequency must be maintained for a minimum of tCKELCK after CKE goes LOW  The clock satisfies tCH(abs) and tCL(abs) for a minimum of tCKCKEH prior to CKE going HIGH Clock Frequency Change – CKE HIGH During CKE HIGH, the device supports input clock frequency change under the following conditions:  tCK(abs)min is met for each clock cycle  Refresh requirements apply during clock frequency change  During clock frequency change, only REFab or REFpb commands may be executing  Any ACTIVATE, READ, WRITE, PRECHARGE, MODE REGISTER WRITE, or MODE REGISTER READ commands (and any associated data bursts) have completed prior to changing the frequency  Related timing conditions (tRCD, tWR, tRP , tMRW, and tMRR) have been met prior to changing the frequency  During clock frequency change, CS is held LOW  The device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 × tCK + tXP After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL, and so forth. These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 135/300 Clock Stop – CKE HIGH During CKE HIGH, the device supports clock stop under the following conditions:  CK_t is held LOW and CK_c is held HIGH during clock stop  During clock stop, CS is held LOW  Refresh requirements apply during clock stop  During clock stop, only REFab or REFpb commands may be executing  Any ACTIVATE, READ, WRITE, MPC (WRITE -FIFO, READ-FIFO, READ DQ CALIBRA - TION), PRECHARGE, MODE REGISTER WRITE, or MODE REGISTER READ commands have completed, including any associated data bursts and extra 4 clock cycles must be provided prior to stopping the clock  Related timing conditions (tRCD, tWR, tRP , tMRW, tMRR, tZQLAT, and so forth) have been met prior to stopping the clock  READ with AUTO PRECHARGE and WRITE with AUTO PRECHARGE commands need extra 4 clock cycles in addition to the related timing constraints, nWR and nRTP , to complete the operations  REFab, REFpb, SRE, SRX, and MPC[ZQCAL START] commands are required to have extra 4 clock cycles prior to stopping the clock  The device is ready for normal operation after the clock is restarted and satisfies tCH(abs) and tCL(abs) for a minimum of 2 × tCK + tXP

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 136/300 MODE REGISTER READ Operation The MODE REGISTER READ (MRR) command is used to read configuration and status data from t he device registers. The MRR command is initiated with CS and CA[5:0] in the proper state as defined by the Command Truth Table. The mode register address operands (MA[5:0]) enable the user to select one of 64 registers. The mode register contents are avai lable on the first four UI data bits of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ following the MRR command. Subsequent data bits contain valid but undefined content. DQS is toggled for the duration of the MODE REGISTER READ burst. The MRR has a command burs t length of 16. MRR operation must not be interrupted. MRR UI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQ0 OP0 V DQ1 OP1 V DQ2 OP2 V DQ3 OP3 V DQ4 OP4 V DQ5 OP5 V DQ6 OP6 V DQ7 OP7 V DQ8– DQ15 V DMI0– DMI1 V Note: 1. MRR data are extended to the first 4 UIs, allowing the LPDRAM controller to sample data easily. 2. DBI during MRR depends on mode register setting MR3 OP[6]. 3. The read preamble and postamble of MRR are the same as for a normal read.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 137/300 MODE REGISTER READ Operation Note: 1. Only BL = 16 is supported. 2. Only DESELECT is allowed during tMRR period. 3. There are some exceptions about issuing commands after tMRR. Refer to MRR/MRW Timing Constraints Table for detail. 4. DBI is disable mode. 5. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times. 6. DQ/DQS: VSSQ termination

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 138/300 MRR After a READ and WRITE Command After a prior READ command, the MRR command must not be issued earlier than BL/2 clock cycles, in a similar way WL + BL/2 + 1 + RU( tWTR/tCK) clock cycles after a PRIOR WRITE, WRITE with AP , MASK WRITE, MASK WRITE with AP , and MPC[WRITE-FIFO] command in order to avoid the collision of READ and WRITE burst data on device internal data bus. READ-to-MRR Timing Note: 1. The minimum number of clock cycles from the burst READ command to the MRR command is BL/2. 2. Read BL = 32, MRR BL = 16, RL = 14, Preamble = Toggle, Postamble = 0.5nCK, DBI = Disable, DQ/DQS: V SSQ termination. 3. DOUT n = data-out to column n. 4. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 139/300 WRITE-to-MRR Timing Note: 1. Write BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. Only DES is allowed during tMRR period. 3. DOUT n = data-out to column n. 4. The minimum number of clock cycles from the BURST WRITE command to MRR command is WL + BL/2 + 1 + RU(tWTR/tCK). 5. tWTR starts at the rising edge of CK after the last latching edge of DQS. 6. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 140/300 MRR After Power-Down Exit Following the power -down state, an additional time, tMRRI, is required prior to issuing the MODE REGISTER READ (MRR) command. This additional time (equivalent to tRCD) is required in or der to maximize power -down current savings by allowing more power-up time for the MRR data path after exit from power-down mode. MRR Following Power-Down Note: 1. Only DES is allowed during tMRR period. 2. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 141/300 MODE REGISTER WRITE The MODE REGISTER WRITE (MRW) writes configuration data to the mode registers. The MRW command is initiated with CKE, CS, and CA[5:0] to valid levels at the rising edge of t he clock. The mode register address and the data written to it is contained in CA[5:0] according to the Command Truth Table. The MRW command period is defined by tMRW. Mode register WRITEs to read-only registers have no impact on the functionality of the device. MODE REGISTER WRITE Timing

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 142/300 Mode Register Write States MRW can be issued from either a bank-idle or a bank-active state. Certain restrictions may apply for MRW from an active state. Truth Table for MRR and MRW Current State Command Intermediate State Next State All banks idle MRR Reading mode register, all banks idle All banks idle MRW Writing mode register, all banks idle All banks idle Bank(s) active MRR Reading mode register Bank(s) active MRW Writing mode register Bank(s) active MRR/MRW Timing Constraints: DQ ODT is Disable From Command To Command Minimum Delay Between "From Command" and "To Command" Unit Note MRR MRR tMRR – RD/RDA tMRR – WR/WRA/MWR/MWRA RL + RU(tDQSCK(MAX)/tCK) + BL/2 -WL + tWPRE + RD(tRPST) nCK MRW RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 3 nCK RD/RDA MRR BL/2 nCK WR/WRA/MWR/ MWRA WL + 1 + BL/2 + RU(tWTR/tCK) nCK MRW tMRD – POWER-DOWN EXIT tXP + tMRRI – MRW RD/RDA tMRD – WR/WRA/MWR/MWRA tMRD – MRW tMRW – RD/ RD-FIFO/ READ DQ CAL MRW RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + MAX(RU(7.5ns/tCK), 8nCK) nCK RD with AUTO PRECHARGE RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + MAX(RU(7.5ns/tCK), 8nCK) + nRTP - 8 nCK WR/ MWR/ WR-FIFO WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) nCK WR/MWR with AUTO PRECHARGE WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) + nWR nCK

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 143/300 MRR/MRW Timing Constraints: DQ ODT is Enable From Command To Command Minimum Delay Between "From Command" and "To Command" Unit Note MRR MRR tMRR – RD/RDA tMRR – WR/WRA/MWR/MWRA RL + RU( tDQSCK(MAX)/tCK) + BL/2 - ODTLon - RD(tODTon(MIN)/tCK) + RD(tRPST) + 1 nCK MRW RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 3 nCK RD/RDA MRR BL/2 nCK WR/WRA/MWR/ MWRA WL + 1 + BL/2 + RU(tWTR/tCK) nCK MRW tMRD – POWER-DOWN EXIT tXP + tMRRI – MRW RD/RDA tMRD – WR/WRA/MWR/MWRA tMRD – MRW tMRW – RD/ RD-FIFO/ READ DQ CAL MRW RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + MAX(RU(7.5ns/tCK), 8nCK) nCK RD with AUTO PRECHARGE RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + MAX(RU(7.5ns/tCK), 8nCK) + nRTP - 8 nCK WR/ MWR/ WR-FIFO WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) nCK WR/MWR with AUTO PRECHARGE WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) + nWR nCK

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 144/300 VREF Current Generator (VRCG) LPDDR4 SDRAM VREF current generators (VRCG) incorporate a high current mode to reduce the settling time of the internal VREF(DQ) and VREF(CA) levels during training and when changing frequency set points during operation. The high current mode is enabled by setting MR13[ OP3] = 1. Only DESELECT commands may be issued until tVRCG_ENABLE is satisfied. tVRCG_ENABLE timing is shown below. VRCG Enable Timing VRCG high current mode is disabled by setting MR13[OP3] = 0. Only DESELECT commands may be issued until tVRCG_DISABLE is satisfied. tVRCG_DISABLE timing is shown below. VRCG Disable Timing Note that LPDDR4 SDRAM devices support V FER(CA) and V REF(DQ) range and value changes without enabling VRCG high current mode. VRCG Enable/Disable Timing Parameter Symbol Min Max Unit VREF high current mode enable time tVRCG_ENABLE – 200 ns VREF high current mode disable time tVRCG_DISABLE – 100 ns

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 145/300 VREF Training VREF(CA) Training The device's internal V REF(CA) specification parameters are operating voltage range, step size, V REF step time, V REF full-range step time, and VREF valid level. The voltage operating range specifies the minimum required V REF setting range for LPDDR4 devices. The minimum range is defined by VREF,max and VREF,min. VREF Operating Range (VREF,max, VREF,min) The VREF step size is defined as the step size between adjacent steps. However, for a given design, the device has one value for VREF step size that falls within the given range. The VREF set tolerance is the variation in the V REF voltage from t he ideal setting. This accounts for accumulated error over multiple steps. There are two ranges for VREF set tolerance uncertainty. The range of VREF set tolerance uncertainty is a function of the number of steps n. The VREF set tolerance is measured with respect to the ideal line that is based on the two endpoints, where the endpoints are at the minimum and maximum VREF values for a specified range.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 146/300 VREF Set-Point Tolerance and Step Size The VREF increment/decrement step times are defined by tVREF_TIME-SHORT, tVREF_TIME-MIDDLE, and tVREF_TIME-LONG. The parameters are defined from TS to TE as shown below, where TE is referenced to when the VREF voltage is at the final DC level within the VREF valid tolerance (VREF,val_tol). The VREF valid level is d efined by V REF,val_tol to qualify the step time TE (see the following figures). This parameter is used to ensure an adequate RC time constant behavior of the voltage level change after any V REF increment/decrement adjustment. This parameter is only applicable for LPDDR4 component level validation/characterization. tVREF_TIME-SHORT is for a single step size increment/decrement change in the VREF voltage. tVREF_TIME-MIDDLE is at least two stepsizes increment/decrement change within the same VREF(CA) range in VREF voltage. tVREF_TIME-LONG is the time including up to VREF,min to VREF,max or VREF,max to VREF,min change across the VREF(CA) range in VREF voltage. TS is referenced to MRW command clock. TE is referenced to VREF_val_tol.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 147/300 tVref for Short, Middle, and Long Timing Diagram The MRW command to the mode register bits are as follows; MR12 OP[5:0] : VREF(CA) Setting MR12 OP[6] : VREF(CA) Range The minimum time required between two V REF MRW commands is tVREF_TIME-SHORT for a single step and tVREF_TIME-MIDDLE for a full voltage range step. VREF(CA) Single-Step Increment

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 148/300 VREF(CA) Single-Step Decrement VREF(CA) Full Step from VREF,min to VREF,max VREF(CA) Full Step from VREF,max to VREF,min The following table contains the CA internal VREF specification that will be characterized at the component level for compliance.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 149/300 Internal VREF(CA) Specifications Symbol Parameter Min Typ Max Unit Note VREF(CA),max_r0 VREF(CA) range-0 MAX operating point – – 44.9% VDDQ 1, 11 VREF(CA),min_r0 VREF(CA) range-0 MIN operating point 15.0% – – VDDQ 1, 11 VREF(CA),max_r1 VREF(CA) range-1 MAX operating point – – 62.9% VDDQ 1, 11 VREF(CA),min_r1 VREF(CA) range-1 MIN operating point 32.9% – – VDDQ 1, 11 VREF(CA),step VREF(CA) step size 0.50% 0.60% 0.70% VDDQ 2 VREF(CA),set_tol VREF(CA) set tolerance –11 0 11 mV 3, 4, 6 –1.1 0 1.1 mV 3, 5, 7 tVREF_TIME-SHORT VREF(CA) step time – – 100 ns 8 tVREF_TIME-MIDDLE – – 200 ns 12 tVREF_TIME-LONG – – 250 ns 9 tVREF_time_weak – – 1 ms 13, 14 VREF(CA)_val_tol VREF(CA) valid tolerance –0.10% 0.00% 0.10% VDDQ 10 Note: 1. VREF(CA) DC voltage referenced to VDDQ(DC). 2. VREF(CA) step size increment/decrement range. VREF(CA) at DC level. 3. VREF(CA),new = VREF(CA),old + n × VREF(CA),step; n = number of steps; if increment, use "+"; if decrement, use "–". 4. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 11mV. The maximum value of VREF(CA) setting tolerance = VREF(CA),new + 11mV. For n > 4. 5. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 1.1mV. The maximum value of VREF(CA) setting tolerance = VREF(CA),new + 1.1mV. For n ≤ 4. 6. Measured by recording the minimum and maximum values of the V REF(CA) output over the range, drawing a straight line between those points and comparing all other VREF(CA) output settings to that line. 7. Measured by recording the minimum and maximum values of the V REF(CA) output across four consecutive steps (n = 4), drawing a straight line between those points and comparing all other VREF(CA) output settings to that line. 8. Time from MRW command to increment or decrement one step size for VREF(CA). 9. Time from MRW command to increment or decrement V REF,min to VREF,max or VREF,max to VREF,min change across the VREF(CA) range in VREF voltage. 10. Only applicable for DRAM component level test/characterization purposes. Not applicable for normal mode of operation. VREF valid is to qualify the step times which will be characterized at the component level. 11. DRAM range-0 or range-1 set by MR12 OP[6]. 12. Time from MRW command to increment or decrement more than one step size up to a full range of VREF voltage within the same VREF(CA) range. 13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0b. 14. tVREF_time_weak covers all VREF(CA) range and value change conditions are applied to VREF_TIME-SHORT/MIDDLE/LONG.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 150/300 VREF(DQ) Training The device's internal V REF(DQ) specification parameters are operating voltage range, step size, V REF step tolerance, V REF step time and VREF valid level. The voltage operating range specifies the minimum required V REF setting range for LPDDR4 devices. The minimum range is defined by VREF,max and VREF,min. VREF Operating Range (VREF,max, VREF,min) The VREF step size is defined as the step size between adjacent steps. However, for a given design, the device has one value for VREF step size that falls within the given range. The VREF set tolerance is the variation in the V REF voltage from the ideal setting. T his accounts for accumulated error over multiple steps. There are two ranges for VREF set tolerance uncertainty. The range of VREF set tolerance uncertainty is a function of the number of steps n. The VREF set tolerance is measured with respect to the ideal line that is based on the two endpoints, where the endpoints are at the minimum and maximum VREF values for a specified range.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 151/300 VREF Set Tolerance and Step Size The VREF increment/decrement step times are defined by tVREF_TIME-SHORT, tVREF_TIME-MIDDLE and tVREF_TIME-LONG. The tVREF_TIME-SHORT, tVREF_TIMEMIDDLE and tVREF_TIME-LONG times are defined from TS to TE in the following figure where TE is referenced to when the VREF voltage is at the final DC level within the VREF valid tolerance (VREF,VAL_TOL). The VREF valid level is defined by V REF,VAL_TOL to qualify the step time TE (see the figure below). This parameter is used to ensure an adequate RC time constant behavior of the voltage level change after any V REF increment/decrement adjustment. This parameter is only applicable for DRAM component level validation/characterization. tVREF_TIME-SHORT is for a single step size increment/decrement change in the VREF voltage. tVREF_TIME-MIDDLE is at least two step sizes of increment/decrement change in the VREF(DQ) range in the VREFvoltage. tVREF_TIME-LONG is the time including and up to the full range of VREF (MIN to MAX or MAX to MIN) across the VREF(DQ) range in VREF voltage.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 152/300 VREF(DQ) Transition Time for Short, Middle, or Long Changes Note: 1. TS is referenced to MRW command clock. 2. TE is referenced to VREF,VAL_TOL. The MRW command to the mode register bits are defined as: MR14 OP[5:0]: VREF(DQ) setting MR14 OP[6]: VREF(DQ) range The minimum time required between two V REF MRW commands is tVREF_TIME-SHORT for a single step and VREF_TIME-MIDDLE for a full voltage range step. VREF(DQ) Single-Step Size Increment

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 153/300 VREF(DQ) Single-Step Size Decrement VREF(DQ) Full Step from VREF,min to VREF,max VREF(DQ) Full Step from VREF,max to VREF,min The following table contains the DQ internal VREF specification that will be characterized at the component level for compliance.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 154/300 Internal VREF(DQ) Specifications Symbol Parameter Min Typ Max Unit Note VREF(DQ),max_r0 VREF MAX operating point Range-0 – – 44.9% VDDQ 1, 11 VREF(DQ),min_r0 VREF MIN operating point Range-0 15.0% – – VDDQ 1, 11 VREF(DQ),max_r1 VREF MAX operating point Range-1 – – 62.9% VDDQ 1, 11 VREF(DQ),min_r1 VREF MIN operating point Range-1 32.9% – – VDDQ 1, 11 VREF(DQ),step VREF(DQ) step size 0.50% 0.60% 0.70% VDDQ 2 VREF(DQ),set_tol VREF(DQ) set tolerance –11 0 11 mV 3, 4, 6 –1.1 0 1.1 mV 3, 5, 7 tVREF_TIME-SHORT VREF(DQ) step time – – 100 ns 8 tVREF_TIME-MIDDLE – – 200 ns 12 tVREF_TIME-LONG – – 250 ns 9 tVREF_time_weak – – 1 ms 13, 14 VREF(DQ),val_tol VREF(DQ) valid tolerance –0.10% 0.00% 0.10% VDDQ 10 Note: 1. VREF(DQ) DC voltage referenced to VDDQ(DC). 2. VREF(DQ) step size increment/decrement range. VREF(DQ) at DC level. 3. VREF(DQ),new = VREF(DQ),old + n × VREF(DQ),step; n = number of steps; if increment, use "+"; if decrement, use "–". 4. The minimum value of VREF(DQ) setting tolerance = VREF(DQ),new - 11mV. The maximum value of VREF(DQ) setting tolerance = VREF(DQ),new + 11mV. For n > 4. 5. The minimum value of VREF(DQ) setting tolerance = VREF(DQ),new - 1.1mV. The maximum value of VREF(DQ) setting tolerance = VREF(DQ),new + 1.1mV. For n ≤ 4. 6. Measured by recording the minimum and maximum values of the V REF(DQ) output over the range, drawing a straight line between those points and comparing all other VREF(DQ) output settings to that line. 7. Measured by recording the minimum and maximum values of the V REF(DQ) output across four consecutive steps (n = 4), drawing a straight line between those points and comparing all other VREF(DQ) output settings to that line. 8. Time from MRW command to increment or decrement one step size for VREF(DQ). 9. Time from MRW command to increment or decrement VREF,min to VREF,max or VREF,max to VREF,min change across the VREF(DQ) Range in VREF(DQ) Voltage. 10. Only applicable for DRAM component level test/characterization purposes. Not applicable for normal mode of operation. VREF valid is to qualify the step times which will be characterized at the component level. 11. DRAM range-0 or range-1 set by MR14 OP[6]. 12. Time from MRW command to increment or decrement more than one step size up to a full range of VREF voltage within the same VREF(DQ) range. 13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0. 14. tVREF_time_weak covers all VREF(DQ) Range and Value change conditions are applied to tVREF_TIME-SHOR/MIDDLE/LONG.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 155/300 Command Bus Training Command Bus Training Mode The command bus must be trained before enabling termination for high -frequency operation. The device provides an internal VREF(CA) that defaults to a level suitable for unterminated, low -frequency operation, but the V REF(CA) must be trained to achieve suitable receiver voltage margin for terminated, high-frequency operation. The training mode described here centers the internal V REF(CA) in the CA data eye and at the same time allows for timing adjustments of the CS and CA signals to meet setup/ hold requirements. Because it can be difficult to capture commands prior to training the CA inputs, the training mode described here uses a minimum of external commands to enter, train, and exit the CA bus training mode. The die has a bond-pad (ODT_CA) but ODT_CA pin is ignored by LPDDR4X devices. CA ODT is fully controlled through MR11 and MR22. See On-Die Termination for more in- formation. The device uses frequency set points to enable multiple operating settings for the die. The device defaults to FSP -OP[0] at power-up, which has the default settings to operate in un -terminated, low -frequency environments. Prior to training, the termination should be enabled for one die in each channel by setting MR13 OP[6] = 1b (FSP-WR[1]) and setting all other mode register bits f or FSP -OP[1] to the desired settings for high - frequency operation. Upon training entry, the device will automatically switch to FSP- OP[1] and use the high-frequency settings during training (See the Command Bus Training Entry Timing figure for more infor mation on FSP -OP register sets). Upon training exit, the device will automatically switch back to FSP-OP[0], returning to a "known- good" state for unterminated, low-frequency operation. To enter command bus training mode, issue a MRW -1 command followed by a MRW-2 command to set MR13 OP[0] = 1b (command bus training mode enabled). After time tMRD, CKE may be set LOW, causing the device to switch to FSP-OP[1], and completing the entry into command bus training mode. A status DQS_t, DQS_c, DQ, and DMI are as noted below; the DQ ODT state will be followed by FREQUENCY SET POINT function except in the case of output pins.  DQS_t[0], DQS_c[0] become input pins for capturing DQ[6:0] levels by toggling.  DQ[5:0] become input pins for setting VREF(CA) level.  DQ[6] becomes an input pin for setting VREF(CA) range.  DQ[7] and DMI[0] become input pins, and their input level is valid or floating.  DQ[13:8] become output pins to feedback, capturing value via the command bus using the CS signal.  DQS_t[1], DQS_c[1], DMI[1], and DQ[15:14] become output pins or are disabled, meaning the device may be driven to a valid level or may be left floating. At time tCAENT later, the device may change its VREF(CA) range and value using input signals DQS_t[0], DQS_c[0], and DQ[6:0] from existing value that is set via MR12 OP[6:0]. The mapping between MR12 OP code and DQs is shown below. At least one VREF(CA) setting is required before proceeding to the next training step.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 156/300 Mapping MR12 Op Code and DQ Numbers Mapping MR12 OP code OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQ number DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 The new VREF(CA) value must "settle" for time tVREFCA_Long before attempting to latch CA information. Note: If DQ ODT is enabled in MR11 -OP[2:0], then the SDRAM will terminate the DQ lanes during command bus training when entering VREF(CA) range and values on DQ[6:0]. To verify that the receiver has the correct VREF(CA) setting, and to further train the CA eye relative to clock (CK), values latched at the receiver on the CA bus are asynchronously output to the DQ bus. To exit command bus training mode, drive CKE HIGH, and after time tVREFCA_Long, issue the MRW-1 command followed by the MRW-2 command to set MR13 OP[0] = 0b. After time tMRW, the device is ready for normal operation. After training exit, the device will automatically switch back to the FSP-OP registers that were in use prior to training. Command bus training (CBT) may be executed from the idle or self refresh state. When executing CBT within the self refresh state, the device must not be in a power-down state (for example, CKE must be HIGH prior to training entry). CBT entry and exit is the same, regardless of the state from which CBT is initiated. Training Sequence for Single-Rank Systems The sequence example shown here assumes an initial low-frequency, non-terminating operating point training a high-frequency, terminating operating point. The bold text shows high -frequency instructions. Any operating point may be trained from any known good operating point. 1. Set MR13 OP[6] = 1b to enable writing to frequency set point 1 (FSP-WR[1]) (or FSP-OP[0]). 2. Write FSP-WR[1] (or FSP-WR[0]) registers for all channels to set up high-frequency operating parameters. 3. Issue MRW-1 and MRW-2 commands to enter command bus training mode. 4. Drive CKE LOW, and change CK frequency to the high-frequency operating point. 5. Perform command bus training (VREF(CA), CS, and CA). 6. Exit training by driving CKE HIGH, change CK frequency to the low -frequency operating point, and issue MRW -1 and MRW-2 commands. When CKE is d riven HIGH, the device will automatically switch back to the FSP -OP registers that were in use prior to training (trained values are not retained). 7. Write the trained values to FSP -WR[1] (or FSP -WR[0]) by issuing MRW -1 and MRW -2 commands to the SDRAM and setting all applicable mode register parameters. 8. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[1] (or FSP-OP[0]), to turn on termination, and change CK frequency to the high -frequency operating point. At this point the command bus i s trained and you may proceed to other training or normal operation.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 157/300 Training Sequence for Multiple-Rank Systems The sequence example shown here is assuming an initial low -frequency operating point, training a high -frequency operating point. The bold text shows high-frequency instructions. Any operating point may be trained from any known good operating point. 1. Set MR13 OP[6] = 1b to enable writing to frequency set point 1 (FSP-WR[1]) (or FSP-WR[0]). 2. Write FSP-WR[1] (or FSP-WR[0]) registers for all channels and ranks to set up high-frequency operating parameters. 3. Read MR0 OP[7] on all channels and ranks to determine which die are terminating, signified by MR0 OP[7] = 1b. 4. Issue MRW-1 and MRW-2 commands to enter command bus training mode on the terminating rank. 5. Drive CKE LOW on the terminating rank (or all ranks), and change CK frequency to the high-frequency operating point. 6. Perform command bus training on the terminating rank (VREF(CA), CS, and CA). 7. Exit training by driving CKE HIGH, change CK frequency to t he low-frequency operating point, and issue MRW -1 and MRW-2 commands to write the trained values to FSP-WR[1] (or FSP-WR[0]). When CKE is driven HIGH, the SDRAM will automatically switch back to the FSP-OP registers that were in use prior to training (trained values are not retained by the device). 8. Issue MRW-1 and MRW-2 commands to enter training mode on the non-terminating rank (but keep CKE HIGH). 9. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[1] (or FSP-OP[0]), to turn on termination, and change CK frequency to the high-frequency operating point. 10. Drive CKE LOW on the non -terminating (or all) ranks. The non -terminating rank(s) will now be using FSP -OP[1] (or FSP-OP[0]). 11. Perform command bus training on the non-terminating rank (VREF(CA), CS, and CA). 12. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP- OP[0] (or FSP-OP[1]) to turn off termination. 13. Exit training by driving CKE HIGH on the non-terminating rank, change CK frequency to the low-frequency operating point, and issue MRW-1 and MRW-2 commands. When CKE is driven HIGH, the device will automatically switch back to the FSP-OP registers that were in use prior to training (that is, trained values are not retained by the device). 14. Write the trained values to F SP-WR[1] (or FSP -WR[0]) by issuing MRW -1 and MRW -2 commands and setting all applicable mode register parameters. 15. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[1] (or FSP-OP[0]), to turn on termination, and change CK frequency to the high-frequency operating point. At this point the command bus is trained for both ranks and the user may proceed to other training or normal operation.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 158/300 Relation Between CA Input Pin and DQ Output Pin Mapping CA Input Pin and DQ Output Pin Mapping CA number CA5 CA4 CA3 CA2 CA1 CA0 DQ number DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 Command Bus Training Mode Entry – CA Training Pattern I/O with VREF(CA) Value Update Note: 1. After tCKELCK, the clock can be stopped or the frequency changed any time. 2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS. 3. Continue to drive CK, and hold CA and CS LOW, until tCKELCK after CKE is LOW (which disables command decoding). 4. The device may or may not capture the first rising edge of DQS_t/DQS_c due to an unstable first rising edge. Therefore, at least two consecutive pulses of DQS signal input is required every for DQS input signal while capturing DQ[6:0] signals. The captured value of the DQ[6:0] signal level by each DQS edge may be overwritten at a ny time and the device will temporarily update the VREF(CA) setting of MR12 after time tVREFCA_Long. 5. tVREFCA_Long may be reduced to tVREFCA_Short if the following conditions are met: 1) The new VREF setting is a single step above or below the old V REF setting; 2) The DQS pulses a single time, or the new VREF setting value on DQ[6:0] is static and meets tDS,train/ tDH,train for every DQS pulse applied. 6. When CKE is driven LOW, the device will switch its FSP-OP registers to use the alternate (non-active) set. For example, if the device is currently using FSP -OP[0], then it will switch to FSP -OP[1] when CKE is driven LOW. All operating parameters should be written to the alternate mode registers before entering command bus training to ensure that ODT settings, RL/WL/nWR setting, and so forth, are set to the correct values. 7. When CKE is driven LOW in command bus training mode, the device will change operation to the alternate FSP, that is, the inverse of the FSP programmed in the FSP-OP mode register.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 159/300 Consecutive VREF(CA) Value Update Note: 1. After tCKELCK, the clock can be stopped or the frequency changed any time. 2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS. 3. Continue to drive CK, and hold CA and CS LOW, until tCKELCK after CKE is LOW (which disables command decoding). 4. The device may or may not capture the first rising edge of DQS_t/DQS_c due to an unstable first rising edge. Therefore, at least two consecutive pulses of DQS signal input is required every for DQS input signal while capturing DQ[6:0] signals. The captured value of the DQ[6:0] signal level by each DQS edge may be overwritten at any time and the device will temporarily update the VREF(CA) setting of MR12 after time tVREFCA_Long. 5. tVREFCA_Long may be reduced to tVREFCA_Short if the following conditions are met: 1) The new VREF setting is a single step above or below the old V REF setting; 2) The DQS pulses a single time, or the new VREF setting value on DQ[6:0] is static and meets tDS,train/ tDH,train for every DQS pulse applied. 6. When CKE is driven LOW, the device will switch its FSP-OP registers to use the alternate (non-active) set. For example, if the device is currently using FSP -OP[0], then it will switch to FSP -OP[1] when CKE is driven LOW. All operating parameters should be written to the alternate mode registers before entering command bus training to ensure that ODT settings, RL/WL/nWR setting, and so forth, are set to the correct values. 7. When CKE is driven LOW in command bus training mode, the device will change operation to the alternate FSP, that is, the inverse of the FSP programmed in the FSP-OP mode register.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 160/300 Command Bus Training Mode Exit with Valid Command Note: 1. The clock can be stopped or the frequency changed any time before tCKCKEH. CK must meet tCKCKEH before CKE is driven HIGH. When CKE is driven HIGH, the clock frequency must be returned to the original frequency (that is, the frequency corresponding to the FSP at command bus training mode entry. 2. CS and CA[5:0] must be deselected (LOW) tCKCKEH before CKE is driven HIGH. 3. When CKE is driven HIGH, ODT_CA will revert to the state/value defined by FSP-OP prior to command bus training mode entry, that is, the original frequency set point (FSP-OP , MR13-OP[7]). For example, if the device was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH. 4. Training values are not retained by the device and must be written to the FSP -OP register set before returning to operation at the trained frequency. For example, VREF(CA) will return to the value programmed in the original set point. 5. When CKE is driven HIGH, the device will revert to the FSP in operation at command bus training mode entry.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 161/300 Command Bus Training Mode Exit with Power-Down Entry Note: 1. The clock can be stopped or the frequency changed any time before tCKCKEH. CK must meet tCKCKEH before CKE is driven HIGH. When CKE is driven HIGH, the clock frequency must be returned to the original frequency (that is, the frequency corresponding to the FSP at command bus training mode entry. 2. CS and CA[5:0] must be deselected (LOW) tCKCKEH before CKE is driven HIGH. 3. When CKE is driven HIGH, ODT_CA will revert to the state/value defined by FSP-OP prior to command bus training mode entry, that is, the original frequency set point (FSP-OP , MR13-OP[7]). For example, if the device was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH. 4. Training values are not retained by the device and must be written to the FSP -OP regis ter set before returning to operation at the trained frequency. For example, VREF(CA) will return to the value programmed in the original set point. 5. When CKE is driven HIGH, the device will revert to the FSP in operation at command bus training mode entry.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 162/300 Write Leveling Mode Register Write-WR Leveling Mode To improve signal-integrity performance, the device provides a write leveling feature to compensate for CK-to-DQS timing skew, affecting timing parameters such as tDQSS, tDSS, and tDSH. The memory controller uses the write leveling feature to receive feedback from the device, enabling it to adjust the clock -to-data strobe signal relationship for each DQS_t/DQS_c signal pair. The device samples the clock state with the rising edge of DQS signals and asynchronously feeds back to the memory controller. The memory controller references this feedback to adjust the clock -to-data strobe signal relationship for each DQS_t/DQS_c signal pair. All data bits (DQ[7:0] for DQS[0] and DQ[15:8] for DQS[1]) carry the training feedback to the controller. Both DQS signals in each channel must be leveled independently. Write leveling entry/exit is independent between channels for dual -channel devices. The device enters write leveling mode when mode register MR2-OP[7] is set HIGH. When entering write leveling mode, the state of the DQ pins is undef ned. During write leveling mode, only DESELECT commands, or a MRW command to exit the WRITE LEVELING operation, are allowed. Depending on the absolute values of tQSL and tQSH in the application, the value of tDQSS may have to be better than the limits provided in the AC Timing Parameters section in order to satisfy the tDSS and tDSH specifications. Upon completion of the WRITE LEVELING operation, the device exits write leveling mode when MR2-OP[7] is reset LOW. Write leveling should be performed before write training (DQS2DQ training). Write Leveling Procedure 1. Enter write leveling mode by setting MR2-OP[7]=1. 2. Once in write leveling mode, DQS_t must be driven LOW and DQS_c HIGH after a delay of tWLDQSEN. 3. Wait for a time tWLDQSEN before providing the first DQS signal input. The delay time tWLMRD(MAX) is controller-dependent. 4. The device may or may not capture the first rising edge of DQS_t due to an unstable first rising edge; therefore, at least two consecutive pulses of DQS signal input is required for every DQS input signal during write training mode. The captured clock level for each DQS edge is overwritten, and the device provides asynchronous feedback on all DQ bits after time tWLO. 5. The feedback provided by the device is referenced by the controller to increment or decrement the DQS_t and/or DQS_c delay settings. 6. Repeat steps 4 and 5 until the proper DQS_t/DQS_c delay is established. 7. Exit write leveling mode by setting MR2-OP[7] = 0.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 163/300 Write Leveling Timing – tDQSL(MAX) Note: 1. Clock can be stopped except during DQS toggle period (CK_t = LOW, CK_c = HIGH). However, a stable clock prior to sampling is required to ensure timing accuracy. Write Leveling Timing – tDQSL(MIN) Note: 1. Clock can be stopped except during DQS toggle period (CK_t = LOW, CK_c = HIGH). However, a stable clock prior to sampling is required to ensure timing accuracy.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 164/300 Input Clock Frequency Stop and Change The input clock frequency can be stopped or changed from one stable clock rate to another stable clock rate during write leveling mode. The frequency stop or change timing is shown below. Clock Stop and Timing During Write Leveling Note: 1. CK_t is held LOW and CK_c is held HIGH during clock stop. 2. CS will be held LOW during clock stop. Write Leveling Timing Parameters Parameter Symbol Min/Max Value Units DQS_t/DQS_c delay after write leveling mode is programmed tWLDQSEN MIN 20 tCK MAX – Write preamble for write leveling tWLWPRE MIN 20 tCK MAX – First DQS_t/DQS_c edge after write leveling mode is programmed tWLMRD MIN 40 tCK MAX – Write leveling output delay tWLO MIN 0 ns MAX 20 MODE REGISTER SET command delay tMRD Refer to Mode Register Timing Parameter Table Valid clock requirement before DQS toggle tCKPRDQS MIN MAX(7.5ns, 4nCK) MAX – Valid clock requirement after DQS toggle tCKPSTDQS MIN MAX(7.5ns, 4nCK) MAX –

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 165/300 Write Leveling Setup and Hold Timing Parameter Symbol Min/Max Data Rate Unit 1600 2400 3200 3733 Write leveling hold time tWLH MIN 150 100 75 62.5 ps Write leveling setup time tWLS MIN 150 100 75 62.5 ps Write leveling input valid window tWLIVW MIN 240 160 120 105 ps Note: 1. In addition to the traditional setup and hold time specifications, there is value in a invalid window -based specification for write leveling training. As the training is based on each device, worst case process skews for setup and hold do not make sense to close timing between CK and DQS. 2. tWLIVW is defined in a similar manner to TdIVW_total, except that here it is a DQS invalid window with respect to CK. This would need to account for all voltage and temperature (VT) drift terms between CK and DQS within the device that affect the write leveling invalid window. The figure below shows the DQS input mask for timing with respect to CK. The “total” mask (tWLIVW) defines the time the input signal must not encroach in order for the DQS input to be successfully captured by CK. The mask is a receiver property and it is not the valid data-eye. DQS_t/DQS_c to CK_t/CK_c Timings at the Pins Referenced from the Internal Latch

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 166/300 MULTIPURPOSE Operation The device uses the MULTIPURPOSE command to issue a NO OPERATION (NOP) command and to access various training modes. The MPC command is initiated with CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the Command Truth Table. The MPC command has seven operands (OP[6:0]) that are decoded to execute specific commands in the SDRAM. OP[6] is a special bit that is decoded on the first rising CK edge of the MPC command. When OP[6] = 0, the device executes a NOP command, and when OP[6] = 1, the device further decodes one of several training commands. When OP[6] = 1 and the training command includes a READ or WRITE operation, the MPC command must be followed immediately by a CAS-2 command. For training commands that read or write, READ latency (RL) and WRITE latency (WL) are counted from the second rising CK edge of the CAS-2 command with the same timing relationship as a typical READ or WRITE command. The operands of the CAS-2 command following a MPC READ/WRITE command must be driven LOW. The following MPC commands must be followed by a CAS-2 command:  WRITE-FIFO  READ-FIFO  READ DQ CALIBRATION All other MPC commands do not require a CAS-2 command, including the following:  NOP  START DQS INTERVAL OSCILLATOR  STOP DQS INTERVAL OSCILLATOR  ZQCAL START (ZQ CALIBRATION START)  ZQCAL LATCH (ZQ CALIBRATION LATCH) MPC Command Definition SDR Command SDR Command Pins SDR CA Pins CK_t Edge Note CKE CS CA0 CA1 CA2 CA3 CA4 CA5 CK_t (n-1) CK_t(n) MPC (Train, NOP) H H H L L L L L OP6 1, 2 L OP0 OP1 OP2 OP3 OP4 OP5 Note: 1. See the Command Truth Table for more information. 2. MPC commands for READ or WRITE TRAINING operations must be immediately followed by the CAS -2 command, consecutively, without any other commands in between. The MPC command must be issued before issuing the CAS -2 command.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 167/300 MPC Commands Function Operand Data Training Modes OP[6:0] 0XXXXXXb: NOP 1000001b: READ-FIFO: READ-FIFO supports only BL16 operation 1000011b: READ DQ CALIBRATION (MR32/MR40) 1000101b: RFU 1000111b: WRITE-FIFO: WRITE-FIFO supports only BL16 operation 1001001b: RFU 1001011b: START DQS OSCILLATOR 1001101b: STOP DQS OSCILLATOR 1001111b: ZQCAL START 1010001b: ZQCAL LATCH All Others: Reserved Note: 1. See command truth table for more information. 2. MPC commands for READ or WRITE TRAINING operations must be immediately followed by CAS-2 command consecutively without any other commands in -between. MPC command must be issued first before issuing the CAS -2 command. 3. WRITE-FIFO and READ-FIFO commands will only operate as BL16, ignoring the burst length selected by MR1 OP[1:0]. WRITE-FIFO – tWPRE = 2nCK, tWPST = 0.5nCK Note: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active, during refresh or during self refresh, with CKE HIGH. 2. Write-1 to MPC is shown as an example of command -to-command timing for MPC. T iming from Write -1 to MPC[WRITE-FIFO] is tWRWTR. 3. Seamless MPC[WRITE-FIFO] commands may be executed by repeating the command every tCCD time. 4. MPC[WRITE-FIFO] uses the same command-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a WRITE-1 command. 5. A maximum of five MPC[WRITE-FIFO] commands may be executed consecutively without corrupting FIFO data. The sixth MPC[WRITE-FIFO] command will overwrite the FIFO data from the first command. If fewer than five MPC[WRITE -FIFO] commands are executed, then the remaining FIFO locations will contain undefined data. 6. For the CAS-2 command following an MPC command, the CAS-2 operands must be driven LOW. 7. To avoid corrupting the FIFO contents, MPC[READ-FIFO] must immediately follow MPC[WRITE-FIFO]/CAS-2 without any other commands in-between. See Write Training section for more information on FIFO pointer behavior.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 168/300 READ-FIFO – tWPRE = 2nCK, tWPST = 0.5nCK, tRPRE = Toggling, tRPST = 1.5nCK Note: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active, during refresh or during self refresh with CKE HIGH. 2. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time. 3. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a READ-1 command. 4. Data may be continuously read from the FIFO without any data corruption. After five MPC[READ -FIFO] commands, the FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE -FIFO] commands were executed, then the MPC[R EAD-FIFO] commands to those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior. 5. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW. 6. DMI[1:0] signals will be driven if WR -DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training for more information on DMI behavior.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 169/300 READ-FIFO – tRPRE = Toggling, tRPST = 1.5nCK Note: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active, during refresh or during self refresh with CKE HIGH. 2. MPC[READ-FIFO] to READ -1 operation is shown as an example of command -to-command timing for MPC. Timing from MPC[READ-FIFO] command to read is tRTRRD. 3. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time. 4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a READ-1 command. 5. Data may be continuously read from the FIFO without any data corruption. After five MPC[READ -FIFO] commands, th e FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE -FIFO] commands are executed, then the MPC[READ-FIFO] commands to those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior. 6. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW. 7. DMI[1:0] signals will be driven if WR -DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training for more information on DMI behavior.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 170/300 Timing Constraints for Training Commands Previous Command Next Command Minimum Delay Unit Note WR/MWR MPC[WRITE-FIFO] tWRWTR nCK 1 MPC[READ-FIFO] Not allowed – 2 MPC[READ DQ CALIBRATION] WL + RU(tDQSS(MAX)/tCK) + BL/2 + RU(tWTR/tCK) nCK RD/MRR MPC[WRITE-FIFO] tRTRRD nCK 3 MPC[READ-FIFO] Not allowed – 2 MPC[READ DQ CALIBRATION] tRTRRD nCK 3 MPC[WRITE-FIFO] WR/MWR Not allowed – 2 MPC[WRITE-FIFO] tCCD nCK RD/MRR Not allowed – 2 MPC[READ-FIFO] WL + RU(tDQSS(MAX)/tCK) + BL/2 + RU(tWTR/tCK) nCK MPC[READ DQ CALIBRATION] Not allowed – 2 MPC[READ-FIFO] WR/MWR tRTRRD nCK 3 MPC[WRITE-FIFO] tRTW nCK 4 RD/MRR tRTRRD nCK 3 MPC[READ-FIFO] tCCD nCK MPC[READ DQ CALIBRATION] tRTRRD nCK 3 MPC[READ DQ CALIBRATION] WR/MWR tRTRRD nCK 3 MPC[WRITE-FIFO] tRTRRD nCK 3 RD/MRR tRTRRD nCK 3 MPC[READ-FIFO] Not allowed – 2 MPC[READ DQ CALIBRATION] tCCD nCK Note: 1. tWRWTR = WL + BL/2 + RU(tDQSS(MAX)/tCK) + MAX(RU(7.5ns/tCK), 8nCK). 2. No commands are allowed between MPC[ WRITE-FIFO] and MPC[READ -FIFO] except the MRW commands related to training parameters. 3. tRTRRD = RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) + MAX(RU(7.5ns/tCK), 8nCK). 4. In case of DQ ODT disable MR11 OP[2:0] = 000b, tRTW = RL + RU( tDQSCK(MAX)/tCK) + BL/2 - WL + tWPRE + RD(tRPST). In case of DQ ODT enable MR11 OP[2:0] ≠ 000b, tRTW = RL + RU(tDQSCK(MAX)/tCK) + BL/2 + RD(tRPST) - ODTLon - RD(tODTon(MIN)/tCK) + 1.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 171/300 Read DQ Calibration Training The READ DQ CALIBRATION TRAINING function outputs a 16-bit, user-defined pattern on the DQ pins. Read DQ calibration is initiated by issuing a MPC[READ DQ CALIBRATION] command followed by a CAS -2 command, which causes the device to drive the contents of MR32, followed by the contents of MR40 on each of DQ[15:0] and DMI[1:0]. The pattern can be inverted on selected DQ pins according to user-defined invert masks written to MR15 and MR20. Read DQ Calibration Training Procedure 1. Issue MRW commands to write MR32 (first eight bits), MR40 (second eight bits), MR15 (eight -bit invert mask for byte 0), and MR20 (eight-bit invert mask for byte 1). In the alternative, this step could be replaced with the default pattern:  MR32 default = 5Ah  MR40 default = 3Ch  MR15 default = 55h  MR20 default = 55h 2. Issue an MPC command, followed immediately by a CAS-2 command.  Each time an MPC command, followed by a CAS -2, is received by the device, a 16 -bit data burst will drive the eight bits programmed in MR32 followed by the eight bits programmed in MR40 on all I/O pins after the currently set RL.  The data pattern will be inverted for I/O pins with a 1 programmed in the corresponding invert mask mode register bit (see table below).  The pattern is driven on the DMI pins, but no DATA BUS INVERSION function is enabled, even if read DBI is enabled in the mode register.  The MPC command can be issued every tCCD seamlessly, and tRTRRD delay is required between ARRAY READ command and the MPC command as well the delay required between the MPC command and an ARRAY READ.  The operands received with the CAS-2 command must be driven LOW. 3. DQ Read DQ calibration training can be performed with any or no banks active during refresh or during self refresh with CKE HIGH. Invert Mask Assignments DQ pin 0 1 2 3 DMI0 4 5 6 7 MR15 bit 0 1 2 3 N/A 4 5 6 7 DQ pin 8 9 10 11 DMI1 12 13 14 15 MR20 bit 0 1 2 3 N/A 4 5 6 7

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 172/300 Read DQ Calibration Training Timing: Read-to-Read DQ Calibration Note: 1. Read-1 to MPC operation is shown as an example of command -to-command timing. Timing from Read -1 to MPC command is tRTRRD. 2. MPC uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command. 3. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK. 4. DES commands are shown for ease of illustration; other commands may be valid at these times. Read DQ Calibration Training Timing: Read DQ Calibration to Read DQ Calibration/Read Note: 1. MPC[READ DQ CALIBRATION] to MPC[READ DQ CALIBRATION] operation is shown as an example of command-to-command timing. 2. MPC[READ DQ CALIBRATION] to READ-1 operation is shown as an example of command- to-command timing. 3. MPC[READ DQ CALIBRATION] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a READ-1 command. 4. Seamless MPC[READ DQ CALIBRATION] commands may be executed by repeating the command every tCCD time. 5. Timing from MPC[READ DQ CALIBRATION] command to READ-1 is tRTRRD. 6. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK. 7. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 173/300 Read DQ Calibration Training Example An example of read DQ calibration training output is shown in table below. This shows the 16-bit data pattern that will be driven on each DQ in byte 0 when one READ DQ CALIBRATION TRAINING command is executed. This output assumes the following mode register values are used:  MR32 = 1CH  MR40 = 59H  MR15 = 55H  MR20 = 55H Read DQ Calibration Bit Ordering and Inversion Example Pin Bit Sequence → Invert 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DQ0 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ1 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ2 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ3 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DMI0 Never 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ4 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ5 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ6 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ7 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ8 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ9 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ10 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ11 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DMI1 Never 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ12 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ13 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ14 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ15 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 Note: 1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0] when read DQ calibration is initiated via a MPC[READ DQ CALIBRATION] command. The pattern transmitted serially on each data lane, organized little endian such that the low- order bit in a byte is transmitted first. If the data pattern is 27H, then the first bit transmitted with be a 1, followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111 →. 2. MR15 and MR20 may be used to invert the MR32/MR40 data pattern on the DQ pins. See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins. 3. DMI [1:0] outputs status follows MR Setting vs. DMI Status table. 4. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3-OP[6].

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 174/300 MR Setting vs. DMI Status DM Function MR13 OP[5] WRITE DBIdc Function MR3 OP[7] READ DBIdc Function MR3 OP[6] DMI Status 1: Disable 0: Disable 0: Disable High-Z 1: Disable 1: Enable 0: Disable The data pattern is transmitted 1: Disable 0: Disable 1: Enable The data pattern is transmitted 1: Disable 1: Enable 1: Enable The data pattern is transmitted 0: Enable 0: Disable 0: Disable The data pattern is transmitted 0: Enable 1: Enable 0: Disable The data pattern is transmitted 0: Enable 0: Disable 1: Enable The data pattern is transmitted 0: Enable 1: Enable 1: Enable The data pattern is transmitted MPC[READ DQ CALIBRATION] After Power-Down Exit Following the power -down state, an additional time, tMRRI, is required prior to issuing the MPC[READ DQ CALIBRATION] command. This additional time (equivalent to tRCD) is required in order to be able to maximize power-down current savings by allowing more power-up time for the read DQ data in MR32 and MR40 data path after exit from standby, power-down mode. MPC[READ DQ CALIBRATION] Following Power-Down State

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 175/300 Write Training The device uses an unmatched DQS-DQ path to enable high-speed performance and save power. As a result, the DQS strobe must be trained to arrive at the DQ latch centeraligned with the data eye. The DQ receiver is located at the DQ pad and has a shorter internal delay than the DQS signal. The DQ receiver will latch the data present on the DQ bus when DQS reaches the latch, and training is accomplished by delaying the DQ signals relative to DQS such that the data eye arrives at the receiver latch centered on the DQS transition. Two modes of training are available:  Command-based FIFO WR/RD with user patterns  An internal DQS clock-tree oscillator, which determines the need for, and the magnitude of, required training The command-based FIFO WR/RD uses the MPC command with operands to enable this special mode of operation. When issuing the MPC command, if CA[5] is set LOW (OP[6] = 0), then the device will perform a NOP command. When CA[5] is set HIGH, the CA[4:0] pins enable training functions or are reserved for future use (RFU). MPC commands that initiate a read or write to the device must be followed immediately by a CAS-2 command. See the MPC Operation section for more information. To perform write training, the controller can issue an MPC[WRITE-FIFO] command with OP[6:0] set, followed immediately by a CAS-2 command (CAS -2 operands should be d riven LOW) to initiate a WRITE -FIFO. Timings for MPC[WRITE -FIFO] are identical to WRITE commands, with WL timed from the second rising clock edge of the CAS-2 command. Up to five consecutive MPC[WRITE-FIFO] commands with user-defined patterns may be issued to the device, which will store up to 80 values (BL16 × 5) per pin that can be read back via the MPC[READ -FIFO] command. (The WRITE/READ -FIFO POINTER operation is described in a different section. After writing data with the MPC[WRITE-FIFO] command, the data can be read back with the MPC[READ-FIFO] command and results can be compared with "expected" data to determine whether further training (DQ delay) is needed. MPC[READ-FIFO] is initiated by issuing an MPC command, as described in the MPC Operation section, followed immediately by a CAS-2 command (CAS-2 operands must be driven LOW). Timings for the MPC[READ -FIFO] command are identical to READ commands, with RL timed from the second rising clock edge of the CAS-2 command. READ-FIFO is nondestructive to the data captured in the FIFO; data may be read continuously until it is disturbed by another command, such as a READ, WRITE, or another MPC[WRITE -FIFO]. If fewer than five WRITE-FIFO commands are executed, unwritten registers will have undefined (but valid) data when read back. For example: If five WRITE-FIFO commands are executed sequentially, then a series of READ-FIFO commands will read valid data from FIFO[0], FIFO[1]….FIFO[4] and then wrap back to FIFO[0] on the next READ -FIFO. However, if fewer than fiv e WRITE-FIFO commands are executed sequentially (example = 3), then a series of READ-FIFO commands will return valid data for FIFO[0], FIFO[1], and FIFO[2], but the next two READ - FIFO commands will return undefined data for FIFO[3] and FIFO[4] before wrapping back to the valid data in FIFO[0]. The READ-FIFO pointer and WRITE-FIFO pointer are reset under the following conditions:  Power-up initialization  RESET_n asserted  Power-down entry  Self refresh power-down entry The MPC[WRITE-FIFO] command advances the WRITE-FIFO pointer, and the MPC[READ -FIFO] advances the READ -FIFO pointer. Also any normal (non-FIFO) READ operation (RD, RDA) advances both WRITE-FIFO pointer and READ-FIFO pointer. Issuing (non-FIFO) READ operation command is inhibited during write train ing period. To keep the pointers aligned, the SoC memory controller must adhere to the following re- striction at the end of Write training period: b = a + (n × c) Where:  'a' is the number of MPC[WRITE-FIFO] commands  'b' is the number of MPC[READ-FIFO] commands 'c' is the FIFO depth (= 5 for LPDDR4)  'n' is a positive integer, ≥0

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 176/300 WRITE-to-MPC[WRITE-FIFO] Operation Timing Note: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during REFRESH or during SELF REFRESH with CKE HIGH. 2. Write-1 to MPC is shown as an example of command -to-command timing for MPC. Timing from Write -1 to MPC[WRITE-FIFO] is tWRWTR. 3. Seamless MPC[WR-FIFO] commands may be executed by repeating the command every tCCD time. 4. MPC[WRITE-FIFO] uses the same comma nd-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a WRITE -1 command. 5. A maximum of five MPC[WRITE -FIFO] commands may be executed consecutively without corrupting FIFO data. The sixth MPC[WRITE -FIFO] command will overwrite the FIFO data from the first c ommand. If fewer than five MPC[WRITE-FIFO] commands are executed, then the remaining FIFO locations will contain undefined data. 6. For the CAS-2 command following an MPC command, the CAS-2 operands must be driven LOW. 7. To avoid corrupting the FIFO contents, MPC[READ-FIFO] must immediately follow MPC[WRITE -FIFO]/CAS-2 without any other commands disturbing FIFO pointers in between. FIFO pointers are disturbed by CKE LOW, WRITE, MASKED WRITE, READ, READ DQ CALIBRATION, and MRR. 8. BL = 16, Write postamble = 0.5nCK. 9. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 177/300 MPC[WRITE-FIFO]-to-MPC[READ-FIFO] Timing Note: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during refresh or during self refresh with CKE HIGH. 2. MPC[WRITE-FIFO] to MPC[READ-FIFO] is shown as an example of command-to-command timing for MPC. Timing from MPC[WRITE-FIFO] to MPC[READ-FIFO] is specified in the command-to-command timing table. 3. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time. 4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ ) as a READ-1 command. 5. Data may be continuously read from the FIFO without any data corruption. After five MPC[ READ-FIFO] commands, the FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE -FIFO] commands were executed, then the MPC[READ -FIFO] commands to those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior. 6. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW. 7. DMI[1:0] signals will be driven if WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more information on DMI behavior. 8. BL = 16, Write postamble = 0.5nCK, Read preamble: Toggle, Read postamble: 0.5nCK. 9. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 178/300 MPC[READ-FIFO] to Read Timing Note: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during refresh or during self refresh with CKE HIGH. 2. MPC[READ-FIFO] to READ -1 operation is shown as an example of command -to-command timing for MPC. Timing from MPC[READ-FIFO] command to READ is tRTRRD. 3. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time. 4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ ) as a READ-1 command. 5. Data may be continuo usly read from the FIFO without any data corruption. After five MPC[READ -FIFO] commands, the FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE -FIFO] commands were executed, then the MPC[READ -FIFO] commands t o those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior. 6. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW. 7. DMI[1:0] signals will be driven if WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training for more information on DMI behavior. 8. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK 9. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 179/300 MPC[WRITE-FIFO] with DQ ODT Timing Note: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during refresh or during self refresh with CKE HIGH. 2. MPC[WRITE-FIFO] uses the same command-to-data/ODT timing relationship (RL, tDQSCK, tDQS2DQ, ODTLon, ODTLoff, tODTon, tODToff) as a WRITE-1 command. 3. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW. 4. BL = 16, Write postamble = 0.5nCK. 5. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 180/300 Power-Down Exit to MPC[WRITE-FIFO] Timing Note: 1. Any commands except MPC[WRITE -FIFO] and other exception commands defined other section in this document (for example. MPC[READ DQ CALIBRATION]). 2. DES commands are shown for ease of illustration; other commands may be valid at these times. MPC[WRITE-FIFO] AC Timing Parameter Symbol MIN/MAX Value Unit Additional time after tXP has expired until MPC[WRITE-FIFO] command may be issued tMPCWR MIN tRCD + 3nCK –

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 181/300 Internal Interval Timer As voltage and temperature change on the device, the DQS clock-tree delay will shift, requiring retraining. The device includes an internal DQS clock-tree oscillator to measure the amount of delay over a given time interval (determi ned by the controller), allowing the controller to compare the trained delay value to the delay value seen at a later time. The DQS oscillator will provide the controller with important information regarding the need to retrain and the magnitude of potential error. The DQS interval oscillator is started by issuing an MPC command with OP[6:0] set as described in MPC Operation, which will start an internal ring oscillator that counts the number of time a signal propagates through a copy of the DQS clock tree. The DQS oscillator may be stopped by issuing an MPC[STOP DQS OSCILLATOR] command with OP[6:0] set as described in MPC Operation, or the controller may instruct the SDRAM to count for a specific number of clocks and then stop automatically (See MR23 for mo re information). If MR23 is set to automatically stop the DQS oscillator, then the MPC[STOP DQS OSCILLATOR] command should not be used (illegal). When the DQS oscillator is stopped by either method, the result of the oscillator counter is automatically stored in MR18 and MR19. The controller may adjust the accuracy of the result by running the DQS interval oscillator for shorter (less accurate) or lo nger (more accurate) duration. The accuracy of the result for a given temperature and voltage is determined b y the following equation, where run time = total time between START and STOP commands and DQS delay = the value of the DQS clock tree delay (tDQS2DQ(MIN)/(MAX)): DQS oscillator granularity error = 2 x (DQS delay) run time Additional matching error must be included, which is the difference between DQS training circuit and the actual DQS clock tree across voltage and temperature. The matching error is vendor specific. Therefore, the total accuracy of the DQS oscillator counter is given by: DQS oscillator accuracy = 1 - granularity error - matching error For example, if the total time between START and STOP commands is 100ns, and the maximum DQS clock tree delay is 800ps (tDQS2DQ(MAX)), then the DQS oscillator granularity error is: DQS oscillator granularity error = 2 x (0.8ns) 100ns = 1.6% This equates to a granularity timing error of 12.8ps. Assuming a circuit matching error of 5.5ps across voltage and temperature, the accuracy is: DQS oscillator accuracy = 1 - 12.8 + 5.5 800 = 97.7% For example, running the DQS oscillator for a longer period improves the accuracy. If the total time between START and STOP commands is 500ns, and the maxim um DQS clock tree delay is 800ps ( tDQS2DQ(MAX)), then the DQS oscillator granularity error is: DQS oscillator granularity error = 2 x (0.8ns) 500ns = 0.32%

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 182/300 This equates to a granularity timing error or 2.56ps. Assuming a circuit matching error of 5.5ps across voltage and temperature, the accuracy is: DQS oscillator accuracy = 1 - 2.56 + 5.5 800 = 99.0% The result of the DQS interval oscillator is defined as the number of DQS clock tree delays that can be counted within the ru n time, determined by the controller. The result is stored in MR18-OP[7:0] and MR19-OP[7:0]. MR18 contains the least significant bits (LSB) of the result, and MR19 contains the most significant bits (MSB) of the result . MR18 and MR19 are overwritten by the SDRAM when a MPC[STOP DQS OSCILLATOR] command is received. The SDRAM counter will count to its maximum value (= 2^16) and stop. If the maximum value is read from the mode registers, the memory controller must assume that the counter overflowed the register and therefore discard the result. The longest run time for the oscillator that will not overflow the counter registers can be calculated as follows: Longest runtime interval = 216 x tDQS2DQ(MIN) = 216 × 0.2ns = 13.1µs

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 183/300 DQS Interval Oscillator Matching Error The interval oscillator matching error is defined as the difference between the DQS training ckt (interval oscillator) and the actual DQS clock tree across voltage and temperature. Parameters:  tDQS2DQ: Actual DQS clock tree delay  tDQSOSC: Training ckt (interval oscillator) delay  OSCOffset: Average delay difference over voltage and temperature (shown below)  OSCMatch: DQS oscillator matching error Interval Oscillator Offset – OSCoffset tDQSOSC(V,T) = [ Runtime 2 x Count OSCMatch = [ tDQS2DQ(V,T) - tDQSOSC (V,T) - OSCoffset ] OSCMatch : tDQSOSC: DQS Oscillator Matching Error Specification Parameter Symbol MIN MAX Unit Note DQS oscillator matching error OSCMatch –20 20 ps 1, 2, 3, 4, 5, 6, 7, 8 DQS oscillator offset OSCoffset –100 100 ps 2, 4. 7 Note: 1. The OSCMatch is the matching error per between the actual DQS and DQS interval oscillator over voltage and temperature. 2. This parameter will be characterized or guaranteed by design.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 184/300 3. The OSCMatch is defined as the following: OSCMatch = [tDQS2DQ(V,T) - tDQSOSC(V,T) - OSCof f set ] Where tDQS2DQ(V,T) and tDQSOSC(V,T) are determined over the same voltage and temperature conditions. 4. The runtime of the oscillator must be at least 200ns for determining tDQSOSC(V,T). tDQSOSC(V,T) = [ Runtime 2 x Count 5. The input stimulus for tDQS2DQ will be consistent over voltage and temperature conditions. 6. The OSCoffset is the average difference of the endpoints across voltage and temperature. 7. These parameters are defined per channel. 8. tDQS2DQ(V,T) delay will be the average of DQS-to-DQ delay over the runtime period. OSC Count Readout Time OSC Stop to its counting value readout timing is shown in following figures. In Case of DQS Interval Oscillator is Stopped by MPC Command Note: 1. DQS interval timer run time setting :MR23 OP[7:0] = 00000000b.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 185/300 In Case of DQS Interval Oscillator is Stopped by DQS Interval Timer Note: 1. DQS interval timer run time setting :MR23 OP[7:0] = 00000000b. 2. Setting counts of MR23. DQS Interval Oscillator AC Timing Parameter Symbol MIN/MAX Value Unit Delay time from OSC stop to mode register readout tOSCO MIN MAX (40ns, 8nCK) ns Note: 1. START DQS OSCILLATOR command is prohibited until tOSCO(MIN) is satisfied.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 186/300 Thermal Offset Because of tight thermal coupling, hot spots on an SOC can induce thermal gradients across the device. Because these hot spots may not be located near the thermal sensor, the temperature compensated self refresh (TCSR) circuit may not generate enough refresh cycles to guarantee memory retention. To address this shortcoming, the controller can provide a thermal offset that the memory can use to adjust its TCSR circuit to ensure reliable operation. This thermal offset is provided through MR4 OP[6:5] to either or both channels (dual- channel devices). This temperature offset may modify refresh behaviour for the channel to which the offset is provided. It will take a maximum of 200µs to have the change re - flected in MR4 OP[2:0] for the channel to which the offset is provided. If the in duced thermal gradient from the device temperature sensor location to the hot spot location of the controller is greater than 15°C, self refresh mode will no t reliably maintain memory contents. To accurately determine the temperature gradient between the m emory thermal sensor and the induced hot spot, the memory thermal sensor location must be provided to the controller. Temperature Sensor The device has a temperature sensor that can be read from MR4. This sensor can be used to determine the appropriate refresh rate, to determine whether AC timing de -rating is required at an elevated temperature range, and to monitor the operating temperature. Either the temperature sensor or the device TC can be used to determine if operating temperature requirements are being met. The device monitors device temperature and updates MR4 according to tTSI. Upon exiting self refresh or power -down, the device temperature status bits shall be no older than tTSI. When using the temperature sensor, the actual device case temperature may be higher than the TC specification that applies to standard or elevated temperature ranges. For example, TC may be above 85°C when MR4[2:0] = b011. The device enables a 2°C temperature margin between the point when the device updates the MR4 value and the point when the controller reconfigures the system accordingly. When performing tight thermal coupling of the device to external ho t spots, the maximum device temperature may be higher than indicated by MR4. To ensure proper operation when using the temperature sensor, consider the following:  TempGradient is the maximum temperature gradient experienced by the device at the temperature of interest over a range of 2°C.  ReadInterval is the time period between MR4 reads from the system.  TempSensorInterval (tTSI) is the maximum delay between the internal updates of MR4.  SysRespDelay is the maximum time between a read of MR4 and a response from the system. In order to determine the required frequency of polling MR4, the system uses the TempGradient and the maximum response time of the system in the following equation: TempGradient × (ReadInterval + tTSI + SysRespDelay) ≤ 2°C

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 187/300 Temperature Sensor Parameter Symbol Max/Min Value Unit System temperature gradient TempGradient MAX System Dependent °C/s MR4 read interval ReadInterval MAX System Dependent ms Temperature sensor interval tTSI MAX 32 ms System response delay SysRespDelay MAX System Dependent ms Device temperature margin TempMargin MAX 2 °C For example, if TempGradient is 10°C/s and the SysRespDelay is 1ms: (10°C/s) x (ReadInterval + 32ms + 1ms) ≤ 2°C In this case, ReadInterval shall be no greater than 167ms. Temperature Sensor Timing

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 188/300 ZQ Calibration The MPC command is used to initiate ZQ calibration, which calibrates the output driver impedance and CA/DQ ODT impedance across process, temperature, and voltage. ZQ calibration occurs in the background of device operation and is designed to eliminate any need for coordination between channels (that is, it allows for channel independence). ZQ calibration is require d each time that the PU -Cal value (MR3 -OP[0]) is changed. Additional ZQ CALIBRATION commands may be required as the voltage and temperature change in the system environment. CA ODT values (MR11 -OP[6:4]) and DQ ODT values (MR11-OP[2:0]) may be changed without performing ZQ calibration, as long as the PU-Cal value doesn’t change. There are two ZQ calibration modes ini tiated with the MPC command: ZQCAL START and ZQCAL LATCH. ZQCAL START initiates the calibration procedure, and ZQCAL LATCH captures the result and loads it into the drivers. A ZQCAL START command may be issued anytime the device is not in a power -down state. A ZQCAL LATCH command may be issued anytime outside of power -down after tZQCAL has expired and all DQ bus operations have completed. The CA bus must maintain a deselect state during tZQLAT to allow CA ODT calibration settings to be updated. The DQ calibration value will not be updated until ZQCAL LATCH is performed and tZQLAT has been met. The following mode register fields that modify I/O parameters cannot be changed following a ZQCAL START command and before tZQCAL has expired:  PU-Cal (pull-up calibration VOH point)  PDDS (pull-down drive strength and Rx termination)  DQ ODT (DQ ODT value)  CA ODT (CA ODT value)

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 189/300 ZQCAL Reset The ZQCAL RESET command resets the output impedance calibration to a default accuracy of ±30% across process, voltage, and temperature. This command is used to ensure output impedance accuracy to ±30% when ZQCAL START and ZQCAL LATCH commands are not used. The ZQCAL RESET command is executed by writing MR10-OP[0] = 1B. ZQ Calibration Parameters Parameter Symbol Min/Max Value Unit ZQCAL START to ZQCAL LATCH command interval tZQCAL MIN 1 µs ZQCAL LATCH to next valid command interval tZQLAT MIN MAX(30ns, 8nCK) ns ZQCAL RESET to next valid command interval tZQRESET MIN MAX(50ns, 3nCK) ns ZQCAL Timing Note: 1. WRITE and PRECHARGE operations are shown for illustrative purposes. Any single or multiple valid commands may be executed within the tZQCAL time and prior to latching the results. 2. Before the ZQCAL LATCH command can be executed, any prior commands that utilize the DQ bus must have completed. WRITE commands with DQ termination must be given enough time to turn off the DQ ODT before issuing the ZQCAL LATCH command. See the ODT section for ODT timing.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 190/300 Multichannel Considerations The device includes a single ZQ pin and associated ZQ calibration circuitry. Calibration values from this circuit will be used by both channels according to the following protocol:  The ZQCAL START command can be issued to either or both channels.  The ZQCAL START command can be issued wh en either or both channels are executing other commands, and other commands can be issued during tZQCAL.  The ZQCAL START command can be issued to both channels simultaneously.  The ZQCAL START command will begin the calibration unless a previously requested ZQ calibration is in progress.  If the ZQCAL START command is received while a ZQ calibration is in progress, the command will be ignored and the in-progress calibration will not be interrupted.  The ZQCAL LATCH command is required for each channel.  The ZQCAL LATCH command can be issued to both channels simultaneously.  The ZQCAL LATCH command will latch results of the most recent ZQCAL START command provided tZQCAL has been met.  ZQCAL LATCH commands that do not meet tZQCAL will latch the results of the most recently completed ZQ calibration.  The ZQRESET MRW commands will only reset the calibration values for the channel issuing the command. In compliance with complete channel independence, either channel may issue ZQCAL START and ZQCAL LATCH commands as needed without regard to the state of the other channel. ZQ External Resistor, Tolerance, and Capacitive Loading To use the ZQ CALIBRATION function, a 240 ohms, ±1% tolerance external resistor must be connected between the ZQ pin and VDDQ. If the system configuration shares the CA bus to form a x32 (or wider) channel, the ZQ pin of each die’s x16 channel must use a separate ZQCAL resistor. If the system configuration has more than one rank, and if the ZQ pins of both ranks are attached to a single resistor, then the SDRAM controller must ensure that the ZQCAL's don’t overlap. The total capacitive loading on the ZQ pin must be limited to 25pF. For example, if a system configuration shares a CA bus between n channels to form an n x16 wide bus, and no means are available to control the ZQCAL separately for each channel (that is, separate CS, CKE, or CK), then each x16 channel must have a separate ZQCAL resistor. For a x32, two -rank system, each x16 channel must have its own ZQCAL resistor, but th e ZQCAL resistor can be shared between ranks on each x16 channel. In this configuration, the CS signal can be used to ensure that the ZQCAL commands for Rank[0] and Rank[1] don’t overlap.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 191/300 Frequency Set Points Frequency set points enable the CA bus to be switched between two differing operating frequencies with changes in voltage swings and termination values, without ever being in an untrained state, which could result in a loss of communication to the device. This is accomplished by duplicating all CA bus mode register parameters, as well as other mode register parameters commonly changed with operating frequency. These duplicated registers form two sets that use the same mode register addresses, with read/write access controlled by MR bit FSP-WR (frequency set point write/read) and the operating point controlled by MR bit FSP -OP (FREQUENCY SET POINT operation). Changing the FSP -WR bit enables MR parameters to be changed for an alternate frequency set point without affecting the current operation. Once all necessary parameters have been written to the alternate set point, changing the FSP -OP bit will switch operation to use all of the new parameters simultaneously (within tFC), eliminating the possibility of a loss of communication that could be caused by a partial configuration change. Parameters that have two physical registers controlled by FSP-WR and FSP-OP include those in the following table. Mode Register Function With Two Physical Registers MR Number Operand Function Note MR1 OP[2] WR-PRE (Write preamble length) OP[3] RD-PRE (Read preamble type) OP[6:4] nWR (Write-recovery for AUTO PRECHARGE command) OP[7] RD-PST (Read postamble length) MR2 OP[2:0] RL (READ latency) OP[5:3] WL (WRITE latency) OP[6] WLS (WRITE latency set) MR3 OP[0] PU-CAL (Pull-up calibration point) 1 OP[1] WR-PST(Write postamble length) OP[5:3] PDDS (Pull-down drive strength) OP[6] DBI-RD (DBI-read enable) OP[7] DBI-WR (DBI-write enable) MR11 OP[2:0] DQ ODT (DQ bus receiver on-die termination) OP[6:4] CA ODT (CA bus receiver on-die termination) MR12 OP[5:0] VREF(CA) (VREF(CA) setting) OP[6] VRCA (VREF(CA) range) MR14 OP[5:0] VREF(DQ) (VREF(DQ) setting) OP[6] VRDQ (VREF(DQ) range) MR22 OP[2:0] SOC ODT (Controller ODT value for VOH calibration) OP[3] ODTE-CK (CK ODT enabled for non-terminating rank) OP[4] ODTE-CS (CS ODT enable for non-terminating rank) OP[5] ODTD-CA (CA ODT termination disable) Note: 1. For dual-channel devices, PU-CAL setting is required as the same value for both Ch.A and Ch.B before issuing ZQCAL START command. See Mode Register Definition section for more details. The table below shows how the two mode registers for each of the parameters in the previous table can be modified by setting the appropriate FSP-WR value and how device operation can be switched between operating points by setting the appropriate FSP-OP value. The FSP-WR and FSP-OP functions operate completely independently.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 192/300 Relation Between MR Setting and DRAM Operation Function MR# and Operand Data Operation Note FSP-WR MR13 OP[6] 0 (default) Data write to mode register N for FSP-OP[0] by MRW command. Data read from mode register N for FSP-OP[0] by MRR command. Data write to mode register N for FSP-OP[1] by MRW command. Data read from mode register N for FSP-OP[1] by MRR command. FSP-OP MR13 OP[7] 0 (default) DRAM operates with mode register N for FSP-OP[0] setting. 1 DRAM operates with mode register N for FSP-OP[1] setting. Note: 1. FSP-WR stands for frequency set point write/read. 2. FSP-OP stands for frequency set point operating point. Frequency Set Point Update Timing The frequency set point update timing is shown below. When changing the frequency set point via MR13 OP[7], the V RCG setting: MR13 OP[3] have to be changed into VREF fast response (high current) mode at the same time. After frequency change time (tFC) is satisfied. VRCG can be changed into normal operation mode via MR13 OP[3]. Frequency Set Point Switching Timing Note: 1. For frequency change during frequency set point switching, refer to Input Clock Stop and Frequency Change section.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 193/300 Frequency Set Point AC Timing Parameter Symbol Min/ Max Data Rate Unit Note 1600 3200 3733 Frequency set point switching time tFC_short MIN 200 ns 1 tFC_middle MIN 200 ns tFC_long MIN 250 ns Valid clock requirement after entering FSP change tCKFSPE MIN MAX(7.5ns, 4nCK) – Valid clock requirement before first valid command after FSP change tCKFSPX MIN MAX(7.5ns, 4nCK) – Note: 1. Frequency set point switching time depends on value of VREF(CA) setting: MR12 OP[5:0] and VREF(CA) range: MR12 OP[6] of FSP-OP 0 and 1. The details are shown in table below. Additionally change of frequency set point may affect V REF(DQ) setting. Settling time of VREF(DQ) level is the same as VREF(CA) level. tFC Value Mapping Application Step Size Range From FSP-OP0 To FSP-OP1 From FSP -OP0 To FSP-OP1 tFC_short Base A single step size increment/decrement Base No change tFC_middle Base Two or more step size increment/decrement Base No change tFC_long – – Base Change Note: 1. As well as change from FSP-OP1 to FSP-OP0. tFC Value Mapping: Example Case From/To FSP-OP: MR13 OP[7] VREF(CA) Setting: MR12: OP[5:0] VREF(CA) Range: MR12 OP[6] Application Note From 0 001100 0 tFC_short 1 To 1 001101 0 From 0 001100 0 tFC_middle 2 To 1 001110 0 From 0 Don't Care 0 tFC_long 3 To 1 Don't Care 1 Note: 1. A single step size increment/decrement for VREF(CA) setting value. 2. Two or more step size increment/decrement for VREF(CA) setting value. 3. VREF(CA) range is changed. In this case, changing VREF(CA) setting doesn’t affect tFC value. The LPDDR4 SDRAM defaults to FSP -OP[0] at power -up. Both set points default to settings neede d to operate in un-terminated, low -frequency environments. To enable the device to operate at higher frequencies, Command bus training mode should be utilized to train the alternate frequency set point. See Command Bus Training section for more details on this training mode.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 194/300 Training for Two Frequency Set Points Once both of the frequency set points have been trained, switching between points can be performed with a single MRW followed by waiting for time tFC. Example of Switching Between Two Trained Frequency Set Points Switching to a third (or more) set point can be accomplished if the memory controller has stored the previously -trained values (in particular the VREF(CA) calibration value) and rewrites these to the alternate set point before switching FSP-OP .

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 195/300 Example of Switching to a Third Trained Frequency Set Point

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 196/300 Pull-Up and Pull-Down Characteristics and Calibration Pull-Down Driver Characteristics – ZQ Calibration RONPD,nom Register Min Nom Max Unit 40 ohms RON40PD 0.90 1.0 1.10 RZQ/6 48 ohms RON48PD 0.90 1.0 1.10 RZQ/5 60 ohms RON60PD 0.90 1.0 1.10 RZQ/4 80 ohms RON80PD 0.90 1.0 1.10 RZQ/3 120 ohms RON120PD 0.90 1.0 1.10 RZQ/2 240 ohms RON240PD 0.90 1.0 1.10 RZQ/1 Note: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%. Pull-Up Characteristics – ZQ Calibration VOHPU,nom VOH,nom Min Nom Max Unit VDDQ × 0.5 300 0.90 1.0 1.10 VOH,nom VDDQ × 0.6 360 0.90 1.0 1.10 VOH,nom Note: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%. 2. VOH,nom (mV) values are based on a nominal VDDQ = 0.6V. Valid Calibration Points VOHPU ODT Value 240 120 80 60 48 40 VDDQ × 0.5 Valid Valid Valid Valid Valid Valid VDDQ × 0.6 DNU Valid DNU Valid DNU DNU Note: 1. After the output is calibrated for a given VOH,nom calibration point, the ODT value may be changed without recalibration. 2. If the VOH,nom calibration point is changed, then recalibration is required. 3. DNU = Do not use.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 197/300 On-Die Termination for the Command/Address Bus The on-die termination (ODT) feature allows the device to turn on/off termination resistance for CK_t, CK_c, CS, and CA[5:0] signals without the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to turn on and off termination resistance for any target DRAM devices via the mode register setting. A simple functional representation of the DRAM ODT feature is shown below. ODT for CA

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 198/300 ODT Mode Register and ODT State Table ODT termination values are set and enabled via MR11. The CA bus (CK_t, CK_c, CS, CA[5:0]) ODT resistance values are set by MR11 OP[6:4]. The default state for the CA is ODT disabled. ODT is applied on the CA bus to the CK_t, CK_c, CS, and CA signals. Generally only one termination load will be present even if multiple devices are sharing the command signals. In contrast to LPDDR4 where the ODT_CA input is used in combination with mode registers, LPDDR4X uses mode registers exclu sively to enable CA termination. Be fore enabling CA termination via MR11, all ranks should have appropriate MR22 termination settings programmed. In a multi rank system, the terminating rank should be trained first, followed by the non-terminating rank(s). Command Bus ODT State CA ODT MR11[6:4] ODTD-CA MR22 OP[5] ODTE-CK MR22 OP[3] ODTE-CS MR22 OP[4] ODT State for CA ODT State for CK ODT State for CS Disabled1 Valid2 Valid2 Valid2 Off Off Off Valid2 0 0 0 On On On Valid2 0 0 1 On On Off Valid2 0 1 0 On Off On Valid2 0 1 1 On Off Off Valid2 1 0 0 Off On On Valid2 1 0 1 Off On Off Valid2 1 1 0 Off Off On Valid2 1 1 1 Off Off Off Note: 1. Default value 2. Valid = 0 or 1

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 199/300 ODT Mode Register and ODT Characteristics RZQ =240Ω ±1% over entire operating range after calibration MR11 OP[6:4] RTT VOUT Min Nom Max Unit Note 001b 240Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/1 1, 2 VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3 010b 120Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/2 1, 2 VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3 011b 80Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/3 1, 2 VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3 100b 60Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/4 1, 2 VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3 101b 48Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/5 1, 2 VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3 110b 40Ω VOL(DC) = 0.2 × VDDQ 0.8 1.0 1.1 RZQ/6 1, 2 VOM(DC) = 0.50 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.75 × VDDQ 0.9 1.0 1.3 Mismatch CA-to-CA within clock group 0.50 × VDDQ – – 2 % 1, 2, 3 Note: 1. The tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the section on voltage and temperature sensitivity. 2. Pull-down ODT resistors are r ecommended to be calibrated at 0.50 × V DDQ. Other calibration points may be used to achieve the linearity specification shown above, for example, calibration at 0.75 × VDDQ and 0.20 × VDDQ. 3. CA to CA mismatch within clock group variation for a given component including CK_t, CK_c ,and CS (characterized). CA mismatch = RODT (AVG) RODT (MAX ) - RODT (MIN)

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 200/300 Output Driver and Termination Register Temperature and Voltage Sensitivity When temperature and/or voltage change after calibration, the tolerance limits are widen according to the tables below. Output Driver and Termination Register Sensitivity Definition Resistor Definition Point Min Max Unit Note RONPD 0.50 × VDDQ 90 - (dRONdT‧|ΔT|) - (dRONdV‧|ΔV|) 110 + (dRONdT‧|ΔT|) + (dRONdV‧|ΔV|) 1, 2 VOHPU 0.50 × VDDQ 90 - (dVOHdT‧|ΔT|) - (dVOHdV‧|ΔV|) 110 + (dVOHdT‧|ΔT|) + (dVOHdV‧|ΔV|) 1, 2 RTT(I/O) 0.50 × VDDQ 90 - (dRONdT‧|ΔT|) - (dRONdV‧|ΔV|) 110 + (dRONdT‧|ΔT|) + (dRONdV‧|ΔV|) 1, 2, 3 RTT(IN) 0.50 × VDD2 90 - (dRONdT‧|ΔT|) - (dRONdV‧|ΔV|) 110 + (dRONdT‧|ΔT|) + (dRONdV‧|ΔV|) 1, 2, 4 Note: 1. ΔT = T - T(@calibration), ΔV = V - V(@calibration) 2. dRONdT, dR ONdV, dV OHdT, dV OHdV, dR TTdV, and dR TTdT are not subject to production test but are verified by design and characterization. 3. This parameter applies to input/output pin such as DQS, DQ, and DMI. 4. This parameter applies to input pin such as CK, CA, and CS. 5. Refer to Pull-Up/Pull-Down Driver Characteristics for VOHPU. Output Driver and Termination Register Temperature and Voltage Sensitivity Symbol Parameter Min Max Unit dRONdT RON temperature sensitivity 0 0.75 %/˚C dRONdV RON voltage sensitivity 0 0.20 %/mV dVOHdT VOH temperature sensitivity 0 0.75 %/˚C dVOHdV VOH voltage sensitivity 0 0.35 %/mV dRTTdT RTT temperature sensitivity 0 0.75 %/˚C dRTTdV RTT voltage sensitivity 0 0.20 %/mV

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 201/300 ODT Mode Register The ODT mode is enabled if MR11 OP[2:0] are non -zero. In this case, the value of R TT is determined by the settings of those bits. The ODT mode is disabled if MR11 OP[2:0] = 0. Asynchronous ODT When ODT mode is enabled in MR11 OP[2:0], DRAM ODT is always High -Z. The DRAM ODT feature is automatically turned ON asynchronously after a WRITE-1, MASK WRITE-1, or MPC[WRITE-FIFO] command. After the burst write is complete, the DRAM ODT turns OFF asynchr onously. The DQ bus ODT control is automatic and will turn the ODT resistance on/off if DQ ODT is enabled in the mode register. The following timing parameters apply when the DQ bus ODT is enabled:  ODTLon, tODTon(MIN), tODTon(MAX)  ODTLoff, tODToff(MIN), tODToff(MAX) ODTLON is a synchronous parameter and is the latency from a CAS-2 command to the tODTon reference. ODTLON latency is a fixed latency value for each speed bin. Each speed bin has a different ODTLON latency. Minimum R TT turn-on time ( tODTon(MIN)) is the point in time when the device termination circuit leaves High -Z and ODT resistance begins to turn on. Maximum RTT turn on time (tODTon(MAX)) is the point in time when the ODT resistance is fully on. tODTon(MIN) and tODTon(MAX) are measured after ODTLON latency is satisfied from CAS-2 command. ODTLOFF is a synchronous parameter and it is the latency from CAS -2 command to tODToff reference. ODTL OFF latency is a fixed latency value for each speed bin. Each speed bin has a different ODTLOFF latency. Minimum RTT turn -off time ( tODToff(MIN)) is the point in time when the device termination circuit starts to turn off the ODT resistance. Maximum ODT turn off time (tODToff(MAX)) is the point in time when the on-die termination has reached High-Z. tODToff(MIN) and tODToff(MAX) are measured after ODTLOFF latency is satisfied from CAS-2 command. ODTLON and ODTLOFF Latency Values ODTLON Latency1 ODTLOFF Latency2 Lower Frequency Limit (>) (MHz) Upper Frequency Limit (≤) (MHz) tWPRE = 2tCK WL Set A (nCK) WL Set B (nCK) WL Set A (nCK) WL Set B (nCK) N/A N/A N/A N/A 10 266 N/A N/A N/A N/A 266 533 N/A 6 N/A 22 533 800 4 12 20 28 800 1066 4 14 22 32 1066 1333 6 18 24 36 1333 1600 6 20 26 40 1600 1866 Note: 1. ODTLON is referenced from CAS-2 command. 2. ODTLOFF as shown in table assumes BL = 16. For BL32, 8 tCK should be added.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 202/300 Asynchronous ODTon/ODToff Timing Note: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 203/300 DQ ODT During Power-Down and Self Refresh Modes DQ bus ODT will be disabled in power-down mode. In self refresh mode, the ODT will be turned off when CKE is LOW but will be enabled if CKE is HIGH and DQ ODT is enabled in the mode register. ODT During Write Leveling Mode If ODT is enabled in MR11 OP[2:0] in write leveling mode, the device always provides the termination on DQS signals. DQ termination is always off in write leveling mode. Termination State in Write Leveling Mode ODT State in MR11 OP[2:0] DQS Termination DQ[15:0]/DMI[1:0] Termination Disabled Off Off Enabled On Off

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 204/300 Target Row Refresh Mode The device limits the number of times that a given row can be accessed within a refresh period (tREFW × 2) prior to requiring adjacent rows to be refreshed. The maximum activate count (MAC) is the maximum number of activates that a single row can sustain within a refresh period before the adjacent rows need to be refreshed. The row receiving the excessive actives is the target row (TRn), the adjacent rows to be refreshed are the victim rows. When the MAC limit is reached on TRn, either the device receives all (R × 2) REFRESH commands before another row activate is issued, or the device should be placed into targeted row refresh (TRR) mode. The TRR mode will refresh the rows adjacent to the TRn that encountered tMAC limit. If the device supports unlimited MAC value: MR24 OP[2:0] = 000 and MR24 OP[3] = 1, TARGET ROW REFRESH operation is not required. Even though the device allows to set MR24 OP[7] = 1: TRR mode enable, in this case the device behavior is vendor specific. For example, a certain device may ignore MRW command for entering/exiting TRR mode or a certain device may support commands related TRR mode. See vendor device data sheets for details about TRR mode definition at supporting unlimited MAC value case. There could be a maximum of two target rows to a victim row in a bank. The cumulative value of the activates from the two target rows on a victim row in a bank should not exceed MAC value. MR24 fields are required to support the new TRR settings. Setting MR24 OP[7] = 1 enables TRR mode and setting MR24 OP[7] = 0 disables TRR mode. MR24 OP[6:4] defines which bank (BAn) the target row is located in (refer to MR24 table for details). The TRR mode must be disabled during initialization as well as any other device calibration modes. The TRR mode is entered from a DRAM idle state, once TRR mode has been entered, no other mode register commands are allowed until TRR mode is completed; however, setting MR24 OP[7] = 0 to interrupt and reissue the TRR mode is allowed. When enabled, TRR mode is self -clearing. the mode will be disabled automatically after the completion of defined TRR flow (after the third BAn precharge has completed plus tMRD). Optionally, the TRR mode can also be exited via another MRS command at the completion of TRR by setting MR24 OP[7] = 0. If the TRR is exited via another MRS command, the value written to MR24 OP[6:4] are "Don’t Care." TRR Mode Operation 1. The timing diagram depicts TRR mode. The following steps must be performed when TRR mode is enabled. This mode requires all three ACT (ACT1, ACT2, and ACT3) and three corresponding PRE commands (PRE1, PRE2, and PRE3) to complete TRR mode. PRECHARGE All (PREA) commands issued while the device is in TRR mode will also perform precharge to BAn and counts towards PREn command. 2. Prior to issuing the MRW command to enter TRR mode, the device should be in the idle state. MRW command must be issued with MR24 OP[7] = 1 and MR24 OP[6:4] defining the bank in which the targeted row is located. All other MR24 bits should remain unchanged. 3. No activity is to occur with the device until tMRD has been satisfied. When tMRD has been satisfied, the only commands allowed BAn, until TRR mode has completed, are ACT and PRE. 4. The first ACT to the BAn with the TRn address can now be applied; no other command is allowed at this point. All other banks must remain inactive from when the first BAn ACT command is issued until [(1.5 x tRAS) + tRP] is satisfied. 5. After the first ACT to the BAn with the TRn address is issued, PRE to BAn is to be issued (1.5 × tRAS) later; and then followed tRP later by the second ACT to the BAn with the TRn address. 6. After the second ACT to the BAn with the TRn address is issued, PRE to BAn is to be issued tRAS later and then followed tRP later by the third ACT to the BAn with the TRn address. 7. After the third ACT to the BAn with the TRn address is issued, PRE to BAn would be issued tRAS later. TRR mode is completed once tRP plus tMRD is satisfied. 8. TRR mode must be completed as specified to guarantee that adjacent rows are refreshed. Anytime the TRR mode is interrupted and not completed, the interrupted TRR mode must be cleared and then su bsequently performed again. To clear an interrupted TRR mode, MR24 change is required with setting MR24 OP[7] = 0, MR24 OP[6:4] are "Don’t care," followed by three PRE to BAn, with tRP time in between each PRE command. The complete TRR sequence (steps 2 –7) must be then reissued and completed to guarantee that the adjacent rows are refreshed. 9. A REFRESH command to the device, or entering self refresh mode, is not allowed while the device is in TRR mode.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 205/300 Target Row Refresh Mode Note: 1. TRn is the targeted row. 2. Bank BAn represents the bank in which the targeted row is located. 3. TRR mode self-clears after tMRD + tRP measured from the third BAn precharge PRE3 at clock edge Th4. 4. TRR mode or any other activity can be re -engaged after tRP + tMRD from the third BAn precharge PRE3. PRE_ALL also counts if it is issued instead of PREn. TRR mode is cleared by the device after PRE3 to the BAn bank. 5. ACTIVATE commands to BAn during TRR mode do not provide refresh support (the refresh counter is unaffected). 6. The device must restore the degraded row(s) caused by excessive activation of the targeted row (TRn) necessary to meet refresh requirements. 7. A new TRR mode must wait tMRD + tRP time after the third precharge. 8. BAn may not be used with any other command. 9. ACT and PRE are the only allowed commands to BAn during TRR mode. 10. REFRESH commands are not allowed during TRR mode. 11. All timings are to be met by DRAM during TRR mode, such as tFAW. Issuing ACT1, ACT2, and ACT3 counts towards tFAW budget.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 206/300 Post-Package Repair The device has fail row address repair as an optional post -package repair (PPR) feature and it is readable through MR25 OP[7:0]. PPR provides simple and easy repair method in the system and fail row address can be repaired by the electrical programming of Electrical-fuse scheme. The device can correct one row per bank with PPR. Electrical-fuse cannot be switched back to un -fused states once it is programmed. The controller should prevent unintended PPR mode entry and repair. Failed Row Address Repair 1. Before entering PPR mode, all banks must be precharged. 2. Enable PPR using MR4 OP[4] = 1 and wait tMRD. 3. Issue ACT command with fail row address. 4. Wait tPGM to allow the device repair target row address internally then issue PRECHARGE 5. Wait tPGM_EXIT after PRECHARGE, which allows the device to recognize repaired row address RAn. 6. Exit PPR mode with setting MR4 OP[4] = 0. 7. The device is ready for any valid command after tPGMPST. 8. In more than one fail address repair case, repeat step 2 to 7. Once PPR mode is exited, to confirm whether the target row has correctly repaired, the host can verify the repair by writing data into the target row and reading it back after PPR exit with MR4 OP[4] = 0 and tPGMPST. The following timing diagram shows PPR operation.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 207/300 Post-Package Repair Timing Note: 1. During tPGM, any other commands (including refresh) are not allowed on each die. 2. With one PPR command, only one row can be repaired at one time per die. 3. When PPR procedure completes, reset procedure is required before normal operation. 4. During PPR, memory contents are not refreshed and may be lost. Post-Package Repair Timing Parameters Parameter Symbol Min Max Units PPR programming time tPGM 1000 – ms PPR exit time tPGM_EXIT 15 – ns New address setting time tPGMPST 50 – µs

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 208/300 Read Preamble Training Read preamble training is supported through the MPC function. This mode can be used to train or read level the DQS receivers. After read preamble training is enabled by MR13 OP[1] = 1, the device will drive DQS_t LOW and DQS_c HIGH within tSDO and remain at these levels until an MPC[READ DQ CALIBRATION] command is issued. During read preamble training, the DQS preamble provided during normal operation will not be driven by the de vice. After the MPC[READ DQ CALIBRATION] command is issued, the device will drive DQS_t/DQS_c and DQ like a normal READ burst after RL and tDQSCK. Prior to the MPC[READ DQ CALIBRATION] command, the device may or may not drive DQ[15:0] in this mode. While in read preamble training mode, only READ DQ CALIBRATION commands may be issued.  Issue an MPC[READ DQ CALIBRATION] command followed immediately by a CAS-2 command.  Each time an MPC[READ DQ CALIBRATION] command followed by a CAS -2 is received by the device, a 16-bit data burst will, after the currently set RL, drive the eight bits programmed in MR32 followed by the eight bits programmed in MR40 on all I/O pins.  The data pattern will be inverted for I/O pins with a 1 programmed in the corresponding invert mask mode register bit.  Note that the pattern is driven on the DMI pins, but no DATA BUS INVERSION function is enabled, even if read DBI is enabled in the DRAM mode register.  This command can be issued every tCCD seamlessly.  The operands received with the CAS-2 command must be driven LOW. Read preamble training is exited within tSDO after setting MR13 OP[1] = 0. Read Preamble Training Note: 1. Read DQ calibration supports only BL16 operation.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 209/300 Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed in the table below may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these conditions, or any other conditions outside those indicated in the operationa l sections of this document, is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Absolute Maximum DC Ratings Parameter Symbol Min Max Unit Note VDD1 supply voltage relative to VSS VDD1 –0.4 2.1 V 1 VDD2 supply voltage relative to VSS VDD2 –0.4 1.5 V 1 VDDQ supply voltage relative to VSS VDDQ –0.4 1.5 V 1 Voltage on any ball relative to VSS VIN, VOUT –0.4 1.5 V Storage temperature TSTG –55 125 ˚C 2 Note: 1. For information about relationships between power supplies, see the Voltage Ramp and Device Initialization section. 2. Storage temperature is the case surface temperature on the center/top side of the device. For measurement conditions, refer to the JESD51-2 standard.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 210/300 AC and DC Operating Conditions Operation or timing that is not specified is illegal. To ensure proper operation, the device must be initialized properly. Recommended DC Operating Conditions Symbol Min Typ Max DRAM Unit Note VDD1 1.7 1.8 1.95 Core 1 power V 1, 2 VDD2 1.06 1.1 1.17 Core 2 power/Input buffer power V 1, 2, 3 VDDQ 0.57 0.60 0.65 I/O buffer power V 2, 3 Note: 1. VDD1 uses significantly less power than VDD2. 2. The voltage range is for DC voltage only. DC voltage is the voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz at the DRAM package ball. 3. The voltage noise tolerance from DC to 20 MHz exceeding a peak -to-peak tolerance of 45mV at the DRAM ball is not included in the TdIVW. Input Leakage Current Parameter/Condition Symbol Min Max Unit Note Input leakage current IL -4 4 μA 1, 2 Note: 1. For CK_t, CK_c, CKE, CS, CA, ODT_CA and RESET_n. Any input 0V ≤ VIN ≤ VDD2. All other pins not under test = 0V. 2. CA ODT is disabled for CK_t, CK_c, CS, and CA. Input/Output Leakage Current Parameter/Condition Symbol Min Max Unit Note Input/Output leakage current IOZ -5 5 μA 1, 2 Note: 1. For DQ, DQS_t, DQS_c and DMI. Any I/O 0V ≤ VOUT ≤ VDDQ. 2. I/Os status are disabled: High impedance and ODT off.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 211/300 Operating Temperature Range Parameter/Condition Symbol Min Max Unit Standard TC -25 85 ˚C Note: 1. Operating temperature is the case surface temperature at the center of the top side of the device. For measurement conditions, refer to the JESD51-2 standard. 2. When using the device in the elevated temperature range, some derating may be required. See Mode Registers for vendor-specific derating. 3. Either the device case temperature rating or the temperature sensor can be used to set an appropriate refresh rate, determine the need for AC timing derating, and/or monitor the operating temperature (see Temperature Sensor). When using the temperature sen sor, the actual device case temperature may be higher than the TC rating that applies for the standard or elevated temperature range. For example, TC could be above +85˚C when the temperature sensor indicates a temperature of less than +85˚C.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 212/300 AC and DC Input Measurement Levels Input Levels for CKE Input Levels Parameter Symbol Min Max Unit Note Input HIGH level (AC) VIH(AC) 0.75 × VDD2 VDD2 + 0.2 V 1 Input LOW level (AC) VIL(AC) -0.2 0.25 × VDD2 V 1 Input HIGH level (DC) VIH(DC) 0.65 × VDD2 VDD2 + 0.2 V put LOW level (DC) VIL(DC) -0.2 0.35 × VDD2 V Note: 1. See the AC Overshoot and Undersection. Input Timing Definition for CKE Input Levels for RESET_n Input Levels Parameter Symbol Min Max Unit Note Input HIGH level VIH 0.80 × VDD2 VDD2 + 0.2 V 1 Input LOW level VIL -0.2 0.20 × VDD2 V 1 Note: 1. See the AC Overshoot and Undershoot section. Input Timing Definition for RESET_n

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 213/300 Differential Input Voltage for CK The minimum input voltage needs to satisfy both V indiff_CK and Vindiff_CK/2 specification at input receiver and their measurement period is 1 tCK. Vindiff_CK is the peak -to-peak voltage centered on 0 volts differential and V indiff_CK/2 is maximum and minimum peak voltage from 0 volts. CK Differential Input Voltage CK Differential Input Voltage Parameter Symbol 1600/1867 2133/2400/3200 3733 Unit Note Min Max Min Max Min Max CK differential input voltage Vindiff_CK 420 – 380 – 360 – mV 1 Note: 1. The peak voltage of differential CK signals is calculated in a following equation.  Vindiff_CK = (Maximum peak voltage) - (Minimum peak voltage)  Maximum peak voltage = MAX(f(t))  Minimum peak voltage = MIN(f(t))  f(t) = VCK_t - VCK_c

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 214/300 Peak Voltage Calculation Method The peak voltage of differential clock signals are calculated in a following equation.  VIH.DIFF.peak voltage = MAX(f(t))  VIL.DIFF.peak voltage = MIN(f(t))  f(t) = VCK_t - VCK_c Definition of Differential Clock Peak Voltage Note: 1. VREF(CA) is device internal setting value by VREF training.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 215/300 Single-Ended Input Voltage for Clock The minimum input voltage need to satisfy Vinse_CK, Vinse_CK_HIGH, and Vinse_CK_LOW specification at input receiver. Clock Single-Ended Input Voltage Note: 1. VREF(CA) is device internal setting value by VREF training. Clock Single-Ended Input Voltage Parameter Symbol 1600/1867 2133/2400/3200 3733 Unit Min Max Min Max Min Max Clock single-ended input voltage Vinse_CK 210 – 190 – 180 – mV Clock single-ended input voltage HIGH from VREF(CA) Vinse_CK_HIGH 105 – 95 – 90 – mV Clock single-ended input voltage LOW from VREF(CA) Vinse_CK_LOW 105 – 95 – 90 – mV

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 216/300 Differential Input Slew Rate Definition for Clock Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown below in figure and the tables. Differential Input Slew Rate Definition for CK_t, CK_c Note: 1. Differential signal rising edge from VILdiff_CK to VIHdiff_CK must be monotonic slope. 2. Differential signal falling edge from VIHdiff_CK to VILdiff_CK must be monotonic slope. Differential Input Slew Rate Definition for CK_t, CK_c Description From To Defined by Differential input slew rate for rising edge (CK_t - CK_c) VILdiff_CK VIHdiff_CK |VILdiff_CK - VIHdiff_CK|/ΔTRdiff Differential input slew rate for falling edge (CK_t - CK_c) VIHdiff_CK VILdiff_CK |VILdiff_CK - VIHdiff_CK|/ΔTFdiff Differential Input Level for CK_t, CK_c Parameter Symbol 1600/1867 2133/2400/3200 3733 Unit Min Max Min Max Min Max Differential Input HIGH VIHdiff_CK 175 – 155 – 145 – mV Differential Input LOW VILdiff_CK – –175 – –155 – –145 mV Differential Input Slew Rate for CK_t, CK_c Parameter Symbol 1600/1867 2133/2400/3200 3733 Unit Min Max Min Max Min Max Differential input slew rate for clock SRIdiff_CK 2 14 2 14 2 14 V/ns

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 217/300 Differential Input Cross-Point Voltage The cross-point voltage of differential input signals (CK_t, CK_c) must meet the requirements in table below. The differential input cross-point voltage V IX is measured from the actual cross -point of true and complement signals to the mid level that is VREF(CA). Vix Definition (Clock) Note: 1. The base levels of Vix_CK_FR and Vix_CK_RF are VREF(CA) that is device internal setting value by VREF training. Cross-Point Voltage for Differential Input Signals (Clock) Note 1 and 2 apply to entire table Parameter Symbol 1600/1867 2133/2400/3200 3733 Unit Min Max Min Max Min Max Clock single-ended cross-point voltage ratio Vix_CK_ratio – 25 – 25 – 25 % Note: 1. Vix_CK_ratio is defined by this equation: Vix_CK_ratio = Vix_CK_FR/|MIN(f(t))| 2. Vix_CK_ratio is defined by this equation: Vix_CK_ratio = Vix_CK_RF/MAX(f(t))

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 218/300 Differential Input Voltage for DQS The minimum input voltage needs to satisfy both Vindiff_DQS and Vindiff_DQS/2 specification at input receiver and their measurement period is 1UI ( tCK/2). Vindiff_DQS is the peak to peak voltage centered on 0 volts differential and V indiff_DQS/2 is maximum and minimum peak voltage from 0 volts. DQS Differential Input Voltage DQS Differential Input Voltage Parameter Symbol 1600/1867 2133/2400/3200 3733 Unit Note Min Max Min Max Min Max DQS differential input voltage Vindiff_DQS 360 – 360 – 340 – mV 1 Note: 1. The peak voltage of differential DQS signals is calculated in a following equation.  Vindiff_DQS = (Maximum peak voltage) - (Minimum peak voltage)  Maximum peak voltage = MAX(f(t))  Minimum peak voltage = MIN(f(t))  f(t) = VDQS_t - VDQS_c

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 219/300 Peak Voltage Calculation Method The peak voltage of differential DQS signals are calculated in a following equation.  VIH.DIFF.peak voltage = MAX(f(t))  VIL.DIFF.peak voltage = MIN(f(t))  f(t) = VDQS_t - VDQS_c Definition of Differential DQS Peak Voltage Note: 1. VREF(DQ) is device internal setting value by VREF training.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 220/300 Single-Ended Input Voltage for DQS The minimum input voltage need to satisfy Vinse_DQS, Vinse_DQS_HIGH, and Vinse_DQS_LOW specification at input receiver. DQS Single-Ended Input Voltage Note: 1. VREF(DQ) is device internal setting value by VREF training. DQS Single-Ended Input Voltage Parameter Symbol 1600/1867 2133/2400/3200 3733 Unit Min Max Min Max Min Max DQS single-ended input voltage Vinse_DQS 180 – 180 – 170 – mV DQS single-ended input voltage HIGH from VREF(DQ) Vinse_DQS_HIGH 90 – 90 – 85 – mV DQS single-ended input voltage LOW from VREF(DQ) Vinse_DQS_LOW 90 – 90 – 85 – mV

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 221/300 Differential Input Slew Rate Definition for DQS Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown below in figure and the tables. Differential Input Slew Rate Definition for DQS_t, DQS_c Note: 1. Differential signal rising edge from VILdiff_DQS to VIHdiff_DQS must be monotonic slope. 2. Differential signal falling edge from VIHdiff_DQS to VILdiff_DQS must be monotonic slope. Differential Input Slew Rate Definition for DQS_t, DQS_c Description From To Defined by Differential input slew rate for rising edge (DQS_t - DQS_c) VILdiff_DQS VIHdiff_DQS |VILdiff_DQS - VIHdiff_DQS|/ΔTRdiff Differential input slew rate for falling edge (DQS_t - DQS_c) VIHdiff_DQS VILdiff_DQS |VILdiff_DQS - VIHdiff_DQS|/ΔTFdiff Differential Input Level for DQS_t, DQS_c Parameter Symbol 1600/1867 2133/2400/3200 3733 Unit Min Max Min Max Min Max Differential Input HIGH VIHdiff_DQS 140 – 140 – 120 – mV Differential Input LOW VILdiff_DQS – –140 – –140 – –120 mV Differential Input Slew Rate for DQS_t, DQS_c Parameter Symbol 1600/1867 2133/2400/3200 3733 Unit Min Max Min Max Min Max Differential input slew rate SRIdiff 2 14 2 14 2 14 V/ns

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 222/300 Differential Input Cross-Point Voltage The cross-point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in table below. The differential input cross-point voltage V IX is measured from the actual cross -point of true and complement signals to the mid level that is VREF(DQ). Vix Definition (DQS) Note: 1. The base levels of Vix_DQS_FR and Vix_DQS_RF are VREF(DQ) that is device internal setting value by VREF training. Cross-Point Voltage for Differential Input Signals (DQS) Note 1 and 2 apply to entire table Parameter Symbol 1600/1867 2133/2400/3200 3733 Unit Min Max Min Max Min Max Clock single-ended cross-point voltage ratio Vix_DQS_ratio – 20 – 20 – 20 % Note: 1. Vix_DQS_ratio is defined by this equation: Vix_DQS_ratio = Vix_DQS_FR/|MIN(f(t))| 2. Vix_DQS_ratio is defined by this equation: Vix_DQS_ratio = Vix_DQS_RF/MAX(f(t)) Input Levels for ODT_CA Input Levels for ODT_CA Parameter Symbol Min Max Unit ODT input HIGH level VIHODT 0.75 × VDD2 VDD2 + 0.2 V ODT input LOW level VILODT –0.2 0.25 × VDD2 V

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 223/300 Output Slew Rate and Overshoot/Undershoot specifications Single-Ended Output Slew Rate Single-Ended Output Slew Rate Note 1-5 applies to entire table Parameter Symbol Value Units Min Max Single-ended output slew rate (VOH = VDDQ x 0.5) SRQse 3.0 9.0 V/ns Output slew rate matching ratio (rise to fall) – 0.8 1.2 – Note: 1. SR = Slew rate; Q = Query output; se = Single-ended signal. 2. Measured with output reference load. 3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 4. The output slew rate for falling and rising edges is defined and measured between V OL(AC) = 0.2 × V OH(DC) and VOH(AC) = 0.8 × VOH(DC). 5. Slew rates are measured under average SSO conditions with 50% of the DQ signals per data byte switching. Single-Ended Output Slew Rate Definition

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 224/300 Differential Output Slew Rate Differential Output Slew Rate Note 1-4 applies to entire table Parameter Symbol Value Units Min Max Differential output slew rate (VOH = VDDQ x 0.5) SRQdiff 6 18 V/ns Note: 1. SR = Slew rate; Q = Query output; se = Differential signal. 2. Measured with output reference load. 3. The output slew rate for falling and rising edges is defined and measured between V OL(AC) = –0.8 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC). 4. Slew rates are measured under average SSO conditions with 50% of the DQ signals per data byte switching. Differential Output Slew Rate Definition

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 225/300 Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specifications Parameter 1600 1866 3200 3733 Unit Maximum peak amplitude provided for overshoot area MAX 0.3 0.3 0.3 0.3 V Maximum peak amplitude provided for undershoot area MAX 0.3 0.3 0.3 0.3 V Maximum area above VDD/ VDDQ MAX 0.1 0.1 0.1 0.1 V-ns Maximum area below VSS/ VSSQ MAX 0.1 0.1 0.1 0.1 V-ns Note: 1. VDD stands for VDD2 for CA[5:0], CK_t, CS_n, CKE, and ODT. VDD stands for VDDQ for DQ, DMI, DQS_t, and DQS_c. 2. VSS stands for VSS for CA[5:0], CK_t, CK_c, CS_n, CKE, and ODT. VSS stands for VSSQ for DQ, DMI, DQS_t, and DQS_c. 3. Maximum peak amplitude values are referenced from actual VDD and VSS values. 4. Maximum area values are referenced from maximum VDD and VSS values. Overshoot/Undershoot Specification for CKE and RESET Parameter Specification Maximum peak amplitude provided for overshoot area 0.35V Maximum peak amplitude provided for undershoot area 0.35V Maximum area above VDD 0.8 V-ns Maximum area below VSS 0.8 V-ns Overshoot and Undershoot Definition

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 226/300 Driver Output Timing Reference Load Timing reference loads are not intended as a precise representation of any particular system environment or depiction of an actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufact urers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. Driver Output Timing Reference Load Note: 1. All output timing parameter values are reported with respect to this reference load; this reference load is also used to report slew rate.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 227/300 LVSTL I/O System LVSTL I/O cells are comprised of a driver pull-up and pull-down and a terminator. LVSTL I/O Cell To ensure that the target impedance is achieved, calibrate the LVSTL I/O cell as following example: 1. Calibrate the pull-down device against a 240 ohm resistor to VDDQ via the ZQ pin.  Set strength control to minimum setting  Increase drive strength until comparator detects data bit is less than VDDQ/2  NMOS pull-down device is calibrated to 240 ohms 2. Calibrate the pull-up device against the calibrated pull-down device.  Set VOH target and NMOS controller ODT replica via MRS (VOH can be automatically controlled by ODT MRS)  Set strength control to minimum setting  Increase drive strength until comparator detects data bit is greater than VOH target  NMOS pull-up device is calibrated to VOH target Pull-Up Calibration

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 228/300 Input/Output Capacitance Input/Output Capacitance Note 1 and 2 apply to entire table Parameter Symbol Min Max Unit Note Input capacitance, CK_t and CK_c CCK 0.5 0.9 pF Input capacitance delta, CK_t and CK_c CDCK 0 0.09 3 Input capacitance, all other input-only pins CI 0.5 0.9 4 Input capacitance delta, all other input-only pins CDI –0.1 0.1 5 Input/output capacitance, DQ, DMI, DQS_t, DQS_c CIO 0.7 1.3 6 Input/output capacitance delta, DQS_t, DQS_c CDDQS 0 0.1 7 Input/output capacitance delta, DQ, DMI CDIO –0.1 0.1 8 Input/output capacitance, ZQ pin CZQ 0 5.0 Note: 1. This parameter applies to LPDDR4 die only (does not include package capacitance). 2. This parameter is not subject to production testing; it is verified by design and character- ization. The capacitance is measured according to JEP147 (procedure for measuring input capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ, and VSS applied; all other pins are left floating. 3. Absolute value of CCK_t – CCK_c. 4. CI applies to CS, CKE, and CA[5:0]. 5. CDI = CI – 0.5 × (CCK_t + CCK_c); it does not apply to CKE. 6. DMI loading matches DQ and DQS. 7. Absolute value of CDQS_t and CDQS_c. 8. CDIO = CIO – 0.5 × (CDQS_t + CDQS_c) in byte-lane.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 229/300 IDD Specification Parameters and Test Conditions IDD Measurement Conditions Switching for CA CK_t edge R1 R2 R3 R4 R5 R6 R7 R8 CKE HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH CS LOW LOW LOW LOW LOW LOW LOW LOW CA0 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA1 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA2 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA3 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA4 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA5 HIGH HIGH HIGH LOW LOW LOW LOW HIGH Note: 1. LOW = VIN ≤ VIL(DC) MAX. HIGH = VIN ≥ VIH(DC) MIN. STABLE = Inputs are stable at a HIGH or LOW level. 2. CS must always be driven LOW. 3. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus. 4. The pattern is used continuously during IDD measurement for IDD values that require switching on the CA bus. CA Pattern for IDD4R for BL = 16 Clock Cycle Number CKE CS Command CA0 CA1 CA2 CA3 CA4 CA5 N HIGH HIGH READ-1 L H L L L L N+1 HIGH LOW L H L L L L N+2 HIGH HIGH CAS-2 L H L L H L N+3 HIGH LOW L L L L L L N+4 HIGH LOW DES L L L L L L N+5 HIGH LOW DES L L L L L L N+6 HIGH LOW DES L L L L L L N+7 HIGH LOW DES L L L L L L N+8 HIGH HIGH READ-1 L H L L L L N+9 HIGH LOW L H L L H L N+10 HIGH HIGH CAS-2 L H L L H H N+11 HIGH LOW H H H H H H N+12 HIGH LOW DES L L L L L L N+13 HIGH LOW DES L L L L L L N+14 HIGH LOW DES L L L L L L N+15 HIGH LOW DES L L L L L L Note: 1. BA[2:0] = 010; C[9:4] = 000000 or 111111; Burst order C[3:2] = 00 or 11 (same as LPDDR3 IDDR4R specification). 2. CA pins are kept LOW with DES command to reduce ODT current (different from LPDDR3 IDDR4R specification).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 230/300 CA Pattern for IDD4W for BL = 16 Clock Cycle Number CKE CS Command CA0 CA1 CA2 CA3 CA4 CA5 N HIGH HIGH WRITE-1 L L H L L L N+1 HIGH LOW L H L L L L N+2 HIGH HIGH CAS-2 L H L L H L N+3 HIGH LOW L L L L L L N+4 HIGH LOW DES L L L L L L N+5 HIGH LOW DES L L L L L L N+6 HIGH LOW DES L L L L L L N+7 HIGH LOW DES L L L L L L N+8 HIGH HIGH WRITE-1 L L H L L L N+9 HIGH LOW L H L L H L N+10 HIGH HIGH CAS-2 L H L L H H N+11 HIGH LOW L L H H H H N+12 HIGH LOW DES L L L L L L N+13 HIGH LOW DES L L L L L L N+14 HIGH LOW DES L L L L L L N+15 HIGH LOW DES L L L L L L Note: 1. BA[2:0] = 010; C[9:4] = 000000 or 111111 (same as LPDDR3 IDDR4W specification). 2. No burst ordering (different from LPDDR3 IDDR4W specification). 3. CA pins are kept LOW with DES command to reduce ODT current (different from LPDDR3 IDDR4W specification).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 231/300 Data Pattern for IDD4W (DBI Off) for BL = 16 DBI Off Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL0 1 1 1 1 1 1 1 1 0 8 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 1 1 1 1 1 1 0 0 0 6 BL7 1 1 1 1 0 0 0 0 0 4 BL8 1 1 1 1 1 1 1 1 0 8 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 1 1 1 1 1 1 0 0 0 6 BL15 1 1 1 1 0 0 0 0 0 4 BL16 1 1 1 1 1 1 0 0 0 6 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 1 1 0 2 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 1 1 1 1 1 1 1 1 0 8 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 1 1 1 1 1 1 0 0 0 6 BL27 1 1 1 1 0 0 0 0 0 4 BL28 1 1 1 1 1 1 1 1 0 8 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 # of 1s 16 16 16 16 16 16 16 16 Note: 1. Simplified pattern; same data pattern was applied to DQ[4], DQ[5], DQ[6], and DQ[7] to reduce complexity for I DD4W pattern programming.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 232/300 Data Pattern for IDD4R (DBI Off) for BL = 16 DBI Off Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL0 1 1 1 1 1 1 1 1 0 8 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 1 1 1 1 1 1 0 0 0 6 BL7 1 1 1 1 0 0 0 0 0 4 BL8 1 1 1 1 1 1 1 1 0 8 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 1 1 1 1 1 1 0 0 0 6 BL15 1 1 1 1 0 0 0 0 0 4 BL16 1 1 1 1 1 1 1 1 0 8 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 0 0 0 0 BL19 0 0 0 0 1 1 1 1 0 4 BL20 1 1 1 1 1 1 0 0 0 6 BL21 1 1 1 1 0 0 0 0 0 4 BL22 0 0 0 0 0 0 1 1 0 2 BL23 0 0 0 0 1 1 1 1 0 4 BL24 0 0 0 0 0 0 0 0 0 0 BL25 0 0 0 0 1 1 1 1 0 4 BL26 1 1 1 1 1 1 1 1 0 8 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 1 1 0 2 BL29 0 0 0 0 1 1 1 1 0 4 BL30 1 1 1 1 1 1 0 0 0 6 BL31 1 1 1 1 0 0 0 0 0 4 # of 1s 16 16 16 16 16 16 16 16 Note: 1. Simplified pattern; same data pattern was applied to DQ[4], DQ[5], DQ[6], and DQ[7] to reduce complexity for I DD4R pattern programming.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 233/300 Data Pattern for IDD4W (DBI On) for BL = 16 DBI On Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL0 0 0 0 0 0 0 0 0 1 1 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 0 0 0 0 0 0 1 1 1 3 BL7 1 1 1 1 0 0 0 0 0 4 BL8 0 0 0 0 0 0 0 0 1 1 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 0 0 0 0 0 0 1 1 1 3 BL15 1 1 1 1 0 0 0 0 0 4 BL16 0 0 0 0 0 0 1 1 1 3 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 1 1 0 2 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 0 0 0 0 0 0 0 0 1 1 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 0 0 0 0 0 0 1 1 1 3 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 0 0 1 1 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 # of 1s 8 8 8 8 8 8 16 16 8 Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL16, BL22, BL26, and BL28.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 234/300 Data Pattern for IDD4R (DBI On) for BL = 16 DBI On Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL0 0 0 0 0 0 0 0 0 1 1 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 0 0 0 0 0 0 1 1 1 3 BL7 1 1 1 1 0 0 0 0 0 4 BL8 0 0 0 0 0 0 0 0 1 1 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 0 0 0 0 0 0 1 1 1 3 BL15 1 1 1 1 0 0 0 0 0 4 BL16 0 0 0 0 0 0 0 0 1 1 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 0 0 0 0 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 1 1 1 3 BL21 1 1 1 1 0 0 0 0 0 4 BL22 0 0 0 0 0 0 1 1 0 2 BL23 0 0 0 0 1 1 1 1 0 4 BL24 0 0 0 0 0 0 0 0 0 0 BL25 0 0 0 0 1 1 1 1 0 4 BL26 0 0 0 0 0 0 0 0 1 1 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 1 1 0 2 BL29 0 0 0 0 1 1 1 1 0 4 BL30 0 0 0 0 0 0 1 1 1 3 BL31 1 1 1 1 0 0 0 0 0 4 # of 1s 8 8 8 8 8 8 16 16 8 Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL20, BL26, and BL30.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 235/300 CA Pattern for IDD4R for BL = 32 Clock Cycle Number CKE CS Command CA0 CA1 CA2 CA3 CA4 CA5 N HIGH HIGH READ-1 L H L L L L N+1 HIGH LOW L H L L L L N+2 HIGH HIGH CAS-2 L H L L H L N+3 HIGH LOW L L L L L L N+4 HIGH LOW DES L L L L L L N+5 HIGH LOW DES L L L L L L N+6 HIGH LOW DES L L L L L L N+7 HIGH LOW DES L L L L L L N+8 HIGH LOW DES L L L L L L N+9 HIGH LOW DES L L L L L L N+10 HIGH LOW DES L L L L L L N+11 HIGH LOW DES L L L L L L N+12 HIGH LOW DES L L L L L L N+13 HIGH LOW DES L L L L L L N+14 HIGH LOW DES L L L L L L N+15 HIGH LOW DES L L L L L L N+16 HIGH HIGH READ-1 L H L L L L N+17 HIGH LOW L H L L H L N+18 HIGH HIGH CAS-2 L H L L H H N+19 HIGH LOW H H L H H H N+20 HIGH LOW DES L L L L L L N+21 HIGH LOW DES L L L L L L N+22 HIGH LOW DES L L L L L L N+23 HIGH LOW DES L L L L L L N+24 HIGH LOW DES L L L L L L N+25 HIGH LOW DES L L L L L L N+26 HIGH LOW DES L L L L L L N+27 HIGH LOW DES L L L L L L N+28 HIGH LOW DES L L L L L L N+29 HIGH LOW DES L L L L L L N+30 HIGH LOW DES L L L L L L N+31 HIGH LOW DES L L L L L L Note: 1. BA[2:0] = 010, C[9:5] = 00000 or 11111, Burst order C[4:2] = 000 or 111.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 236/300 CA Pattern for IDD4W for BL = 32 Clock Cycle Number CKE CS Command CA0 CA1 CA2 CA3 CA4 CA5 N HIGH HIGH WRITE-1 L L H L L L N+1 HIGH LOW L H L L L L N+2 HIGH HIGH CAS-2 L H L L H L N+3 HIGH LOW L L L L L L N+4 HIGH LOW DES L L L L L L N+5 HIGH LOW DES L L L L L L N+6 HIGH LOW DES L L L L L L N+7 HIGH LOW DES L L L L L L N+8 HIGH LOW DES L L L L L L N+9 HIGH LOW DES L L L L L L N+10 HIGH LOW DES L L L L L L N+11 HIGH LOW DES L L L L L L N+12 HIGH LOW DES L L L L L L N+13 HIGH LOW DES L L L L L L N+14 HIGH LOW DES L L L L L L N+15 HIGH LOW DES L L L L L L N+16 HIGH HIGH WRITE-1 L L H L L L N+17 HIGH LOW L H L L H L N+18 HIGH HIGH CAS-2 L H L L H H N+19 HIGH LOW L L L H H H N+20 HIGH LOW DES L L L L L L N+21 HIGH LOW DES L L L L L L N+22 HIGH LOW DES L L L L L L N+23 HIGH LOW DES L L L L L L N+24 HIGH LOW DES L L L L L L N+25 HIGH LOW DES L L L L L L N+26 HIGH LOW DES L L L L L L N+27 HIGH LOW DES L L L L L L N+28 HIGH LOW DES L L L L L L N+29 HIGH LOW DES L L L L L L N+30 HIGH LOW DES L L L L L L N+31 HIGH LOW DES L L L L L L Note:

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 237/300 Data Pattern for IDD4W (DBI Off) for BL = 32 DBI Off Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL0 1 1 1 1 1 1 1 1 0 8 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 1 1 1 1 1 1 0 0 0 6 BL7 1 1 1 1 0 0 0 0 0 4 BL8 1 1 1 1 1 1 1 1 0 8 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 1 1 1 1 1 1 0 0 0 6 BL15 1 1 1 1 0 0 0 0 0 4 BL16 1 1 1 1 1 1 0 0 0 6 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 1 1 0 2 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 1 1 1 1 1 1 1 1 0 8 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 1 1 1 1 1 1 0 0 0 6 BL27 1 1 1 1 0 0 0 0 0 4 BL28 1 1 1 1 1 1 1 1 0 8 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 BL32 1 1 1 1 1 1 1 1 0 8 BL33 1 1 1 1 0 0 0 0 0 4 BL34 0 0 0 0 0 0 0 0 0 0 BL35 0 0 0 0 1 1 1 1 0 4 BL36 0 0 0 0 0 0 1 1 0 2

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 238/300 Data Pattern for IDD4W (DBI Off) for BL = 32 (Continued) DBI Off Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL37 0 0 0 0 1 1 1 1 0 4 BL38 1 1 1 1 1 1 0 0 0 6 BL39 1 1 1 1 0 0 0 0 0 4 BL40 1 1 1 1 1 1 1 1 0 8 BL41 1 1 1 1 0 0 0 0 0 4 BL42 0 0 0 0 0 0 0 0 0 0 BL43 0 0 0 0 1 1 1 1 0 4 BL44 0 0 0 0 0 0 1 1 0 2 BL45 0 0 0 0 1 1 1 1 0 4 BL46 1 1 1 1 1 1 0 0 0 6 BL47 1 1 1 1 0 0 0 0 0 4 BL48 1 1 1 1 1 1 0 0 0 6 BL49 1 1 1 1 0 0 0 0 0 4 BL50 0 0 0 0 0 0 1 1 0 2 BL51 0 0 0 0 1 1 1 1 0 4 BL52 0 0 0 0 0 0 0 0 0 0 BL53 0 0 0 0 1 1 1 1 0 4 BL54 1 1 1 1 1 1 1 1 0 8 BL55 1 1 1 1 0 0 0 0 0 4 BL56 0 0 0 0 0 0 1 1 0 2 BL57 0 0 0 0 1 1 1 1 0 4 BL58 1 1 1 1 1 1 0 0 0 6 BL59 1 1 1 1 0 0 0 0 0 4 BL60 1 1 1 1 1 1 1 1 0 8 BL61 1 1 1 1 0 0 0 0 0 4 BL62 0 0 0 0 0 0 0 0 0 0 BL63 0 0 0 0 1 1 1 1 0 4 # of 1s 32 32 32 32 32 32 32 32 Note: 1. Simplified pattern; same data pattern was applied to DQ[4], DQ[5], DQ[6], and DQ[7] to reduce complexity for I DD4W pattern programming.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 239/300 Data Pattern for IDD4R (DBI Off) for BL = 32 DBI Off Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL0 1 1 1 1 1 1 1 1 0 8 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 1 1 1 1 1 1 0 0 0 6 BL7 1 1 1 1 0 0 0 0 0 4 BL8 1 1 1 1 1 1 1 1 0 8 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 1 1 1 1 1 1 0 0 0 6 BL15 1 1 1 1 0 0 0 0 0 4 BL16 1 1 1 1 1 1 0 0 0 6 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 1 1 0 2 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 1 1 1 1 1 1 1 1 0 8 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 1 1 1 1 1 1 0 0 0 6 BL27 1 1 1 1 0 0 0 0 0 4 BL28 1 1 1 1 1 1 1 1 0 8 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 BL32 0 0 0 0 0 0 1 1 0 2 BL33 0 0 0 0 1 1 1 1 0 4 BL34 1 1 1 1 1 1 0 0 0 6 BL35 1 1 1 1 0 0 0 0 0 4 BL36 1 1 1 1 1 1 1 1 0 8 BL37 1 1 1 1 0 0 0 0 0 4 BL38 0 0 0 0 0 0 0 0 0 0

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 240/300 Data Pattern for IDD4R (DBI Off) for BL = 32 (Continued) DBI Off Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL39 0 0 0 0 1 1 1 1 0 4 BL40 0 0 0 0 0 0 1 1 0 2 BL41 0 0 0 0 1 1 1 1 0 4 BL42 1 1 1 1 1 1 0 0 0 6 BL43 1 1 1 1 0 0 0 0 0 4 BL44 1 1 1 1 1 1 1 1 0 8 BL45 1 1 1 1 0 0 0 0 0 4 BL46 0 0 0 0 0 0 0 0 0 0 BL47 0 0 0 0 1 1 1 1 0 4 BL48 1 1 1 1 1 1 1 1 0 8 BL49 1 1 1 1 0 0 0 0 0 4 BL50 0 0 0 0 0 0 0 0 0 0 BL51 0 0 0 0 1 1 1 1 0 4 BL52 1 1 1 1 1 1 0 0 0 6 BL53 1 1 1 1 0 0 0 0 0 4 BL54 0 0 0 0 0 0 1 1 0 2 BL55 0 0 0 0 1 1 1 1 0 4 BL56 0 0 0 0 0 0 0 0 0 0 BL57 0 0 0 0 1 1 1 1 0 4 BL58 1 1 1 1 1 1 1 1 0 8 BL59 1 1 1 1 0 0 0 0 0 4 BL60 0 0 0 0 0 0 1 1 0 2 BL61 0 0 0 0 1 1 1 1 0 4 BL62 1 1 1 1 1 1 0 0 0 6 BL63 1 1 1 1 0 0 0 0 0 4 # of 1s 32 32 32 32 32 32 32 32 Note: 1. Simplified pattern; same data pattern was applied to DQ[4], DQ[5], DQ[6], and DQ[7] to reduce complexity for I DD4R pattern programming.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 241/300 Data Pattern for IDD4W (DBI On) for BL = 32 DBI On Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL0 0 0 0 0 0 0 0 0 1 1 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 0 0 0 0 0 0 1 1 1 3 BL7 1 1 1 1 0 0 0 0 0 4 BL8 0 0 0 0 0 0 0 0 1 1 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 0 0 0 0 0 0 1 1 1 3 BL15 1 1 1 1 0 0 0 0 0 4 BL16 0 0 0 0 0 0 1 1 1 3 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 1 1 0 2 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 0 0 0 0 0 0 0 0 1 1 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 0 0 0 0 0 0 1 1 1 3 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 0 0 1 1 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 BL32 0 0 0 0 0 0 0 0 1 1 BL33 1 1 1 1 0 0 0 0 0 4 BL34 0 0 0 0 0 0 0 0 0 0 BL35 0 0 0 0 1 1 1 1 0 4 BL36 0 0 0 0 0 0 1 1 0 2 BL37 0 0 0 0 1 1 1 1 0 4 BL38 0 0 0 0 0 0 1 1 1 3 BL39 1 1 1 1 0 0 0 0 0 4

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 242/300 Data Pattern for IDD4W (DBI On) for BL = 32 (Continued) DBI On Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL40 0 0 0 0 0 0 0 0 1 1 BL41 1 1 1 1 0 0 0 0 0 4 BL42 0 0 0 0 0 0 0 0 0 0 BL43 0 0 0 0 1 1 1 1 0 4 BL44 0 0 0 0 0 0 1 1 0 2 BL45 0 0 0 0 1 1 1 1 0 4 BL46 0 0 0 0 0 0 1 1 1 3 BL47 1 1 1 1 0 0 0 0 0 4 BL48 0 0 0 0 0 0 1 1 1 3 BL49 1 1 1 1 0 0 0 0 0 4 BL50 0 0 0 0 0 0 1 1 0 2 BL51 0 0 0 0 1 1 1 1 0 4 BL52 0 0 0 0 0 0 0 0 0 0 BL53 0 0 0 0 1 1 1 1 0 4 BL54 0 0 0 0 0 0 0 0 1 1 BL55 1 1 1 1 0 0 0 0 0 4 BL56 0 0 0 0 0 0 1 1 0 2 BL57 0 0 0 0 1 1 1 1 0 4 BL58 0 0 0 0 0 0 1 1 1 3 BL59 1 1 1 1 0 0 0 0 0 4 BL60 0 0 0 0 0 0 0 0 1 1 BL61 1 1 1 1 0 0 0 0 0 4 BL62 0 0 0 0 0 0 0 0 0 0 BL63 0 0 0 0 1 1 1 1 0 4 # of 1s 16 16 16 16 16 16 32 32 16 Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL16, BL22, BL26, BL28, BL32, BL38, BL40, BL46, BL48, BL54, BL58, and BL60.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 243/300 Data Pattern for IDD4R (DBI On) for BL = 32 DBI On Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL0 0 0 0 0 0 0 0 0 1 1 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 0 0 0 0 0 0 1 1 1 3 BL7 1 1 1 1 0 0 0 0 0 4 BL8 0 0 0 0 0 0 0 0 1 1 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 0 0 0 0 0 0 1 1 1 3 BL15 1 1 1 1 0 0 0 0 0 4 BL16 0 0 0 0 0 0 1 1 1 3 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 1 1 0 2 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 0 0 0 0 0 0 0 0 1 1 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 0 0 0 0 0 0 1 1 1 3 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 0 0 1 1 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 BL32 0 0 0 0 0 0 1 1 0 2 BL33 0 0 0 0 1 1 1 1 0 4 BL34 0 0 0 0 0 0 1 1 1 3 BL35 1 1 1 1 0 0 0 0 0 4 BL36 0 0 0 0 0 0 0 0 1 1 BL37 1 1 1 1 0 0 0 0 0 4 BL38 0 0 0 0 0 0 0 0 0 0 BL39 0 0 0 0 1 1 1 1 0 4 BL40 0 0 0 0 0 0 1 1 0 2

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 244/300 Data Pattern for IDD4R (DBI On) for BL = 32 (Continued) DBI On Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL41 0 0 0 0 1 1 1 1 0 4 BL42 0 0 0 0 0 0 1 1 1 3 BL43 1 1 1 1 0 0 0 0 0 4 BL44 0 0 0 0 0 0 0 0 1 1 BL45 1 1 1 1 0 0 0 0 0 4 BL46 0 0 0 0 0 0 0 0 0 0 BL47 0 0 0 0 1 1 1 1 0 4 BL48 0 0 0 0 0 0 0 0 1 1 BL49 1 1 1 1 0 0 0 0 0 4 BL50 0 0 0 0 0 0 0 0 0 0 BL51 0 0 0 0 1 1 1 1 0 4 BL52 0 0 0 0 0 0 1 1 1 3 BL53 1 1 1 1 0 0 0 0 0 4 BL54 0 0 0 0 0 0 1 1 0 2 BL55 0 0 0 0 1 1 1 1 0 4 BL56 0 0 0 0 0 0 0 0 0 0 BL57 0 0 0 0 1 1 1 1 0 4 BL58 0 0 0 0 0 0 0 0 1 1 BL59 1 1 1 1 0 0 0 0 0 4 BL60 0 0 0 0 0 0 1 1 0 2 BL61 0 0 0 0 1 1 1 1 0 4 BL62 0 0 0 0 0 0 1 1 1 3 BL63 1 1 1 1 0 0 0 0 0 4 # of 1s 16 16 16 16 16 16 32 32 16 Note: 1. DBI enabled burst: BL0, BL6, BL8, BL14, BL16, BL22, BL26, BL28, BL34, BL36, BL42, BL44, BL48, BL52, BL58, and BL62.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 245/300 IDD Specifications IDD values are for the entire operating voltage range, and all of them are for the entire standard temperature range. IDD Specification Parameters and Operating Conditions LPDDR4: VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V Parameter/Condition Symbol Power Supply Note Operating one bank active-precharge current: tCK = tCK (MIN); tRC = tRC (MIN); CKE is HIGH; CS is LOW between valid commands; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled IDD01 VDD1 IDD02 VDD2 IDD0Q VDDQ 2 Idle power-down standby current: tCK = tCK (MIN); CKE is LOW; CS is LOW; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled IDD2P1 VDD1 IDD2P2 VDD2 IDD2PQ VDDQ 2 Idle power-down standby current with clock stop: CK_t = LOW, CK_c = HIGH; CKE is LOW; CS is LOW; All banks are idle; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled IDD2PS1 VDD1 IDD2PS2 VDD2 IDD2PSQ VDDQ 2 Idle non-power-down standby current: tCK = tCK (MIN); CKE is HIGH; CS is LOW; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled IDD2N1 VDD1 IDD2N2 VDD2 IDD2NQ VDDQ 2 Idle non-power-down standby current with clock stopped: CK_t = LOW; CK_c = HIGH; CKE is HIGH; CS is LOW; All banks are idle; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled IDD2NS1 VDD1 IDD2NS2 VDD2 IDD2NSQ VDDQ 2 Active power-down standby current: tCK = tCK (MIN); CKE is LOW; CS is LOW; One bank is active; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled IDD3P1 VDD1 IDD3P2 VDD2 IDD3PQ VDDQ 2 Active power-down standby current with clock stop: CK_t = LOW, CK_c = HIGH; CKE is LOW; CS is LOW; One bank is active; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled IDD3PS1 VDD1 IDD3PS2 VDD2 IDD3PSQ VDDQ 3 Active non-power-down standby current: tCK = tCK (MIN); CKE is HIGH; CS is LOW; One bank is active; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled IDD3N1 VDD1 IDD3N2 VDD2 IDD3NQ VDDQ 3 Active non-power-down standby current with clock stopped: CK_t = LOW, CK_c = HIGH; CKE is HIGH; CS is LOW; One bank is active; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled IDD3NS1 VDD1 IDD3NS2 VDD2 IDD3NSQ VDDQ 3 Operating burst READ current: tCK = tCK (MIN); CS is LOW between valid commands; One bank is active; BL = 16 or 32; RL = RL (MIN); CA bus inputs are switching; 50% data change each burst transfer; ODT is disabled IDD4R1 VDD1 IDD4R2 VDD2 IDD4RQ VDDQ 4

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 246/300 IDD Specification Parameters and Operating Conditions (Continued) LPDDR4: VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V Parameter/Condition Symbol Power Supply Note Operating burst WRITE current: tCK = tCK (MIN); CS is LOW between valid commands; One bank is active; BL = 16 or 32; WL = WL (MIN); CA bus inputs are switching; 50% data change each burst transfer; ODT is disabled IDD4W1 VDD1 IDD4W2 VDD2 IDD4WQ VDDQ 3 All-bank REFRESH burst current: tCK = tCK (MIN); CKE is HIGH between valid commands; tRC = tRFCab (MIN); Burst refresh; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled IDD51 VDD1 IDD52 VDD2 IDD5Q VDDQ 3 All-bank REFRESH average current: tCK = tCK (MIN); CKE is HIGH between valid commands; tRC = tREFI; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled IDD5AB1 VDD1 IDD5AB2 VDD2 IDD5ABQ VDDQ 3 Per-bank REFRESH average current: tCK = tCK (MIN); CKE is HIGH between valid commands; tRC = tREFI/8; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled IDD5PB1 VDD1 IDD5PB2 VDD2 IDD5PBQ VDDQ 3 Power-down self refresh current: CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are stable; Maximum 1x self refresh rate; ODT is disabled IDD61 VDD1 5, 6 IDD62 VDD2 5, 6 IDD6Q VDDQ 3, 5, 6 Note: 1. ODT disabled: MR11[2:0] = 000b. 2. IDD current specifications are tested after the device is properly initialized. 3. Measured currents are the summation of VDDQ and VDD2. 4. Guaranteed by design with output load = 5pF and RON = 40 ohm. 5. The 1x self refresh rate is the rate at which the device is refreshed internally during self refresh before going i nto the elevated temperature range. 6. This is the general definition that applies to full-array self refresh. 7. For all IDD measurements, VIHCKE = 0.8 × VDD2; VILCKE = 0.2 × VDD2.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 247/300 AC Timing Clock Timing Parameter Symbol Min/ Max Data Rate Unit 1600 3200 3733 Average clock period tCK(AVG) Min 1250 625 535 ps Max 100 100 100 ns Average HIGH pulse width tCH(AVG) Min 0.46 tCK(AVG) Max 0.54 Average LOW pulse width tCL(AVG) Min 0.46 tCK(AVG) Max 0.54 Absolute clock period tCK(ABS) Min tCK(AVG)min + tJIT(per)min ps Absolute clock HIGH pulse width tCH(ABS) Min 0.43 tCK(AVG) Max 0.57 Absolute clock LOW pulse width tCL(ABS) Min 0.43 tCK(AVG) Max 0.57 Clock period jitter tJIT(per)al- lowed Min -70 -40 -34 ps Max 70 40 34 Maximum clock jitter between two consecutive clock cycles (includes clock period jitter) tJIT(cc)allowed Max 140 80 68 ps

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 248/300 Read Output Timing Parameter Symbol Min/ Max Data Rate Unit Note 533 1066 1600 2133 2667 3200 3733 DQS output access time from CK_t/CK_c tDQSCK Min 1500 ps 1 Max 3500 DQS output access time from CK_t/CK_c - voltage variation tDQSCK_ VOLT Max 7 ps/mV 2 DQS output access time from CK_t/CK_c - temperature variation tDQSCK_ TEMP Max 4 ps/°C 3 CK to DQS rank to rank variation tDQSCK_r ank2rank Max 1.0 ns 4, 5 DQS_t, DQS_c to DQ skew total, per group, per access (DBI Disabled) tDQSQ Max 0.18 UI 6 DQ output hold time to- tal from DQS_t, DQS_c (DBI Disabled) tQH Min MIN(tQSH, tQSL) ps 6 Data output valid win- dow time total, per pin (DBI-Disabled) tQW_total Min 0.75 0.73 0.70 UI 6, 11 DQS_t, DQS_c to DQ skew total, per group, per access (DBI-Enabled) tDQSQ_DBI Max 0.18 UI 6 DQ output hold time total from DQS_t, DQS_c (DBI-Enabled) tQH_DBI Min MIN(tQSH_DBI, tQSL_DBI) ps 6 Data output valid window time total, per pin (DBI-Enabled) tQW_total_ DBI Min 0.75 0.73 0.70 UI 6, 11 DQS_t, DQS_c differential output LOW time (DBI- Disabled) tQSL Min tCL(ABS) - 0.05 tCK (AVG) 9, 11 DQS_t, DQS_c differential output HIGH time (DBI- Disabled) tQSH Min tCH(ABS) - 0.05 tCK (AVG) 10, 11 DQS_t, DQS_c differential output LOW time (DBI- Enabled) tQSL-DBI Min tCL(ABS) - 0.045 tCK (AVG) 9, 11 DQS_t, DQS_c differential output HIGH time (DBI- Enabled) tQSH-DBI Min tCH(ABS) - 0.045 tCK (AVG) 10, 11 Read preamble tRPRE Min 1.8 tCK (AVG) Read postamble tRPST Min 0.4 (or 1.4 if extra postamble is programmed in MR) tCK (AVG)

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 249/300 Read Output Timing (Continued) Parameter Symbol Min/ Max Data Rate Unit Note 533 1066 1600 2133 2667 3200 3733 DQS Low-Z from clock tLZ(DQS) Min (RL × tCK) + tDQSCK(MIN) - (tRPRE(MAX) × tCK) - 200ps ps DQ Low-Z from clock tLZ(DQ) Min (RL × tCK) + tDQSCK(MIN) - 200ps ps DQS High-Z from clock tHZ(DQS) Min (RL × tCK) + tDQSCK(MAX)+(BL/2 × tCK) + (tRPST(MAX) × tCK) - 100ps ps DQ High-Z from clock tHZ(DQ) Min (RL × tCK) + tDQSCK(MAX) + tDQSQ(MAX) + (BL/2 × tCK) - 100ps ps Note: 1. This parameter includes DRAM process, voltage, and temperature variation. It also includes the AC noise impact for frequencies >20 MHz and a max voltage of 45mV peak-to-peak from DC-20 MHz at a fixed temperature on the package. The voltage supply noise must comply with the component MIN/MAX DC operating conditions. 2. tDQSCK_volt max delay variation as a function of DC voltage variation for VDDQ and VDD2. The voltage supply noise must comply with the component MIN/MAX DC operating conditions. The voltage variation is defined as the MAX[ABS(tDQSCK(MIN)@V1 - tDQSCK(MAX)@V2), ABS(tDQSCK(MAX)@V1 - tDQSCK(MIN)@V2)]/ABS(V1 - V2). 3. tDQSCK_temp MAX delay variation as a function of temperature. 4. The same voltage and temperature are applied to tDQSCK_rank2rank. tDQSCK_rank2rank parameter is applied to multi-ranks per byte lane within a package consisting of the same design die. 5. DQ-to-DQS differential jitter where the total includes the sum of deterministic and random timing terms for a specified BER. 6. The deterministic component of the total timing. 7. This parameter will be characterized and guaranteed by design. 8. tQSL describes the ins tantaneous differential output low pulse width on DQS_t - DQS_c, as measured from one falling edge to the next consecutive rising edge. 9. tQSH describes the instantaneous differential output high pulse width on DQS_t - DQS_c, as measured from one falling edge to the next consecutive rising edge. 10. This parameter is a function of input clock jitter. These values assume MIN tCH(ABS) and tCL(ABS). When the input clock jitter MIN tCH(ABS) and tCL(ABS) is 0.44 or greater than tCK(AVG), the minimum value of tQSL will be tCL(ABS) - 0.04 and tQSH will be tCH(ABS) - 0.04.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 250/300 Write Timing Note UI = tCK(AVG)(MIN)/2 Parameter Symbol Min/ Max Data Rate Unit Note 533 1066 1600 2133 2667 3200 3733 Rx timing window total at VdIVW voltage levels TdIVW_ total Max 0.22 0.25 UI 1, 2, 3 DQ and DMI input pulse width (at VCENT_DQ) TdIPW Min 0.45 UI 7 DQ-to-DQS offset tDQS2DQ Min 200 ps 6 Max 800 DQ-to-DQ offset tDQDQ Max 30 ps 7 DQ-to-DQS offset temper- ature variation tDQS2DQ _temp Max 0.6 ps/°C 8 DQ-to-DQS offset voltage variation tDQS2DQ _volt Max 33 ps/50mV 9 DQ-to-DQS offset rank to rank variation tDQS2DQ _rank2ra nk Max 200 ps 10, 11 WRITE command to first DQS transition tDQSS Min 0.75 tCK(AVG) Max 1.25 DQS input HIGH-level width tDQSH Min 0.4 tCK(AVG) DQS input LOW-level width tDQSL Min 0.4 tCK(AVG) DQS falling edge to CK setup time tDSS Min 0.2 tCK(AVG) DQS falling edge from CK hold time tDSH Min 0.2 tCK(AVG) Write postamble tWPST Min 0.4 (or 1.4 if extra postamble is programmed in MR) tCK(AVG) Write preamble tWPRE Min 1.8 tCK(AVG) Note: 1. Data Rx mask voltage and timing parameters are applied per pin and include the DRAM DQ -to-DQS voltage AC noise impact for frequencies >20 MHz with a maximum voltage of 45mV peak -to-peak at a fixed temperature on the package. The voltage supply noise must comply to the component MIN/MAX DC operating conditions. 2. Rx differential DQ-to-DQS jitter total timing window at the VdIVW voltage levels. 3. Defined over the DQ internal VREF range. The Rx mask at the pin must be within the internal VREF(DQ) range irrespective of the input signal common mode. 4. Rx mask defined for one pin toggling with other DQ signals in a steady state. 5. DQ-only minimum input pulse width defined at the VCENT_DQ(pin_mid). 6. DQ-to-DQS offset is within byte from DRAM pin to DRAM internal latch. Includes all DRAM process, voltage, and temperature variations. 7. DQ-to-DQ offset defined within byte from DRAM pin to DRAM internal latch for a given component. 8. tDQS2DQ(MAX) delay variation as a function of temperature. 9. tDQS2DQ(MAX) delay variation as a function of the DC voltage variation for VDDQ and VDD2. It includes the VDDQ and VDD2 AC noise impact for frequencies >20 MHz and MAX voltage of 45mV peak -to-peak from DC -20 MHz at a fixed temperature on the package. 10. The same voltage and temperature are applied to tDQS2DQ_rank2rank. 11. tDQS2DQ_rank2rank parameter is applied to multi -ranks per byte lane within a package consisting of the same design die.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 251/300 CKE Input Timing Parameter Symbol Min/ Max Data Rate Unit Note 1600 3200 3733 CKE minimum pulse width (HIGH and LOW pulse width) tCKE Min MAX(7.5ns, 4nCK) ns 1 Delay from valid command to CKE input LOW tCMDCKE Min MAX(1.75ns, 3nCK) ns 1 Valid clock requirement after CKE input LOW tCKELCK Min MAX(5ns, 5nCK) ns 1 Valid CS requirement before CKE input LOW tCSCKE Min 1.75 ns Valid CS requirement after CKE input LOW tCKELCS Min MAX(5ns, 5nCK) ns 1 Valid Clock requirement before CKE Input HIGH tCKCKEH Min MAX(1.75ns, 3nCK) ns 1 Exit power-down to next valid command delay tXP Min MAX(7.5ns, 5nCK) ns 1 Valid CS requirement before CKE input HIGH tCSCKEH Min 1.75 ns Valid CS requirement after CKE input HIGH tCKEHCS Min MAX(7.5ns, 5nCK) ns 1 Valid clock and CS requirement after CKE input LOW after MRW command tMRWCKEL Min MAX(14ns, 10nCK) ns 1 Valid clock and CS requirement after CKE input LOW after ZQCAL START command tZQCKE Min MAX(1.75ns, 3nCK) ns 1 Note: 1. Delay time has to satisfy both analog time(ns) and clock count (nCK). For example, tCMDCKE will not expire until CK has toggled through at least 3 full cycles (3tCK) and 3.75ns has transpired. The case that 3nCK is applied to is shown below. tCMDCKE Timing

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 252/300 Command Address Input Timing Parameter Symbol Min/ Max Data Rate Unit Note 533 1066 1600 2133 2667 3200 3733 Command/address valid window (referenced from CA VIL/VIH to CK VIX) tcIVW Min 0.3 tCK(AVG) 1, 2, 3 Address and control input pulse width (referenced to VREF) Note: 1. CA Rx mask timing parameters at the pin including voltage and temperature drift. 2. Rx differential CA to CK jitter total timing window at the VcIVW voltage levels. 3. Defined over the CA internal VREF range. The Rx mask at the pin must be within the internal VREF(CA) range irrespective of the input signal common mode. 4. CA only minimum input pulse width defined at the VCENT_CA(pin mid). Boot Timing Parameters (10–55 MHz) Parameter Symbol Min/ Max Value Unit Clock cycle time tCKb Min 18 ns Max 100 DQS output data acess time from CK tDQSCKb Min 1.0 ns Max 10.0 DQS edge to output data edge tDQSQb Max 1.2 ns Mode Register Timing Parameters Parameter Symbol Min/ Max Data Rate Unit 1600 3200 3733 MODE REGISTER WRITE (MRW) command period tMRW Min MAX(10ns, 10nCK) ns MODE REGISTER SET command delay tMRD Min MAX(14ns, 10nCK) ns MODE REGISTER READ (MRR) command period tMRR Min 8 tCK(AVG) Additional time after tXP has expired until the MRR command may be issued tMRRI Min tRCD(MIN) + 3nCK ns Delay from MRW command to DQS driven out tSDO Max MAX(12nCK, 20ns) ns

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 253/300 Core Timing Parameters Refresh rate is determined by the value in MR4 OP[2:0] Parameter Symbol Min/ Max Data Rate Unit Note 533 1066 1600 2133 2667 3200 3733 READ latency (DBI disabled) RL-A Min 6 10 14 20 24 28 32 tCK(AVG) READ latency (DBI enabled) RL-B Min 6 12 16 22 28 32 36 tCK(AVG) WRITE latency (Set A) WL-A Min 4 6 8 10 12 14 16 tCK(AVG) WRITE latency (Set B) WL-B Min 4 8 12 18 22 26 30 tCK(AVG) ACTIVATE-to-ACTIVATE command period (same bank) tRC Min tRAS + tRPab (with all-bank precharge) tRAS + tRPpb (with per-bank precharge) ns Minimum self refresh time (entry to exit) tSR Min MAX(15ns, 3nCK) ns Self refresh exit to next valid command delay tXSR Min MAX(tRFCab + 7.5ns, 2nCK) ns CAS-to-CAS delay tCCD Min 8 tCK(AVG) CAS-to-CAS delay masked write tCCDMW Min 32 tCK(AVG) Internal READ-to-PRE- CHARGE command delay tRTP Min MAX(7.5ns, 8nCK) ns RAS-to-CAS delay tRCD Min MAX(18ns, 4nCK) ns Row precharge time ( single bank) tRPpb Min MAX(18ns, 3nCK) ns Row precharge time (all banks) tRPab Min MAX(21ns, 3nCK) ns Row active time tRAS Min MAX(42ns, 3nCK) ns Max MIN(9 × tREFI × Refresh Rate, 70.2) µs Write recovery time tWR Min MAX(18ns, 4nCK) ns Write-to-read delay tWTR Min MAX(10ns, 8nCK) ns Active bank A to active bank B tRRD Min MAX(10ns, 4nCK) ns Precharge-to-precharge delay tPPD Min 4 tCK(AVG) 1 Four-bank activate window tFAW Min 40 ns Delay from SRE command to CKE input LOW tESCKE Min MAX(1.75ns, 3nCK) – 2 Note: 1. Precharge to precharge timing restriction does not apply to AUTO PRECHARGE commands. 2. Delay time has to satisfy both analog time (ns) and clock count (nCK). It means that tESCKE will not expire until CK has toggled through at least three full cycles (3 tCK) and 1.75ns has transpired. The case which 3nCK is applied to is shown below.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 254/300 tESCKE Timing CA Bus ODT Timing Parameter Symbol Min/ Max Data Rate 533-3733 CA ODT value update time tODTUP Min RU(20ns/tCK(AVG))

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 255/300 CA Bus Training Parameters Parameter Symbol Min/ Max Data Rate Unit Note 1600 3200 3733 Valid clock requirement after CKE input LOW tCKELCK Min MAX(5ns, 5nCK) tCK Data setup for VREF training mode tDStrain Min 2 ns Data hold for VREF training mode tDHtrain Min 2 ns Asynchronous data read tADR Max 20 ns CA BUS TRAINING command-to-command delay tCACD Min RU(tADR/tCK) tCK 1 Valid strobe requirement before CKE LOW tDQSCKE Min 10 ns First CA BUS TRAINING command fol- lowing CKE LOW tCAENT Min 250 ns VREF step time – multiple steps tVREFca_LONG Max 250 ns VREF step time – one step tVREFca_SHORT Max 80 ns Valid clock requirement before CS HIGH tCKPRECS Min 2tCK + tXP – Valid clock requirement after CS HIGH tCKPSTCS Min MAX(7.5ns, 5nCK) – Minimum delay from CS to DQS toggle in command bus training tCS_VREF Min 2 tCK Minimum delay from CKE HIGH to strobe High-Z tCKEHDQS Min 10 ns CA bus training CKE HIGH to DQ tristate tMRZ Min 1.5 ns ODT turn-on latency from CKE tCKELODTon Min 20 ns ODT turn-off latency from CKE tCKEHODToff Min 20 ns Exit command bus training mode to next valid command delay tXCBT_Short Min MAX(200ns, 5nCK) – 2 tXCBT_Middle Min MAX(200ns, 5nCK) – 2 tXCBT_Long Min MAX(250ns, 5nCK) – 2 Note: 1. If tCACD is violated, the data for samples which violate tCACD will not be available, except for the last sample (where tCACD after this sample is met). Valid data for the last sample will be available after tADR. 2. Exit command bus training mode to next valid command delay time depends on value of V REF(CA) setting: MR12 OP[5:0] and VREF(CA) range: MR12 OP[6] of FSP-OP 0 and 1. The details are shown in tFC value mapping table. Additionally exit command bus training mode to next valid command delay time may affect VREF(DQ) setting. Settling time of VREF(DQ) level is same as VREF(CA) level.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 256/300 Asynchronous ODT Turn On and Turn Off Timing Symbol 800–1866 MHz Unit tODTon(MIN) 1.5 ns tODTon(MAX) 3.5 ns tODToff(MIN) 1.5 ns tODToff(MAX) 3.5 ns Temperature Derating Parameters Parameter Symbol Min/ Max Data Rate Unit 1600 3200 3733 DQS output access time from CK_t/CK_c (derated) tDQSCKd Max 3600 ps RAS-to-CAS delay (derated) tRCDd Min tRCD + 1.875 ns ACTIVATE-to-ACTIVATE command period (same bank, derated) tRCd Min tRC + 3.75 ns Row active time (derated) tRASd Min tRAS + 1.875 ns Row precharge time (derated) tRPd Min tRP + 1.875 ns Active bank A to active bank B (derated) tRRDd Min tRRD + 1.875 ns Note: 1. At higher temperatures (>85°C), AC timing derating may be required. If derating is required the device will set MR4 OP[2:0] = 110b.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 257/300 CA Rx Voltage and Timing The command and address (CA), including CS input receiver compliance mask for voltage and timing, is shown in the CA Receiver (Rx) Mask figure below. All CA and CS signals apply the same compliance mask and operate in single data rate mode. The CA input Rx mask for voltage and timing is applied across all pins, as shown in the figure below. The Rx mask defines the area that the input signal must not encroach if the DRAM input receiver is expected to successfully capture a valid input signal; it is not the valid data eye. CA Receiver (Rx) Mask Across Pin VREF (CA) Voltage Variation VCENT_CA(pin mid) is defined as the midpoint between the largest V CENT_CA voltage level and the smallest V CENT_CA voltage level across all CA and CS pins for a given DRAM component. Each CA V CENT level is defined by the center, which is, the widest opening of the cumulative data input eye, as depicted in the figure above. This clarifies that any DRAM component level variation must be accounted for within the CA Rx mask. The component -level VREF will be set by the system to account for R ON and ODT settings.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 258/300 CA Timings at the DRAM Pins Note: 1. All of the timing terms in above figure are measured from the CK_t/CK_c to the center (midpoint) of the TcIVW window taken at the VcIVW_total voltage levels centered around VCENT_CA(pin mid). tcIPW and SRIN_cIVW Definition (for Each Input Pulse) Note: 1. SRIN_cIVW = VdIVW_total/(tr or tf); signal must be monotonic within tr and tf range. CA VIHL_AC Definition (for Each Input Pulse)

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 259/300 DRAM CMD/ADR, CS UI = tCK(AVG)MIN Symbol Parameter DQ – 13337 DQ – 1600/1867 DQ – 3200/3733 Unit Note Min Max Min Max Min Max VclVW Rx mask voltage peak-to- peak – 175 – 175 – 155 mV 1, 2, 3 VIHL(AC) CA AC input pulse amplitude peak-to-peak 210 – 210 – 190 – mV 4, 6 SRIN_clVW Input slew rate over VclVW 1 7 1 7 1 7 V/ns 5 Note: 1. CA Rx mask voltage and timing parameters at the pin, including voltage and temperature drift. 2. Rx mask voltage VcIVW total(MAX) must be centered around VCENT_CA(pin mid). 3. Defined over the CA internal VREF range. The Rx mask at the pin must be within the internal VREF(CA) range irrespective of the input signal common mode. 4. CA-only input pulse signal amplitude into the receiver must meet or exceed VIHL(AC) at any point over the total UI. No timing requirement above level. VIHL(AC) is the peak-to- peak voltage centered around VCENT_CA(pin mid), such that VIHL(AC)/2 (MIN) must be met both above and below VCENT_CA. 5. Input slew rate over VcIVW mask is centered at VCENT_CA(pin mid). 6. VIHL(AC) does not have to be met when no transitions are occurring. 7. The Rx voltage and absolute timing requirements apply for DQ operating frequencies at or below 1333 for all speed bins. For example the tcIVW (ps) = 450ps at or below 1333 operating frequencies.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 260/300 DQ Tx Voltage and Timing DRAM Data Timing Read Data Timing Definitions – tQH and tDQSQ Across DQ Signals per DQS Group

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 261/300 DQ Rx Voltage and Timing The DQ input receiver mask for voltage and timing is applied per pin, as shown in the DQ Receiver (Rx) Mask figure below. The total mask (V dIVW_total, TdIVW_total) defines the area that the input signal must not encroach in order for the DQ input receiver to successfully capture an input signal. The mask is a receiver property, and it is not the valid data eye. DQ Receiver (Rx) Mask Across Pin VREF DQ Voltage Variation VCENT_DQ(pin_mid) is defined as the midpoint between the largest VCENT_DQ voltage level and the smallest VCENT_DQ voltage level across all DQ pins for a given DRAM component. Each VCENT_DQ is defined by the center, which is the widest opening of the cumulative data input eye as shown in the figure above. This clarifies that any DRAM component level variation must be accounted for within the DRAM Rx mask. The componentlevel VREF will be set by the system to account for RON and ODT settings.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 262/300 DQ-to-DQS tDQS2DQ and tDQDQ Note: 1. These timings at the DRAM pins are referenced from the internal latch. 2. tDQS2DQ is measured at the center (midpoint) of the TdIVW window. 3. DQz represents the MAX tDQS2DQ in this example. 4. DQy represents the MIN tDQS2DQ in this example. All of the timing terms in DQ to DQS_t are measured from the DQS_t/DQS_c to the center (midpoint) of the TdIVW window taken at the VdIVW_total voltage levels centered around VCENT_DQ(pin_mid). In figure above, the timings at the pins are referenced with respect to all DQ signals center-aligned to the DRAM internal latch. The data-to-data offset is defined as the difference between the MIN and MAX tDQS2DQ for a given component.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 263/300 DQ tDIPW and SRIN_dIVW Definition for Each Input Pulse Note: 1. SRIN_dIVW = VdIVW_total/(tr or tf) signal must be monotonic within tr and tf range. DQ VIHL(AC) Definition (for Each Input Pulse)

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 264/300 DQs In Receive Mode Note UI = tCK(AVG)(MIN)/2 Symbol Parameter 1600/1867 2133/2400 3200/3733 Unit Note Min Max Min Max Min Max VdIVW_total Rx mask voltage – peak-to- peak – 140 – 140 – 140 mV 1, 2, 3 VIHL(AC) DQ AC input pulse amplitude peak-to-peak 180 – 180 – 180 – mV 5, 7 SRIN_dIVW Input slew rate over VdIVW_total 1 7 1 7 1 7 V/ns 6 Note: 1. Data Rx mask voltage and timing parameters are applied per pin and include the DRAM DQ -to-DQS voltage AC noise impact for frequencies > 20 MHz with a maximum voltage of 45mV peak -to-peak at a fixed temperature on the package. The voltage supply noise must comply to the component MIN/MAX DC operating conditions. 2. Rx mask voltage VdIVW_total(MAX) must be centered around VCENT_DQ(pin_mid). 3. Defined over the DQ internal VREF range. The Rx mask at the pin must be within the internal VREF DQ range irrespective of the input signal common mode. 4. Deterministic component of the total Rx mask voltage or timing. Parameter will be characterized and guaranteed by design. 5. DQ-only input pulse amplitude into the receiver must meet or exceed V IHL(AC) at any point over the total UI. No timing requirement above level. V IHL(AC) is the peak -to-peak voltage centered around V CENT_DQ(pin_mid), such that V IHL(AC)/2 (MIN) must be met both above and below VCENT_DQ. 6. Input slew rate over VdIVW mask centered at VCENT_DQ(pin_mid). 7. VIHL(AC) does not have to be met when no transitions are occurring.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 265/300 Clock Specification The specified clock jitter is a random jitter with Gaussian distribution. Input clocks violating minimum or maximum values may result in device malfunction. Definitions and Calculations Symbol Description Calculation Note tCK(avg) and nCK The average clock period across any consecutive 200-cycle window. Each clock period is calculated from rising clock edge to rising clock edge. Unit tCK(avg) represents the actual clock average tCK(avg) of the input clock under operation. Unit nCK represents one clock cycle of the input clock, counting from actual clock e dge to actual clock edge. tCK(avg) can change no more than ±1% within a 100-clock-cycle window, provided that all jitter and timing specifications are met. N tCK(avg) = Σ tCKj /N j=1 Where N = 200 [ ] tCK(abs) The absolute clock period, as measured from one rising clock edge to the next consecutive rising clock edge. tCH(avg) The average HIGH pulse width, as calculated across any 200 consecutive HIGH pulses. N tCH(avg) = Σ tCHj /(N × tCK(avg)) j=1 Where N = 200 [ ] tCL(avg) The average LOW pulse width, as calculated across any 200 consecutive LOW pulses. N tCL(avg) = Σ tCLj /(N × tCK(avg)) j=1 Where N = 200 [ ] tJIT(per) The single-period jitter defined as the largest de - viation of any signal tCK from tCK(avg). tJIT(per) = min/max of (tCKi - tCK(avg)) Where i = 1 to 200 tJIT(per),act The actual clock jitter for a given system. tJIT(per), allowed The specified clock period jitter allowance. tJIT(cc) The absolute difference in clock periods between two consecutive clock cycles. tJIT(cc) defines the cycle-to-cycle jitter. tJIT(cc) = max of (tCKi+1 - tCKi) 1 tERR(nper) The cumulative error across n multiple consecutive cycles from tCK(avg). i+n-1 tERR(nper) = Σ tCHj /(n × tCK(avg)) j=1 [ ] tERR(nper),act The actual clock jitter over n cycles for a given system. tERR(nper), allowed The specified clock jitter allowance over n cycles.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 266/300 Definitions and Calculations (Continued) Symbol Description Calculation Note tERR(nper),min The minimum tERR(nper). tERR(nper),min = (1 + 0.68LN(n)) × tJIT(per),min 2 tERR(nper),max The maximum tERR(nper). tERR(nper),max = (1 + 0.68LN(n)) × tJIT(per),max 2 tJIT(duty) Defined with absolute and average specifications for tCH and tCL, respectively. tJIT(duty),min = MIN((tCH(abs),min – tCH(avg),min), (tCL(abs),min – tCL(avg),min)) × tCK(avg) tJIT(duty),max = MAX((tCH(abs),max – tCH(avg),max), (tCL(abs),max – tCL(avg),max)) × tCK(avg) Note: 1. Not subject to production testing. 2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value. tCK(abs), tCH(abs), and tCL(abs) These parameters are specified with their average values; however, the relationship between the average timing and the absolute instantaneous timing (defined in the following table) is applicable at all times. tCK(abs), tCH(abs), and tCL(abs) Definitions Parameter Symbol Minimum Unit Absolute clock period tCK(abs) tCK(avg),min + tJIT(per),min ps1 Absolute clock HIGH pulse width tCH(abs) tCH(avg),min + tJIT(duty),min2/tCK(avg),min tCK(avg) Absolute clock LOW pulse width tCL(abs) tCL(avg),min + tJIT(duty),min2/tCK(avg),min tCK(avg) Note: 1. tCK(avg),min is expressed in ps for this table. 2. tJIT(duty),min is a negative value.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 267/300 Clock Period Jitter LPDDR4 devices can tolerate some clock period jitter without core timing parameter derating. This section describes device timing requirements with clock period jitter ( tJIT(per)) in excess of the values found in the AC Timing table. Calculating cycle time derating and clock cycle derating are also described. Clock Period Jitter Effects on Core Timing Parameters Core timing parameters (tRCD, tRP , tRTP , tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) extend across multiple clock cycles. Clock period jitter impacts these parameters when measured in numbers of clock cycles. Within the specification limits, the device is characterized and verified to support tnPARAM = RU[tPARAM/tCK(avg)]. During device operation where clock jitter is outside specification limits, the number of clocks, or tCK(avg), may need to be increased based on the values for each core timing parameter. Cycle Time Derating for Core Timing Parameters For a given number of clocks (tnPARAM), when tCK(avg) and tERR(tnPARAM),act exceed tERR(tnPARAM),allowed, cycle time derating may be required for core timing parameters. CycleTimeDerating = max {[ tPARAM(per) + tERR(tnPARAM),act - tERR(tnPARAM),allowed tnPARAM - tCK(avg)], 0} Cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time derating required is the maximum of the cycle time deratings determined for each individual core timing parameter. Clock Cycle Derating for Core Timing Parameters For each core timing parameter and a given number of clocks ( tnPARAM), clock cycle derating should be specified with tJIT(per). For a given number of clocks ( tnPARAM), when tCK(avg) plus ( tERR(tnPARAM),act) exceed the supported cumulative tERR(tnPARAM),allowed, derating is required. If the equation below results in a positive value for a core timing parameter (tCORE), the required clock cycle derating will be that positive value (in clocks). ClockCycleDerating = RU { tPARAM(per) + tERR(tnPARAM),act - tERR(tnPARAM),allowed tCK(avg) } - tnPARAM Cycle-time derating analysis should be conducted for each core timing parameter.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 268/300 Clock Jitter Effects on READ Timing Parameters tRPRE When the device is operated with input clock jitter, tRPRE must be derated by the tJIT(per),act,max of the input clock that exceeds tJIT(per),allowed,max. Output deratings are relative to the input clock: tRPRE(min,derated) = 0.9 - [ tJIT(per),act,max – tJIT(per),allowed, max tCK(avg) For example, if the measured jitter into a LPDDR4 device has tCK(avg) = 625ps, tJIT(per),act,min = –xx, and tJIT(per),act,max = +xx ps, then tRPRE,min,derated = 0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (xx - xx)/xx = yy tCK(avg). tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) These parameters are measured from a specific clock edge to a data signal transition (DMn or DQm, where: n = 0,1 ; and m = 0–15, and specified timings must be met with respect to that clock edge. Therefore, they are not affected by tJIT(per). tQSH, tQSL These parameters are affected by duty cycle jitter, represented by tCH(abs)min and tCL(abs)min. These parameters determine the absolute data -valid window at the device pin. The absolute minimum data -valid window at the device pin = MIN {(tQSH(abs)min - tDQSQmax), ( tQSL(abs)min - tDQSQmax)}. This minimum data valid window must be met at the target frequency regardless of clock jitter. tRPST tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 269/300 Clock Jitter Effects on WRITE Timing Parameters tDS, tDH These parameters are measured from a data signal (DMIn or DQm, where n = 0, 1 and m = 0 –15) transition edge to its respective data strobe signal (DQSn_t, DQSn_c: n = 0,1) crossing. The specification values are not affected by the amount of tJIT(per) applie d, because the setup and hold times are relative to the data strobe signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met. tDSS, tDSH These parameters are measured from a data signal (DQS_t, DQSn_c) c rossing to its respective clock signal (CK_t, CK_c) crossing. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per)act of the input clock in excess of the allowed period jitter tJIT(per)allowed. tDQSS tDQSS is measured from a data strobe signal (DQSn_t, DQSn_c) crossing to its respec- tive clock signal (CK_t, CK_c) crossing. When the device is operated with input clock jitter, this parameter must be derated by the actual tJIT(per),act of the input clock in excess of tJIT(per)allowed. tDQSS(min,derated) = 0.75 [ tJIT(per),act,min – tJIT(per),allowed, min tCK(avg) tDQSS(max,derated) = 1.25 [ tJIT(per),act,max – tJIT(per),allowed, max ]tCK(avg) For example, if the measured jitter into an LPDDR4 device has tCK(avg) = 625ps, tJIT(per),act,min = -xxps, and tJIT(per),act,max = +xx ps, then: tDQSS,(min,derated) = 0.75 - (-xx + yy)/625 = xxxx tCK(avg) tDQSS,(max,derated) = 1.25 - (xx – yy)/625 = xxxx tCK(avg)

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 270/300 LPDDR4 1.10V VDDQ This section defines LPDDR4 specifications to enable 1.10 VDDQ operation of LPDDR4 devices. Power-Up and Initialization - LPDDR4 To ensure proper functionality for power-up and reset initialization, default values for the MR settings are provided in the table below. Mode Register Default Settings Item Mode Register Setting Default Setting Description FSP-OP/WR MR13 OP[7:6] 00b FSP-OP/WR[0] are enabled WLS MR2 OP[6] 0b WRITE latency set A is selected WL MR2 OP[5:3] 000b WL = 4 RL MR2 OP[2:0] 000b RL = 6, nRTP = 8 nWR MR1 OP[6:4] 000b nWR = 6 DBI-WR/RD MR3 OP[7:6] 00b Write and read DBI are disabled CA ODT MR11 OP[6:4] 000b CA ODT is disabled DQ ODT MR11 OP[2:0] 000b DQ ODT is disabled VREF(CA) setting MR12 OP[6] 1b VREF(CA) range[1] is enabled VREF(CA) value MR12 OP[5:0] 001101b Range1: 27.2% of VDD2 VREF(DQ) setting MR14 OP[6] 1b VREF(DQ) range[1] enabled VREF(DQ) value MR14 OP[5:0] 001101b Range1: 27.2% of VDDQ

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 271/300 Mode Register Definition - LPDDR4 Mode register definitions are provided in the Mode Register Assignments table. In the access column of the table, R indicates read-only; W indicates write-only; R/W indicates read- or write-capable or enabled. The MRR command is used to read from a register. The MRW command is used to write to a register. Mode Register Assignments Note 1–5 apply to entire table MR# MA[5:0] Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 0 00h Device info R CATR RFU RFU RZQI RFU Latency mode REF 1 01h Device feature 1 W RD-PST nWR (for AP) RD-PRE WR-PRE BL 2 02h Device feature 2 W WR Lev WLS WL RL 3 03h I/O config-1 W DBI-WR DBI-RD PDDS PPRP WR-PST PU-CAL 4 04h Refresh and training R /W TUF Thermal offset PPRE SR abort Refresh rate 5 05h Basic config-1 R Manufacturer ID 6 06h Basic config-2 R Revision ID1 7 07h Basic config-3 R Revision ID2 8 08h Basic config-4 R I/O width Density Type 9 09h Test mode W Vendor-specific test mode 10 0Ah I/O calibration W RFU ZQ RST 11 0Bh ODT W RFU CA ODT RFU DQ ODT 12 0Ch VREF(CA) R/W RFU VRCA VREF(CA) 13 0Dh Register control W FSP-OP FSP-WR DMD RRO VRCG VRO RPT CBT 14 0Eh VREF(DQ) R/W RFU VRDQ VREF(DQ) 15 0Fh DQI-LB W Lower-byte invert register for DQ calibration 16 10h PASR_Bank W PASR bank mask 17 11h PASR_Seg W PASR segment mask 18 12h IT-LSB R DQS oscillator count – LSB 19 13h IT-MSB R DQS oscillator count – MSB 20 14h DQI-UB W Upper-byte invert register for DQ calibration 21 15h Vendor use W RFU 22 16h ODT feature 2 W ODTD for x8_2ch ODTD -CA ODTE -CS ODTE -CK SoC ODT

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 272/300 Mode Register Assignments (Continued) Note 1–5 apply to entire table Note: 1. RFU bits must be set to 0 during MRW commands. 2. RFU bits are read as 0 during MRR commands. 3. All mode registers that are specified as RFU or write-only shall return undefined data when read via an MRR command. 4. RFU mode registers must not be written. 5. Writes to read-only registers will not affect the functionality of the device. MR0 Device Feature 0 (MA[5:0] = 00h) MR# MA[5:0] Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 23 17h DQS oscillator stop W DQS oscillator run-time setting 24 18h TRR control R/W TRR mode TRR mode BAn Unltd MAC MAC value 25 19h PPR resources R B7 B6 B5 B4 B3 B2 B1 B0 26–29 1Ah~1Dh – – Reserved for future use 30 1Eh Reserved for test W SDRAM will ignore 31 1Fh – – Reserved for future use 32 20h DQ calibration pattern A W See DQ calibration section 33–38 21h≈26h Do not use – Do not use 39 27h Reserved for test W SDRAM will ignore 40 28h DQ calibration pattern B W See DQ calibration section 41–47 29h≈2Fh Do not use – Do not use 48–63 30h≈3Fh Reserved – Reserved for future use OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 CATR RFU RZQI RFU Latency mode REF

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 273/300 MR0 Op-Code Bit Definitions Note: 1. RZQI MR value, if supported, will be valid after the following sequence:  Completion of MPC[ZQCAL START] command to either channel  Completion of MPC[ZQCAL LATCH] command to either channel then tZQLAT is satisfied RZQI value will be lost after reset. 2. If ZQ is connected to V SSQ to set default calibration, OP[4:3] must be set to 01b. If ZQ is not connected to V SSQ, either OP[4:3] = 01b or OP[4:3] = 10b might indicate a ZQ pin assembly error. It is recommended that the assembly error be corrected. 3. In the case of possible assembly error, the device will default to factory trim settings for R ON, and will ignore ZQ CALIBRATION commands. In either case, the device may not function as intended. 4. If the ZQ pin self -test returns OP[4:3] = 11b, the device has detected a resistor connected to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor me ets the specified limits (that is, 240Ω 1%). 5. See byte mode addendum spec for byte mode latency details. 6. Byte mode latency for 2Ch. x16 device is only allowed when it is stacked in a same package with byte mode device. 7. CATR indicates whether CA for the rank will be terminated or not as a result of ODTCA pad connection and MR22 OP[5] settings for x16 devices, MR22 OP[7:5] settings for byte mode devices. Register Information Type OP Definition Note Refresh mode Read-only OP[0] 0b: Both legacy and modified refresh mode supported 1b: Only modified refresh mode supported Latency mode Read-only OP[1] 0b: Device supports normal latency 1b: Device supports byte mode latency 5, 6 Built-in self-test for RZQ information Read-only OP[4:3] 00b: RZQ self-test not supported 01b: ZQ may connect to VSSQ or float 10b: ZQ may short to VDDQ 11b: ZQ pin self-test completed, no error condition detected (ZQ may not connect to VSSQ, float, or short to VDDQ) 1–4 CA terminating rank Read only OP[7] 0b: CA for this rank is not terminated 7 1b: CA for this rank is terminated

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 274/300 MR3 I/O Configuration 1 (MA[5:0] = 03h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DBI-WR DBI-RD PDDS PPRP WR-PST PU-CAL MR3 Op-Code Bit Definitions Feature Type OP Definition Note PU-CAL (Pull-up calibration point) Write-only OP[0] 0b: VDDQ /2.5 1–4 1b: VDDQ /3 (default) WR-PST (WR postamble length) OP[1] 0b: WR postamble = 0.5 × tCK (default) 2, 3, 5 1b: WR postamble = 1.5 × tCK PPRP (Post-package repair protection) OP[2] 0b: PPR protection disabled (default) 1b: PPR protection enabled PDDS (Pull-down drive strength) OP[5:3] 000b: RFU 1, 2, 3 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 (default) 111b: Reserved DBI-RD (DBI-read enable) OP[6] 0b: Disabled (default) 2, 3 1b: Enabled DBI-WR (DBI-write enable) OP[7] 0b: Disabled (default) 2, 3 1b: Enabled Note: 1. All values are typical. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Recalibration may be required as voltage and temperature vary. 2. There are two physical registers assigned to each b it of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1.The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP ‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be determined by the state of the FSP ‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. 4. For dual-channel device, PU‐CAL (MR3‐OP[0]) must be set the same for both channels on a die. The SDRAM will read the value of only one register (Ch.A or Ch.B); the choice is vendor-specific, so both channels must be set the same. 5. 1.5 × tCK apply > 1.6 GHz clock. 6. If MR3 OP[2] is set to 1b, PPR protection mode is enabled. The PPR protection bit is a sticky bit and can only be set to 0b by a power on reset. MR4 OP[4] controls entry to PPR mode. If PPR protection is enabled then the DRAM will not allow writing of 1b to MR4 OP[4].

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 275/300 MR12 Register Information (MA[5:0] = 0Ch) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU VRCA VREF(CA) MR12 Op-Code Bit Definitions Feature Type OP Data Note VREF(CA) VREF(CA) settings Read/ Write OP[5:0] 000000b–110010b: See VREF Settings table All others: Reserved 1–3,5,6 VRCA VREF(CA) range Read/ Write OP[6] 0b: VREF(CA) range[0] enabled 1b: VREF(CA) range[1] enabled (default) 1,2,4,5,6 Note: 7. This register controls the V REF(CA) levels for frequency set point[1:0]. Values from either VR(ca)[0] or VR(ca)[1] may be selected by setting MR12 OP[6] appropriately. 8. A read to MR12 places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ will be set to 0. See the MRR Operation section. 9. A write to MR12 OP[5:0] sets the internal V REF(CA) level for FSP[0] when MR13 OP[6] = 0b or sets the internal V REF(CA) level for FSP[1] when MR13 OP[6] = 1b. The time required for V REF(CA) to reach the set level depends on the step size from the current level to the new level. See the VREF(CA) training section. 10. A write to MR12 OP[6] switches the device between two internal V REF(CA) ranges. The range (range[0] or range[1]) must be selected when setting the V REF(CA) register. The value, once set, will be retained until overwritten or until the next power‐on or reset event. 11. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the s tate of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 12. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set poin t 1. The device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP ‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 276/300 Mode Register 14 (MA[5:0] = 0Eh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU VRDQ VREF(DQ) MR14 Op-Code Bit Definition Feature Type OP Definition Note VREF(DQ) VREF(DQ) setting Read/ Write OP[5:0] 000000b–110010b: See VREF Settings table All others: Reserved 1–3,5,6 VRDQ VREF(DQ) range OP[6] 0b: VREF(DQ) range[0] enabled 1b: VREF(DQ) range[1] enabled (default) 1,2,4–6 Note: 1. This register controls the V REF(DQ) levels for frequency set point[1:0]. Values from either VR DQ[0] (vendor defined) or VRDQ[1] (vendor defined) may be selected by setting OP[6] appropriately. 2. A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused D Q shall be set to 0. See the MRR Operation section. 3. A write to OP[5:0] sets the internal VREF(DQ) level for FSP[0] when MR13 OP[6] = 0b, or sets FSP[1] when MR13 OP[6] = 1b. The time required for V REF(DQ) to reach the set level depends on the step size fro m the current level to the new level. See the VREF(DQ) training section. 4. A write to OP[6] switches the device between two internal V REF(DQ) ranges. The range (range[0] or range[1]) must be selected when setting the V REF(DQ) register. The value, once set, w ill be retained until overwritten, or until the next power‐on or reset event. 5. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state o f the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 6. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. T he device will operate only according to the values stored in the registers for the active set point, for example, the set point determined by the state of the FSP ‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 277/300 VREF Setting for Range[0] and Range[1] Note 1-3 apply to entire table Function OP Range[0] Values Range[1] Values VREF(CA) (% of VDDQ) VREF(DQ) (% of VDDQ) VREF(CA) (% of VDDQ) VREF(DQ) (% of VDDQ) VREF setting for MR12 and MR14 OP[5:0] 000000b: 10.0% 011010b: 20.4% 000000b: 22.0% 011010b: 32.4% 000001b: 10.4% 011011b: 20.8% 000001b: 22.4% 011011b: 32.8% 000010b: 10.8% 011100b: 21.2% 000010b: 22.8% 011100b: 33.2% 000011b: 11.2% 011101b: 21.6% 000011b: 23.2% 011101b: 33.6% 000100b: 11.6% 011110b: 22.0% 000100b: 23.6% 011110b: 34.0% 000101b: 12.0% 011111b: 22.4% 000101b: 24.0% 011111b: 34.4% 000110b: 12.4% 100000b: 22.8% 000110b: 24.4% 100000b: 34.8% 000111b: 12.8% 100001b: 23.2% 000111b: 24.8% 100001b: 35.2% 001000b: 13.2% 100010b: 23.6% 001000b: 25.2% 100010b: 35.6% 001001b: 13.6% 100011b: 24.0% 001001b: 25.6% 100011b: 36.0% 001010b: 14.0% 100100b: 24.4% 001010b: 26.0% 100100b: 36.4% 001011b: 14.4% 100101b: 24.8% 001011b: 26.4% 100101b: 36.8% 001100b: 14.8% 100110b: 25.2% 001100b: 26.8% 100110b: 37.2% 001101b: 15.2% 100111b: 25.6% 001101b: 27.2% default 100111b: 37.6% 001110b: 15.6% 101000b: 26.0% 001110b: 27.6% 101000b: 38.0% 001111b: 16.0% 101001b: 26.4% 001111b: 28.0% 101001b: 38.4% 010000b: 16.4% 101010b: 26.8% 010000b: 28.4% 101010b: 38.8% 010001b: 16.8% 101011b: 27.2% 010001b: 28.8% 101011b: 39.2% 010010b: 17.2% 101100b: 27.6% 010010b: 29.2% 101100b: 39.6% 010011b: 17.6% 101101b: 28.0% 010011b: 29.6% 101101b: 40.0% 010100b: 18.0% 101110b: 28.4% 010100b: 30.0% 101110b: 40.4% 010101b: 18.4% 101111b: 28.8% 010101b: 30.4% 101111b: 40.8% 010110b: 18.8% 110000b: 29.2% 010110b: 30.8% 110000b: 41.2% 010111b: 19.2% 110001b: 29.6% 010111b: 31.2% 110001b: 41.6% 011000b: 19.6% 110010b: 30.0% 011000b: 31.6% 110010b: 42.0% 011001b: 20.0% All others: Reserved 011001b: 32.0% All others: Reserved Note: 1. These values may be used for MR14 OP[5:0] and MR12 OP[5:0] to set the VREF(CA) or VREF(DQ) levels in the device. 2. The range may be selected in each of the MR14 or MR12 registers by setting OP[6] appropriately. 3. Each of the MR14 or MR12 registers represents either FSP[0] or FSP[1]. Two frequency set points e ach for CA and DQ are provided to allow for faster switching between terminated and unterminated operation or between different high‐frequency settings, which may use different terminations values.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 278/300 MR22 Register Information (MA[5:0] = 16h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 ODTD for x8_2ch ODTD-CA ODTE-CS ODTE-CK SOC ODT MR22 Register Information Feature Type OP Definition Note SOC ODT (controller ODT value for VOH calibration) Write-only OP[2:0] 000b: Disable (default) 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 111b: RFU 1, 2, 3 ODTE-CK (CK ODT enabled for non-terminating rank) Write-only OP[3] 0b: ODT-CK override enable (default) 1b: ODT-CK override disable 2, 3, 4, 6, 8 ODTE-CS (CS ODT enabled for non-terminating rank) Write-only OP[4] 0b: ODT-CS override enable (default) 1b: ODT-CS override disable 2, 3, 5, 6, 8 ODTD-CA (CA ODT termination disable) Write-only OP[5] ODT bond PAD is ignored 0b: CA ODT obeys ODT_CA bond pad (default) 1b: CA ODT disable 2, 3, 6, 7, 8 ODTD for x8_2ch (Byte) mode Write-only OP[7:6] See Byte Mode section Note: 1. All values are typical. 2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP -WR bit (MR13 OP[6]) will be written to with an MRW command or read from with an MRR command to this address. 3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation. 4. When OP[3] = 1 the CK signals will be terminated to the value set by MR11 OP[6:4] regardless of the state of the ODT_CA bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more devices but CK is not, enabling CK to terminate on all devices. 5. When OP[4] = 1 the CS signal will be terminated to the value set by MR11 OP[6:4] regardless of the state of the ODT_CA bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more devices but CS is not, enabling CS to terminate on all devices. 6. For system configurations where the CK, CS, and CA signals are shared between packages, the package design should provide for the ODT_CA ball to be bonded on the system board outside of the memory package. This provides the necessary control of the ODT function for all die with shared command bus signals. 7. When OP[5] = 0, CA[5:0] will terminate when the ODT_CA bond pad is HIGH and MR11 OP[6:4] is valid and disable termination when ODT_CA is LOW or MR11 OP[6:4] is disabled. When OP[5] = 1, termination for CA[5:0] i s disabled regardless of the state of the ODT_CA bond pad or MR11 OP[6:4]. 8. To ensure proper operation in a multi -rank configuration, when CA, CK or CS ODT is enabled via MR11 OP[6:4] and also via MR22 or ODT_CA pad setting, the rank providing ODT will continue to terminate the command bus in all DRAM states including Active, Self-refresh, Self-refresh Power-down, Active Power-down and Precharge Power-down.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 279/300 Burst READ Operation - LPDDR4 ATE Condition tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ). Th is section shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single ended. tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) tLZ(DQS) Method for Calculating Transitions and Endpoint Note: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ/3. 2. Termination condition for DQS_t and DQS_C = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 280/300 tHZ(DQS) Method for Calculating Transitions and Endpoint Note: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ/3. 2. Termination condition for DQS_t and DQS_C = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements. Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements Measured Parameter Measured Parameter Symbol Vsw1 Vsw2 Unit DQS_c Low-Z time from CK_t, CK_c tLZ(DQS) 0.4 × VOH 0.6 × VOH V DQS_c High-Z time from CK_t, CK_c tHZ(DQS) 0.4 × VOH 0.6 × VOH V

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 281/300 tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) tLZ(DQ) Method for Calculating Transitions and Endpoint Note: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ/3. 2. Termination condition for DQ and DMI = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 282/300 tHZ(DQ) Method for Calculating Transitions and Endpoint Note: 1. Conditions for calibration: Pull down driver RON = 40 ohms, VOH = VDDQ/3. 2. Termination condition for DQ and DMI = 50 ohms to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements. Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements Measured Parameter Measured Parameter Symbol Vsw1 Vsw2 Unit DQ Low-Z time from CK_t, CK_c tLZ(DQ) 0.4 × VOH 0.6 × VOH V DQ High-Z time from CK_t, CK_c tHZ(DQ) 0.4 × VOH 0.6 × VOH V

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 283/300 VREF Specifications - LPDDR4 Internal VREF(CA) Specifications The device's internal VREF(CA) specification parameters are operating voltage range, step size, VREF step time, VREF full-range step time, and VREF valid level. The voltage operating range specifies the minimum required VREF setting range for LPDDR4 devices. The minimum range is defined by VREF,max and VREF,min. Internal VREF(CA) Specifications Symbol Parameter Min Typ Max Unit Note VREF(CA),max_r0 VREF(CA) range-0 MAX operating point – – 30% VDD2 1, 11 VREF(CA),min_r0 VREF(CA) range-0 MIN operating point 10% – – VDD2 1, 11 VREF(CA),max_r1 VREF(CA) range-1 MAX operating point – – 42% VDD2 1, 11 VREF(CA),min_r1 VREF(CA) range-1 MIN operating point 22% – – VDD2 1, 11 VREF(CA),step VREF(CA) step size 0.30% 0.40% 0.50% VDD2 2 VREF(CA),set_tol VREF(CA) set tolerance tVREF_TIME-SHORT VREF(CA) step time – – 100 ns 8 tVREF_TIME-MIDDLE – – 200 ns 12 tVREF_TIME-LONG – – 250 ns 9 tVREF_time_weak – – 1 ms 13, 14 VREF(CA)_val_tol VREF(CA) valid tolerance –0.10% 0.00% 0.10% VDD2 10 Note: 1. VREF(CA) DC voltage referenced to VDD2(DC). 2. VREF(CA) step size increment/decrement range. VREF(CA) at DC level. 3. VREF(CA),new = VREF(CA),old + n × VREF(CA),step; n = number of steps; if increment, use "+"; if decrement, use "–". 4. The minimum value of V REF(CA) setting tolerance = V REF(CA),new - 1.0% × V DD2. The maximum value of V REF(CA) setting tolerance = VREF(CA),new + 1.0% × VDD2. For n > 4. 5. The minimum value of V REF(CA) setting tolerance = V REF(CA),new - 0.10% × V DD2. The maximum value of V REF(CA) setting tolerance = VREF(CA),new + 0.10% × VDD2. For n < 4. 6. Measured by recording the minimum and maximum values of the V REF(CA) output over the range, drawing a straight line between those points and comparing all other VREF(CA) output settings to that line. 7. Measured by recording the minimum and maximum values of the V REF(CA) output across four consecutive steps (n = 4), drawing a straight line between those points and compar- ing all other VREF(CA) output settings to that line. 8. Time from MRW command to increment or decrement one step size for VREF(CA). 9. Time from MRW command to increment or decrement VREF,min to VREF,max or VREF,max to VREF,min change across the VREF(CA) range in VREF voltage. 10. Only applicable for DRAM component level tes t/characterization purposes. Not applicable for normal mode of operation. VREF valid is to qualify the step times which will be characterized at the component level. 11. DRAM range-0 or range-1 set by MR12 OP[6]. 12. Time from MRW command to increment or decrement more than one step size up to a full range of VREF voltage within the same VREF(CA) range. 13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0b. 14. tVREF_time_weak covers all VREF(CA) range and value change conditions are applied to tVREF_TIME-SHORT/MIDDLE/LONG.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 284/300 Internal VREF(DQ) Specifications The device's internal VREF(DQ) specification parameters are operating voltage range, step size, VREF step tolerance, VREF step time and VREF valid level. The voltage operating range specifies the minimum required VREF setting range for LPDDR4 devices. The minimum range is defined by VREF,max and VREF,min. Internal VREF(DQ) Specifications Symbol Parameter Min Typ Max Unit Note VREF(DQ),max_r0 VREF MAX operating point Range-0 – – 30% VDDQ 1, 11 VREF(DQ),min_r0 VREF MIN operating point Range-0 10% – – VDDQ 1, 11 VREF(DQ),max_r1 VREF MAX operating point Range-1 – – 42% VDDQ 1, 11 VREF(DQ),min_r1 VREF MIN operating point Range-1 22% – – VDDQ 1, 11 VREF(DQ),step VREF(DQ) step size 0.30% 0.40% 0.50% VDDQ 2 VREF(DQ),set_tol VREF(DQ) set tolerance tVREF_TIME-SHORT VREF(DQ) step time – – 100 ns 8 tVREF_TIME-MIDDLE – – 200 ns 12 tVREF_TIME-LONG – – 250 ns 9 tVREF_time_weak – – 1 ms 13, 14 VREF(DQ),val_tol VREF(DQ) valid tolerance –0.10% 0.00% 0.10% VDDQ 10 Note: 1. VREF(DQ) DC voltage referenced to VDDQ(DC). 2. VREF(DQ) step size increment/decrement range. VREF(DQ) at DC level. 3. VREF(DQ),new = VREF(DQ),old + n × VREF(DQ),step; n = number of steps; if increment, use "+"; if decrement, use "–". 4. The minimum value of V REF(DQ) setting tolerance = V REF(DQ),new - 1.0% × V DDQ. The maximum value of V REF(DQ) setting tolerance = VREF(DQ),new + 1.0% × VDDQ. For n > 4. 5. The minimum value of V REF(DQ) setting tolerance = V REF(DQ),new - 0.10% × V DDQ. The maximum value of V REF(DQ) setting tolerance = VREF(DQ),new + 0.10% × VDDQ. For n < 4. 6. Measured by recording the minimum and maximum values of the V REF(DQ) output over the range, drawing a straight line between those points and comparing all other VREF(DQ) output settings to that line. 7. Measured by recording the minimum and maximum values of the V REF(DQ) output across four consecutive steps (n = 4), drawing a straight line between those points and compar- ing all other VREF(DQ) output settings to that line. 8. Time from MRW command to increment or decrement one step size for VREF(DQ). 9. Time from MRW command to increment or decrement VREF,min to VREF,max or VREF,max to VREF,min change across the VREF(DQ) Range in VREF(DQ) Voltage. 10. Only applicable for DRAM component level test/characterization purposes. Not applicable for normal mode of operation. VREF valid is to qualify the step times which will be characterized at the component level. 11. DRAM range-0 or range-1 set by MR14 OP[6]. 12. Time from MRW command to increment or decrement more than one step size up to a full range of VREF voltage within the same VREF(DQ) range. 13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0. 14. tVREF_time_weak covers all VREF(DQ) Range and Value change conditions are applied to tVREF_TIME-SHOR/MIDDLE/LONG.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 285/300 Command Definitions and Timing Diagrams - LPDDR4 Pull Up/Pull Down Driver Characteristics and Calibration Pull-Down Driver Characteristics – ZQ Calibration RONPD,nom Register Min Nom Max Unit 40 ohms RON40PD 0.90 1.0 1.10 RZQ/6 48 ohms RON48PD 0.90 1.0 1.10 RZQ/5 60 ohms RON60PD 0.90 1.0 1.10 RZQ/4 80 ohms RON80PD 0.90 1.0 1.10 RZQ/3 Note: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%. Pull-Up Characteristics – ZQ Calibration VOHPU,nom VOH,nom Min Nom Max Unit VDDQ/2.5 440 0.90 1.0 1.10 VOH,nom VDDQ/3 367 0.90 1.0 1.10 VOH,nom Note: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%. 2. VOH,nom (mV) values are based on a nominal VDDQ = 1.1V. Terminated Valid Calibration Points VOHPU ODT Value 240 120 80 60 48 40 VDDQ/2.5 Valid Valid Valid DNU DNU DNU VDDQ/3 Valid Valid Valid Valid Valid Valid Note: 1. Once the output is calibrated for a given VOH(nom) calibration point, the ODT value may be changed without recalibration. 2. If the VOH(nom) calibration point is changed, then recalibration is required. 3. DNU = Do not use.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 286/300 On-Die Termination for the Command/Address Bus The on-die termination (ODT) feature allows the device to turn on/off termination resistance for CK_t, CK_c, CS, and CA[5:0] signals without the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to turn on and off termination resistance for any target DRAM devices via the mode register setting. A simple functional representation of the DRAM ODT feature is shown below. ODT for CA

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 287/300 ODT Mode Register and ODT State Table ODT termination values are set and enabled via MR11. The CA bus (CK_t, CK_c, CS, CA[5:0]) ODT resistance values are set by MR11 OP[6:4]. The default state for the CA is ODT disabled. ODT is applied on the CA bus to the CK_t, CK_c, CS, and CA signals. The CA ODT of the device is designed to enable one rank to terminate the entire command bus in a multi - rank system, so only one termination load will be present even if multiple devices are sharing the command signals. For this reason, CA ODT remains on, even when the de- vice is in the power-down or self refresh power-down state. The die has a bond pad (ODT_CA) for multirank operations. When the ODT_CA pad is LOW, the die will not terminate the CA bus regardless of the state of the mode register CA ODT bits (MR11 OP[6:4]). If, however, the ODT_CA bond pad is HIGH and the mode register CA ODT bits are enabled, the die will terminate the CA bus with the ODT values found in MR11 OP[6:4]. In a multirank system, the terminating rank should be trained first, followed by the non-terminating rank(s). Command Bus ODT State CA ODT MR11[6:4] ODT_CA Bond Pad ODTD-CA MR22 OP[5] ODTE-CK MR22 OP[3] ODTE-CS MR22 OP[4] ODT State for CA ODT State for CK ODT State for CS Disabled1 Valid2 Valid3 Valid3 Valid3 Off Off Off Valid3 0 Valid3 0 0 Off Off Off Valid3 0 Valid3 0 1 Off Off On Valid3 0 Valid3 1 0 Off On Off Valid3 0 Valid3 1 1 Off On On Valid3 1 0 Valid3 Valid3 On On On Valid3 1 1 Valid3 Valid3 Off On On Note: 1. Default value. 2. Valid = H or L (a defined logic level) 3. Valid = 0 or 1. 4. The state of ODT_CA is not changed when the device enters power-down mode. This maintains termination for alternate ranks in multirank systems.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 288/300 ODT Mode Register and ODT Characteristics RZQ = 240Ω ±1% over entire operating range after calibration MR11 OP[6:4] RTT VOUT Min Nom Max Unit Note 001b 240Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/1 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 010b 120Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/2 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 011b 80Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/3 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 100b 60Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/4 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 101b 48Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/5 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 110b 40Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/6 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 Mismatch, CA -CA within clock group 0.33 × VDD2 – – 2 % 1, 2, 3 Note: 1. The tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the section on voltage and temperature sensitivity. 2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDD2. Other calibration points may be required to achieve the linearity specification shown above, for example, calibration at 0.5 × VDD2 and 0.1 × VDD2. 3. CA to CA mismatch within clock group variation for a given component including CK_t, CK_c ,and CS (characterized).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 289/300 RZQ = 240Ω ±1% over entire operating range after calibration MR11 OP[6:4] RTT VOUT Min Nom Max Unit Note 001b 240Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/1 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 010b 120Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/2 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 011b 80Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/3 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 100b 60Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/4 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 101b 48Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/5 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 110b 40Ω VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/6 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 Mismatch, CA -CA within clock group 0.33 × VDD2 – – 2 % 1, 2, 3 Note: 1. The tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the section on voltage and temperature sensitivity. 2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDD2. Other calibration points may be required to 3. CA to CA mismatch within clock group variation for a given component including CK_t, CK_c ,and CS (characterized).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 290/300 DQ On-Die Termination On-die termination (ODT) is a feature that allows the device to turn on/off termination resistance for each DQ, DQS, and DMI signal without the ODT control pin. The OD T feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to turn on and off termination resistance for any target DRAM devices during WRITE or MASK WRITE operation. The ODT feature is off and cannot be supported in power-down and self refresh modes. The switch is enabled by the internal ODT control logic, which uses the WRITE -1 or MASK WRITE-1 command and other mode register control information. The value of RTT is determined by the MR bits. Functional Representation of DQ ODT

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 291/300 RZQ = 240Ω ±1% over entire operating range after calibration MR11 OP[6:4] RTT VOUT Min Nom Max Unit Note 001b 240Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/1 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 010b 120Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/2 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 011b 80Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/3 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 100b 60Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/4 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 101b 48Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/5 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 110b 40Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/6 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 Mismatch, DQ-DQ within clock group 0.33 × VDDQ – – 2 % 1, 2, 3 Note: 1. The ODT tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the following section on voltage and temperature sensitivity. 2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × V DDQ. Other calibration points may be required to achieve the linearity specification shown above, (for example, calibration at 0.5 × VDDQ and –0.1 × VDDQ. 3. DQ-to-DQ mismatch within byte variation for a given component, including DQS (characterized).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 292/300 RZQ = 240Ω ±1% over entire operating range after calibration MR11 OP[6:4] RTT VOUT Min Nom Max Unit Note 001b 240Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/1 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 010b 120Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/2 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 011b 80Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/3 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 100b 60Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/4 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 101b 48Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/5 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 110b 40Ω VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/6 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 Mismatch, DQ-DQ within clock group 0.33 × VDDQ – – 2 % 1, 2, 3 Note: 1. The ODT tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the following section on voltage and temperature sensitivity. 2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × V DDQ. Other calibration points may be required to achieve the linearity specification shown above, (for example, calibration at 0.5 × VDDQ and –0.1 × VDDQ. 3. DQ-to-DQ mismatch within byte variation for a given component, including DQS (characterized).

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 293/300 Output Driver and Termination Register Temperature and Voltage Sensitivity When temperature and/or voltage change after calibration, the tolerance limits are widen according to the tables below. Output Driver and Termination Register Sensitivity Definition Resistor Definition Point Min Max Unit Notes RONPD 0.33 × VDDQ 90 - (dRONdT × |ΔT|) - (dRONdV × |ΔV|) 110 + (dRONdT × |ΔT|) + (dRONdV × |ΔV|) 1, 2 VOHPU 0.33 × VDDQ 90 - (dVOHdT × |ΔT|) - (dVOHdV × |ΔV|) 110 + (dVOHdT × |ΔT|) + (dVOHdV × |ΔV|) 1, 2, 5 RTT(I/O) 0.33 × VDDQ 90 - (dRONdT × |ΔT|) - (dRONdV × |ΔV|) 110 + (dRONdT × |ΔT|) + (dRONdV × |ΔV|) 1, 2, 3 RTT(IN) 0.33 × VDD2 90 - (dRONdT × |ΔT|) - (dRONdV× |ΔV|) 110 + (dRONdT × |ΔT|) + (dRONdV × |ΔV|) 1, 2, 4 Note: 1. ΔT = T - T(@calibration), ΔV = V - V(@calibration) 2. dRONdT, dRONdV, dV OHdT, dV OHdV, dR TTdV, and dR TTdT are not subject to production test but are verified by design and characterization. 3. This parameter applies to input/output pin such as DQS, DQ, and DMI. 4. This parameter applies to input pin such as CK, CA, and CS. 5. Refer to Pull-up/Pull-down Driver Characteristics for VOHPU.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 294/300 Output Driver and Termination Register Temperature and Voltage Sensitivity Symbol Parameter Min Max Unit dRONdT RON temperature sensitivity 0 0.75 %/˚C dRONdV RON voltage sensitivity 0 0.20 %/mV dVOHdT VOH temperature sensitivity 0 0.75 %/˚C dVOHdV VOH voltage sensitivity 0 0.35 %/mV dRTTdT RTT temperature sensitivity 0 0.75 %/˚C dRTTdV RTT voltage sensitivity 0 0.20 %/mV AC and DC Operating Conditions - LPDDR4 Recommended DC Operating Conditions Operation or timing that is not specified is illegal. To ensure proper operation, the de- vice must be initialized properly. Recommended DC Operating Conditions Symbol Min Typ Max DRAM Unit Note VDD1 1.7 1.8 1.95 Core 1 power V 1, 2 VDD2 1.06 1.1 1.17 Core 2 power/Input buffer power V 1, 2, 3 VDDQ 1.06 1.1 1.17 I/O buffer power V 2, 3 Note: 1. VDD1 uses significantly less power than VDD2. 2. The voltage range is for DC voltage only. DC voltage is the voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz at the DRAM package ball. 3. The voltage noise tolerance from DC to 20 MHz exceeding a peak -to-peak tolerance of 45mV at the DRAM ball is not included in the TdIVW.

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 295/300 Output Slew Rate and Overshoot/Undershoot specifications - LPDDR4 Single-Ended Output Slew Rate Note 1-5 applies to entire table Parameter Symbol Value Units Min Max Single-ended output slew rate (VOH = VDDQ/3) SRQse 3.5 9.0 V/ns Output slew rate matching ratio (rise to fall) – 0.8 1.2 – Note: 1. SR = Slew rate; Q = Query output; se = Single-ended signal 2. Measured with output reference load. 2. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process 3. variation. 4. The output slew rate for falling and rising edges is defined and measured between VOL(AC) = 0.2 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC). 5. Slew rates are measured under average SSO conditions with 50% of the DQ signals per data byte switching. Single-Ended Output Slew Rate Definition

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 296/300 Differential Output Slew Rate Differential Output Slew Rate Note 1-4 applies to entire table Parameter Symbol Value Units Min Max Differential output slew rate (VOH = VDDQ/3) SRQdiff 7 18 V/ns Note: 1. SR = Slew rate; Q = Query output; se = Differential signal 2. Measured with output reference load. 3. The output slew rate for falling and rising edges is defined and measured between VOL(AC) = –0.8 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC). 4. Slew rates are measured under average SSO conditions with 50% of the DQ signals per data byte switching. Differential Output Slew Rate Definition

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 297/300 LVSTL I/O System - LPDDR4 LVSTL I/O cells are comprised of a driver pull-up and pull-down and a terminator. LVSTL I/O Cell To ensure that the target impedance is achieved, calibrate the LVSTL I/O cell as following example: 1. Calibrate the pull-down device against a 240 ohm resistor to VDDQ via the ZQ pin.

Set strength control to minimum setting
Increase drive strength until comparator detects data bit is less than VDDQ/3
NMOS pull-down device is calibrated to 120 ohms 2. Calibrate the pull-up device against the calibrated pull-down device.
Set VOH target and NMOS controller ODT replica via MRS (VOH can be automatically controlled by ODT MRS)
Set strength control to minimum setting
Increase drive strength until comparator detects data bit is greater than VOH target
NMOS pull-up device is calibrated to VOH target Pull-Up Calibration

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 298/300 PACKING DIMENSIONS 200-BALL (10x14.5 mm) Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max D1 8.80 BSC 0.346 BSC E1 13.65 BSC 0.537 BSC e1 0.80 BSC 0.031 BSC e2 0.65 BSC 0.026 BSC Controlling dimension: Millimeter. (Revision date: Sep 19 2022) D side Pin#1 index "A" E 1 E Pin#1 index Detail : "A" ob 1 2 A solder ball seating plane AA

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 299/300

Revision History

0.1 2020/09/29 Original 1.0 2022/09/12 1. Delete Preliminary 2. Correct Ordering Information table 1.1 2023/04/18 Add the specification of LPDDR4 1.2 2023/05/18 1. Modify package code to BY from product ID 2. Modify packing dimension to 200-BALL (10x14.5x1.0 mm) 3. Remove the speed grade of 4266 Mbps

Elite Semiconductor Microelectronics Technology Inc Publication Date: May. 2023 Revision: 1.2 300/300 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyright s or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, o r loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.

Product Information

M56Z8G32256A specifications and overview.

Summary

32M x 32 Bit x 8 Banks May. 2023 - Revision: 1.2

Description

32M x 32 Bit x 8 Banks May. 2023 - Revision: 1.2

Source title M56Z8G32256A Datasheet(PDF) - Elite Semiconductor Memory Technology Inc.

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