M54HCT138_04 STMICROELECTRONICS | Alldatasheet

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I HIGH SPEED: tPD = 16ns (TYP .) at VCC = 4.5V I LOW POWER DISSIPATION: I CC = 4µA(MAX.) at TA=25°C I COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.) VIL = 0.8V (MAX) I SYMMETRICAL OUTPUT IMPEDANCE: OH | = IOL = 4mA (MIN) I BALANCED PROPAGATION DELAYS: t PLH ≅ tPHL I PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 138

I DEVICE FULLY COMPLIANT WITH SCC-9205-022

DESCRIPTION

The M54HCT138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C 2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M54HCT138 RAD HARD 3 TO 8 LINE DECODER (INVERTING) PIN CONNECTION ORDER CODES PACKAGE FM EM DILC M54HC138D M54HC138D1 FPC M54HC138K M54HC138K1 Rev. 1 DILC-16 FPC-16

Figure 1: IEC Logic Symbols Figure 2: Input And Output Equivalent Circuit Table 1: Pin Description Table 2: Truth Table X : Don’t Care PIN N° SYMBOL NAME AND FUNCTION 1, 2, 3 A, B, C Address Inputs 4, 5 G2A , G2B Enable Inputs

6 G1 Enable Input

9, 10, 11, 12, 13, 14, 15, Y0 to Y7 Data Outputs

8 GND Ground (0V)

16 V CC Positive Supply Voltage

G2B G2A G 1 CBA Y 0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 XXLXXXHHHHHHHH XHXXXX HHHHHHHH HXXXXX HHHHHHHH L LHL L L LHHHHHHH L LHL LHHLHHHHHH L LHLHLHHLHHHHH L LHLHHHHHLHHHH L LHHL LHHHHLHHH L LHHLHHHHHHLHH L LHHHLHHHHHHLH L LHHHHHHHHHHHL

Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays Table 3: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Table 4: Recommended Operating Conditions Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7 V VI DC Input Voltage -0.5 to V CC + 0.5 V VO DC Output Voltage -0.5 to V CC + 0.5 V IIK DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA ICC or IGND DC V CC or Ground Current ± 50 mA PD Power Dissipation 300 mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature (10 sec) 265 °C Symbol Parameter Value Unit VCC Supply Voltage 4.5 to 5.5 V VI Input Voltage 0 to V CC V VO Output Voltage 0 to V CC V Top Operating Temperature -55 to 125 °C tr, tf Input Rise and Fall Time (VCC = 4.5 to 5.5V) 0 to 500 ns

Table 5: DC Specifications Table 6: AC Electrical Characteristics (CL = 50 pF, Input tr = tf = 6ns) Table 7: Capacitive Characteristics 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC Symbol Parameter Test Condition Value UnitVCC (V) TA = 25°C -40 to 85°C -55 to 125°C VIH High Level Input Voltage 4.5 to 5.5 2.0 2.0 2.0 V VIL Low Level Input Voltage 4.5 to 5.5 0.8 0.8 0.8 V VOH High Level Output Voltage 4.5 IO =-20 µA 4.4 4.5 4.4 4.4 VOL Low Level Output Voltage 4.5 IO =20 µA 0.0 0.1 0.1 0.1 II Input Leakage Current 5.5 VI = VCC or GND ± 0.1 ± 1 ± 1 µA ICC Quiescent Supply Current 5.5 VI = VCC or GND 44 0 8 0 µA ∆ ICC Additional Worst Case Supply Current

5.5 Per Input pin

V I = 0.5V or VI = 2.4V Other Inputs at VCC or GND IO = 0 2.0 2.9 3.0 mA Symbol Parameter Test Condition Value UnitVCC (V) TA = 25°C -40 to 85°C -55 to 125°C tTLH tTHL Output Transition Time 4.5 8 15 19 22 ns tPLH tPHL Propagation Delay Time (A, B, C - Y) 4 . 5 1 73 0 3 8 4 5n s tPLH tPHL Propagation Delay Time (G1 - Y) 4 . 5 1 63 0 3 8 4 5n s tPLH tPHL Propagation Delay Time (G2 - Y) 4 . 5 1 93 0 3 8 4 5n s Symbol Parameter Test Condition Value UnitVCC (V) TA = 25°C -40 to 85°C -55 to 125°C C IN Input Capacitance 51 0 1 0 1 0 p F C PD Power Dissipation Capacitance (note 52 pF

Figure 6: WAVEFORM - PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle)

DIM. mm. inch A 2.1 2.71 0.083 0.107 a1 3.00 3.70 0.118 0.146 B 1.82 2.39 0.072 0.094 e 2.54 0.100 I 3.83 0.151 K 10.90 12.1 0.429 0.476 L 1.14 1.5 0.045 0.059 DILC-16 MECHANICAL DATA 0056437F

DIM. mm. inch C 1.49 1.95 0.059 0.077 F 1.27 0.050 H 6.0 0.237 L 18.75 22.0 0.738 0.867 N 4.31 0.170 FPC-16 MECHANICAL DATA 0016030E 1 8 F G D H A B M C N H E L

Table 8: Revision History Date Revision Description of Changes 16-Jun-2004 1 First Release

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