M53D256328A-2F

Elite Semiconductor Mem...

Internal pipelined double-data-rate architecture, two data

Manufacturer: Elite Semiconductor Mem...

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Technical content

Features

 JEDEC Standard  Internal pipelined double-data-rate architecture, two data access per clock cycle  Bi-directional data strobe (DQS)  No DLL; CLK to DQS is not synchronized.  Differential clock inputs (CLK and CLK )  Four bank operation  CAS Latency : 3  Burst Type : Sequential and Interleave  Burst Length : 2, 4, 8, 16  Special function support - PASR (Partial Array Self Refresh) - Internal TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength)  All inputs except data & DM are sampled at the rising edge of the system clock(CLK)  DQS is edge-aligned with data for READ; center-aligned with data for WRITE  Data mask (DM) for write masking only  VDD/VDDQ = 1.7V ~ 1.95V  Auto & Self refresh  15.6us refresh interval (64ms refresh period, 4K cycle)  LVCMOS-compatible inputs

Ordering Information

Product ID Max Freq. V DD Package Comments M53D256328A -5BG2F 200MHz M53D256328A -6BG2F 166MHz M53D256328A -7.5BG2F 133MHz 1.8V 144 ball FBGA Pb-free Functional Block Diagram Bank A Command Decoder Bank D Latch Circuit Bank B Bank C

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 2/47 BALL CONFIGURATION (TOP VIEW) (BGA144, 12mmX12mmX1.4m Body, 0.8mm Ball Pitch) DQS0 VSS Thermal DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ21 DQ22 CAS CS RAS DM0 VDDQ DQ5 VDDQ DQ16 DQ18 DM2 DQ20 DQ23 WE NC NC VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD BA0 NC DQ3 VDDQ VSSQ VSS VSSQ VSS BA1 23456789 VSSQ VSSQ VSSQ VSSQ DQ2 DQ1 VSSQ VSSQ VSS A10/AP DQ0 VDDQ VDD VSS VSS VDD A11 DQ31 VDDQ VDD VSS DQ29 DQ30 VSSQ VSSQ NC VSS VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS VDD VSS Thermal VSS Thermal VSS Thermal VSS Thermal DQ28 VDDQ VSSQ VSS VSS NC VSSQ NC VSSQ VDD VDD CLK DM3 VDDQ DQ26 VDDQ CKE CLK DQS3 DQ27 DQ25 DQ24 NC NC NC DQ8 VDDQ NC DQ15 DQ13 DM1 DQ11 DQ9 NC DQ14 DQ12 DQS1 DQ10 VSSQ VSSQ VSSQ VSSQ VSSQ 11 12 VDDQ VDDQ VDDQ B C D E F G H J K L M N Ball Description Ball Name Function Ball Name Function A0~A11, BA0~BA1 Address inputs - Row address A0~A11 - Column address A0~A8 A10/AP : AUTO Precharge BA0~BA1 : Bank selects (4 Banks) DM0~DM3 DM is an input mask signal for write data. DM0 corresponds to the data on DQ0~DQ7; DM1 correspond to the data on DQ8~DQ15; DM2 correspond to the data on DQ16~DQ23; DM3 correspond to the data on DQ24~DQ31. DQ0~DQ31 Data-in/Data-out CLK, CLK Clock input RAS Row address strobe CKE Clock enable CAS Column address strobe CS Chip select WE Write enable V DDQ Supply Voltage for DQ VSS Ground V SSQ Ground for DQ VDD Power NC No connection DQS0~DQS3 Bi-directional Data Strobe. DQS0 corresponds to the data on DQ0~DQ7; DQS1 correspond to the data on DQ8~DQ15; DQS2 correspond to the data on DQ16~DQ23; DQS3 correspond to the data on DQ24~DQ31.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 3/47 Absolute Maximum Rating Parameter Symbol Value Unit Voltage on any pin relative to VSS V IN, VOUT -0.5 ~ 2.7 V Voltage on VDD supply relative to VSS V DD -0.5 ~ 2.7 V Voltage on VDDQ supply relative to VSS V DDQ -0.5 ~ 2.7 V Operating ambient temperature T A 0 ~ +70 C° Storage temperature T STG -55 ~ +150 C° Power dissipation P D 1.0 W Short circuit current I OS 50 mA Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operation Condition & Specifications DC Operation Condition Recommended operating conditions (Voltage reference to VSS = 0V) Parameter Symbol Min Max Unit Note Supply voltage V DD 1.7 1.95 V I/O Supply voltage V DDQ 1.7 1.95 V Input logic high voltage (for Address and Command) V IH (DC) 0.8 x V DDQ VDDQ + 0.3 V Input logic low voltage (for Address and Command) V IL (DC) -0.3 0.2 x V DDQ V Input logic high voltage (for DQ, DM, DQS) V IHD (DC) 0.7 x V DDQ VDDQ + 0.3 V Input logic low voltage (for DQ, DM, DQS) V ILD (DC) -0.3 0.3 x V DDQ V Output logic high voltage V OH (DC) 0.9 x V DDQ - V I OH = -0.1mA Output logic low voltage V OL (DC) - 0.1 x V DDQ V I OL = 0.1mA Input Voltage Level, CLK and CLK inputs VIN (DC) -0.3 V DDQ + 0.3 V Input Differential Voltage, CLK and CLK inputs VID (DC) 0.4 x VDDQ V DDQ + 0.6 V 1 Input leakage current I I -2 2 μA Output leakage current I OZ -5 5 μA Note: 1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 4/47 DC Characteristics Recommended operating condition (Voltage reference to VSS = 0V) Version Parameter Symbol Test Condition -5 -6 -7.5 Unit Operating Current (One Bank Active) IDD0 tRC= tRC (min); tCK = tCK (min); CKE = HIGH; CS = HIGH between valid commands; address inputs are SWITCHING; data input signals are STABLE 95 85 80 mA IDD2P All banks idle, CKE = LOW; CS = HIGH, tCK = tCK (min); address & control inputs are SWITCHING; data input signals are STABLE 600 μAPrecharge Standby Current in p o w e r - d o w n mode IDD2PS All banks idle, CKE = LOW; CS = HIGH, CLK = LOW, CLK = HIGH; address & control inputs are SWITCHING; data input signals are STABLE 600 μA IDD2N All banks idle, CKE = HIGH; CS = HIGH, tCK = tCK (min); address & control inputs are SWITCHING; data input signals are STABLE 12 11 10 mA Precharge Standby Current in non power-down mode IDD2NS All banks idle, CKE = HIGH; CS = HIGH, CLK = LOW, CLK = HIGH; address & control inputs are SWITCHING; data input signals are STABLE 4 mA IDD3P One bank active, CKE = LOW; C S= H I G H , tCK = tCK (min); address & control inputs are SWITCHING; data input signals are STABLE 4 mA Active Standby Current in power-down mode IDD3PS One bank active, CKE = LOW; CS = HIGH, CLK = LOW, CLK = HIGH; address & control inputs are SWITCHING; data input signals are STABLE 4 mA IDD3N One bank active, CKE = HIGH, CS = HIGH, tCK = tCK (min); address & control inputs are SWITCHING; data input signals are STABLE 40 35 30 mAActive Standby Current in non power-down mode (One Bank Active) IDD3NS One bank active, CKE = HIGH; CS = HIGH, CLK= LOW, CLK = HIGH; address & control inputs are SWITCHING; data input signals are STABLE 4 mA IDD4R One bank active; BL=4; CL=3; tCK = tCK (min); continuous read bursts; IOUT = 0 mA; address inputs are SWITCHING; 50% data changing each burst 140 130 110 mA Operating Current (Burst Mode) IDD4W One bank active; BL=4; tCK = tCK (min); continuous write bursts; IOUT = 0 mA; address inputs are SWITCHING; 50% data changing each burst 120 115 100 mA IDD5 tRFC= tRFC(min) 100 100 100 mA Auto Refresh Current IDD5A Burst refresh; tCK = tCK (min); CKE = HIGH; address inputs are SWITCHING; data input signals are STABLE tRFC= tREFI 12 12 12 mA

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 5/47 TCSR range 45 75 C° Full array 650 700 μA 1/2 array 600 650 μA 1/4 array 550 600 μA 1/8 array 500 550 μA Self Refresh Current IDD6 CKE = LOW, CLK = LOW, CLK = HIGH; EMRS set to all 0’s; address & control & data bus inputs are STABLE 1/16 array 450 500 μA Deep Power Down Current IDD8 address & control & data inputs are STABLE 10 μA Note: 1. Input slew rate is 1V/ns. 2 . I DD specifications are tested after the device is properly initialized. 3. Definitions for I DD: LOW is defined as V IN ≤ 0.1 * V DDQ; H I G H i s d e f i n e d a s V IN ≥ 0.9 * V DDQ; S T A B L E i s d e f i n e d a s i n p u t s s t a b l e a t a H I G H o r L O W l e v e l ; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once p e r t w o c l o c k c y c l e s ; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. AC Operation Conditions & Timing Specification AC Operation Conditions Parameter Symbol Min Max Unit Note Input High (Logic 1) Voltage, DQ, DQS and DM signals V IHD(AC) 0.8 x V DDQ V DDQ+0.3 V Input Low (Logic 0) Voltage, DQ, DQS and DM signals V ILD(AC) -0.3 0.2 x V DDQ V Input Differential Voltage, CLK and CLK inputs VID(AC) 0.6 x V DDQ V DDQ+0.6 V 1 Input Crossing Point Voltage, CLK and CLK inputs VIX(AC) 0.4 x V DDQ 0.6 x V DDQ V 2 Note: 1. VID is the magnitude of the difference between the input level on CLK and the input on CLK . 2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must tra ck variations in the DC level of the same. Input / Output Capacitance (VDD = 1.8V, VDDQ =1.8V, TA = 25 C° , f = 1MHz) Parameter Symbol Min Max Unit Input capacitance (A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE ) CIN1 2 5 pF Input capacitance (CLK, CLK ) CIN2 4 7 pF Data & DQS input/output capacitance C OUT 2 7 pF Input capacitance (DM) C IN3 2 6 pF

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 6/47 AC Operating Test Conditions (VDD = 1.7V~ 1.95V) Parameter Value Unit Input signal minimum slew rate 1.0 V/ns Input levels (VIH/VIL) 0.8 x V DDQ / 0.2 x VDDQ V Input timing measurement reference level 0.5 x V DDQ V Output timing measurement reference level 0.5 x V DDQ V AC Timing Parameter & Specifications (VDD = 1.7V~1.95V, VDDQ=1.7V~1.95V) -5 -6 -7.5 Parameter Symbol min max min max min max Unit Note Clock Period t CK 5 100 6 100 7.5 100 ns 12 Access time from CLK/ CLK tAC 2 5 2 5.5 2 6 ns Data strobe edge to clock edge t DQSCK 2 5 2 5.5 2 6 ns Data-in and DM setup time (to DQS) (fast slew rate) tDS 0.7 0.7 0.8 ns 13,14 ,15 Data-in and DM hold time (to DQS) (fast slew rate) t DH 0.7 0.7 0.8 ns 13,14 ,15 Data-in and DM setup time (to DQS) (slow slew rate) tDS 0.8 0.8 0.9 ns 13,14 ,16 Data-in and DM hold time (to DQS) (slow slew rate) tDH 0.8 0.8 0.9 ns 13,14 ,16 DQ and DM input pulse width (for each input) t DIPW 1.8 1.8 1.8 ns 17 Input setup time (fast slew rate) t IS 0.9 1.1 1.3 ns 15,18 Input hold time (fast slew rate) t IH 0.9 1.1 1.3 ns 15,18 Input setup time (slow slew rate) t IS 1.1 1.3 1.5 ns 16,18 Input hold time (slow slew rate) t IH 1.1 1.3 1.5 ns 16,18 Control and Address input pulse width t IPW 2.3 2.7 3.0 ns 17 DQS input high pulse width t DQSH 0.4 0.4 0.4 tCK DQS input low pulse width t DQSL 0.4 0.4 0.4 tCK DQS falling edge to CLK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CLK rising-hold time tDSH 0.2 0.2 0.2 tCK Data strobe edge to output data edge t DQSQ 0.4 0.5 0.6 ns 20

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 7/47 AC Timing Parameter & Specifications-continued -5 -6 -7.5 Parameter Symbol min max min max min max Unit Note Data-out high-impedance window from CLK/ CLK tHZ 5 5.5 6 ns 19 Data-out low-impedance window from CLK/ CLK tLZ 1.0 1.0 1.0 ns 19 Half Clock Period tHP tCLmin or tCHmin tCLmin or tCHmin tCLmin or tCHmin ns 10,11 DQ-DQS output hold time tQH tHP - tQHS tHP - tQHS tHP - tQHS ns 11 Data hold skew factor t QHS 0.5 0.65 0.75 ns 11 ACTIVE to PRECHARGE command t RAS 40 70K 42 70K 45 70K ns Row Cycle Time t RC 55 60 67.5 ns AUTO REFRESH Row Cycle Time t RFC 72 72 72 ns ACTIVE to READ,WRITE delay t RCD 15 18 22.5 ns PRECHARGE command period t RP 15 18 22.5 ns Minimum tCKE High/Low time t CKE 2 2 2 t CK ACTIVE bank A to ACTIVE bank B command tRRD 10 12 15 ns WRITE recovery time t WR 15 15 15 ns Write data in to READ command delay t WTR 1 1 1 t CK Col. Address to Col. Address delay t CCD 1 1 1 t CK Refresh period t REF 64 64 64 ms Average periodic refresh interval t REFI 15.6 15.6 15.6 μs 9 Write preamble t WPRE 0.25 0.25 0.25 t CK Clock to DQS write preamble setup time tWPRES 0 0 0 ns 21 Load Mode Register / Extended Mode register cycle time tMRD 2 2 2 t CK Exit self refresh to first valid command t XSR 200 200 200 ns 24 Exit power-down mode to first valid command tXP 25 25 25 ns 25 Auto precharge write recovery + Precharge time tDAL (tWR/tCK) (tRP/tCK) (tWR/tCK) (tRP/tCK) (tWR/tCK) (tRP/tCK) ns 26 Notes: 1. All voltages referenced to V SS. 2. All parameters assume pr oper device initialization. 3. Tests for AC timing may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage and temperature range specified.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 8/47 4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). For the half strength driver with a nominal 10 pF load parameters tAC and tQH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by design / characterization. Use of IBIS or other simulation tools for system design validation is suggested. I/O Z0 =5 0o h m s 20 pFTiming Reference Load 5. The CLK/ CLK input reference voltage level (for timing referenced to CLK/ CLK ) is the point at which CLK and CLK cross; the input reference voltage level for signals other than CLK/ CLK is V DDQ/2. 6. The timing reference voltage level is V DDQ/2. 7. AC and DC input and output voltage levels are defined in AC/DC operation conditions. 8. A CLK/ CLK differential slew rate of 2.0 V/ ns is assumed for all parameters. 9. A maximum of eight consecutive AUTO REFRESH commands (with t RFC(min)) can be posted to any given Mobile DDR, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 x tREFI. 10. Refer to the smaller of the actual clock low time and the actual clock high time as provided to the device. 11. t QH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH). tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 12. The only time that the clock frequency is allowed to change is during power-down or self-refresh modes. 13. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to VIL(AC) for falling input signals. 14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 15. Input slew rate ≥ 1.0 V/ns. 16. Input slew rate ≥ 0.5 V/ns and < 1.0 V/ns. 17. These parameters guarantee device timing but th ey are not necessarily tested on each device. 18. The transition time for address and command inputs is measured between V IH and VIL. 19. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 20. t DQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 21. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before the corresponding CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 22. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 23. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled). 24. There must be at least two clock pulses during the t XSR period. 25. There must be at least one clock pulse during the t XP period. 26. Minimum 3 clocks of t DAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and minimum 1 clock for tRP. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next higher integer.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 9/47 Command Truth Table COMMAND CKEn-1 CKEn CS RAS CAS WE DM BA0,1 A10/AP A11, A9~A0 Note Register Extended MRS H X L L L L X OP CODE 1,2 Register Mode Register Set H X L L L L X OP CODE 1,2 Auto Refresh H 3 Entry H L L L L H X X L H H H 3 Refresh Self Refresh Exit L H H X X X XX Bank Active & Row Addr. H X L L H H X V Row Address Auto Precharge Disable L 4 Read & Column Address Auto Precharge Enable H X L H L H X V H Column Address (A0~A8) 4 Auto Precharge Disable L 4,8Write & Column Address Auto Precharge Enable H X L H L L V V H Column Address (A0~A8) 4,6,8 Entry H L L H H L X H X X X Deep Power Down Mode Exit L H L H H H X X Burst Terminate H X L H H L X X 7 Bank Selection V L Precharge All Banks H X L L H L X X H X H X X X Entry H L L H H H X H X X X Active Power Down Mode Exit L H L H H H X X H X X X Entry H L L H H H X H X X X Precharge Power Down Mode Exit L H L H H H X X Deselect (NOP) H X X X No Operation (NOP) H X L H H H XX (V = Valid, X = Don’t Care, H = Logic High, L = Logic Low) Notes: 1. OP Code: Operand Code. A0~A11 & BA0~BA1: Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by “Auto”.. Auto/self refresh can be issued only at all banks precharge state. 4. BA0~BA1: Bank select addresses. If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected. If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected. If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected. 5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. New row active of the associated bank can be issued at t RP after end of burst. 7. Burst Terminate command is valid at every burst length. 8. DM and Data-in are sampled at the rising and falling edges of the DQS. Data-in byte are masked if the corresponding and coincident DM is “High”. (Write DM latency is 0).

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 10/47 Basic Functionality Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a high state (all other inputs may be undefined.) - Apply V DD before or at the same time as VDDQ. 2. Start clock and maintain stable condition for a minimum. 3. The minimum of 200us after stable power and clock (CLK, CLK ), apply NOP. 4. Issue precharge commands for all banks of the device. 5. Issue 2 or more auto-refresh commands. 6. Issue mode register set command to initialize the mode register. 7. Issue extended mode register set command to set PASR and DS. 0123456789 CLOCK CKE CS RAS CAS ADDR WE DQ DQM A10/AP t RP Key Key BA1 BA0 High-Z Precharge (All Banks) Auto Refresh Auto Refresh Mode Register Set Extended Mode Register Set : Don't care t RFC t RFC High level is necessary High level is necessary 10 11 12 13 14 15 16 17 18 19 20 RA BS BS RA Row Active t MRD t MRD

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 11/47 Mode Register Definition Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of Mobile DDR SDRAM. It programs CAS latency, addressing mode, burst length and various vend or specific options to make Mobile DD R SDRAM useful for variety of different applications. The default value of the register is not defined, therefore the mode register must be written in the power up seq uence of Mobile DDR SDRAM. The mode regist er is written by asserting low on CS , RAS , CAS , WE and BA0~BA1 (The Mobile DDR SDRAM should be in all bank precharge with CKE already high prio r to writing into the mode r egister). The state of address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0~BA1 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the m ode register. The mode register c ontents can be changed using the same command and clock cycle requirements during operation as lo ng as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7~A11 is used for test mode. A7~A11 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 A11~ A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0* 0* 0* CAS Latency BT Burst Length Mode Register A 3 B u r s t T y p e

0 Sequential

1 Interleave

BA1 BA0 Operating Mode 0 0 0 Reserved 0 0 0 Reserved Reserved 0 0 MRS Cycle 0 0 1 Reserved 0 0 1 2 2 1 0 EMRS Cycle 0 1 0 Reserved 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 16 16 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Reserved Reserved * BA0~BA1 and A11~A7 should stay “0” during MRS cycle

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 12/47 Burst Address Ordering for Burst Length Starting Column Address Burst Length A3 A2 A1 A0 Sequential Mode Interleave Mode 0 0, 1 0, 1 2 1 1, 0 1, 0 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 4 1 1 3, 0, 1, 2 3, 2, 1, 0

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 13/47 Extended Mode Register Set (EMRS) The extended mode register stores for selecting PASR and DS. The extended mode register set must be done before any active command after the power up sequence. The extended mo de register is written by asserting low on CS , RAS , CAS , WE , BA0 and high on BA1 (The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended more register). The state of addr ess pins A0~An in the same cycle as CS , RAS , CAS , WE going low is written in the extended mode register. Refer to the table for specific codes. The extended mode register can be changed by using the same command and clock cycle requirements during operations as long as all banks are in the idle state. Internal Temperature Compensated Self Refresh (TCSR) 1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the device temperature. 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. BA1 BA0 A11 ~ A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 1 0* 0* DS TCSR PASR Extended Mode Register Set * BA0 and A11~ A8 should stay “0” during EMRS cycle ** MSB: most significant bit A2-A0 Self Refresh Coverage

000 Full array

001 1/2 array (BA1 = 0) 010 1 / 4 a r r a y (BA1 = BA0 =0)

011 Reserved

100 Reserved

(BA1 = BA0 = Row Addr MSB** =0) 110 1/16 array (BA1 = BA0 = Row Addr 2 MSB =0) PASR

111 Reserved

000 Full Strength

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 14/47 Precharge The precharge command is used to precharge or close a bank t hat has activated. The precharge command is issued when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank se lect addresses (BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. Burst Selection for Precharge by Bank address bits A10/AP BA1 BA0 Precharge 0 0 0 Bank A Only 0 0 1 Bank B Only 0 1 0 Bank C Only 0 1 1 Bank D Only

1 X X All Banks

NOP & Device Deselect The device should be deselected by deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the control inputs. The Mobile DDR SDRAM is put in NOP mode when CS is actived and by deactivating RAS , CAS and WE . For both Deselect and NOP, the device should finish the current operation when this command is issued.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 15/47 Row Active The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CLK). The Mobile DDR SDRAM has four i ndependent banks, so Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (t RCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation comma nd (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min). Bank Activation Command Cycle ( CAS Latency = 3) Address 01 23 456 Command Bank A Row Addr. Bank A Row. Addr. Bank B Row Addr. Bank A Activate NOP Bank B Activate NOP Bank A Activate RAS-CAS delay ( t RCD ) RAS-RAS delay ( t RRD ) ROW Cycle Time ( t RC ) :D o n ' tC a r e CLK CLK Bank A Col. Addr. Write A with Auto Precharge NOP Read Bank This command is used after the row activate command to initia te the burst read of data. T he read command is initiated by activating CS , RAS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command. Write Bank This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating CS , RAS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 16/47 Essential Functionality for Mobile DDR SDRAM Burst Read Operation Burst Read operation in Mobile DDR SDRAM is in the same manner as the current Mobile DDR SDRA M such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst and burst length. The first out put data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and risi ng edge of Data Strobe (DQS) adopted by Mo bile DDR SDRAM until the burst length is completed. <Burst Length = 4, CAS Latency = 3> 01 234 5678 COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP CLK CLK CAS Latency=3 DQS DQ's Dout0 Dout1 Dout2 Dout3 tRPRE tDQSCK tRPST tAC tDQSCK tDQSQ(max) tQH tQHtQHS Burst Write Operation The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst w rite cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is comp leted. When the burst has been finished, a ny additional data supplied to the DQ pins will be ignored. <Burst Length = 4> 01 234 5678 COMMAND DQS DQ's WRITEA NOP NOP NOP NOP NOP PREB t DQSS( max) t WR Din0 Din1 Din2 Din3 t WPRES CLK CLK NOP Din0 Din1 Din2 Din3 DQS DQ's t DQSS( min) Din0 Din1 Din2 Din3 t WPRES Din0 Din1 Din2 Din3 t WR t DS t DH WRITEB

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 17/47 Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining addresses are ove rridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 clock. <Burst Length = 4, CAS Latency = 3> 01 234 5678 COMMAND DQS DQ's READ A NOP NOP NOP NOP NOP NOP NOP Dout A 0 READ B Dout A 1 Dout B 2 Dout B 3Dout B 0 Dout B 1 CLK CLK t CCD(min) t RPRE t DQSCK Hi-Z Hi-Z t RPST Read Interrupted by a Write & Burst Terminate To interrupt a burst read with a write co mmand, Burst Terminate command must be asse rted to avoid data contention on the I/O bus by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the write operation, Burt Terminate command must be applied at least RU(CL) clocks ［RU means round up to the nearest integer］ before the Write command. <Burst Length = 4, CAS Latency = 3> 01 234 5678 COMMAND DQS DQ's READ NOP NOP NOP NOP NOP Dout 0 Burst Terminate Din 0Dout 1 Din 1 Din 2 Din 3 CLK CLK NOP WRITE t DQSCK t RPRE t RPST t AC t WPRE t WPRES t DQSS t WPST The following functionality establishes how a Write command may interrupt a Read burst. 1. For Write commands interrupting a Read burst, a Burst Terminat e command is required to stop the read burst and tristate the DQ bus prior to valid input write data. Once the Burst Term inate command has been issued, the minimum delay to a Write command = RU (CL) [CL is the CAS Latency and RU means round up to the nearest integer]. 2. It is illegal for a Write and Burst Terminate command to interrupt a Read with auto precharge command.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 18/47 Read Interrupted by a Precharge A Burst Read operation can be interrupted by precharge of the sa me bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency. <Burst Length = 8, CAS Latency = 3> 01 234 5678 COMMAND DQS DQ's READ NOP NOP NOP NOP NOP NOP Dout 0 Precharge Dout 1 1t CK NOP Interrupted by precharge CLK CLK Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7 t RPRE t DQSCK t AC When a burst Read command is issued to a Mobile DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is complete. The following functionality dete rmines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interr upting a Read burst, the Precharge command may be given on the rising clock edge which is CL clock cycles befor e the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS precharge time). 2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge which is CL clock cycles before the last data fr om the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank after tRP. 3. For a Read with auto precharge command, a new Bank Acti vate command may be issued to the same bank after t RP where tRP begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During Read with auto precharge, the init iation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above. 4. For all cases above, t RP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command and a new Bank Activate command to the same bank equals t RP / t CK (where tCK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. In all cases, a Precharge operati on cannot be initiated unless t RAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with auto precharge commands where t RAS(min) must still be satisfied such that a Read with auto precharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 19/47 Write Interrupted by a Write A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the inte rval that separates the commands must be at least one clock cycle. When the previous burst is inte rrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. <Burst Length = 4> 01 234 5678 COMMAND DQS DQ's NOP NOP NOP NO P NOP NOP Di n A 0 WRITE A Di n A 1 Din B 0 Din B 1 Di n B 2 Di n B 3 1t CK NOP WRI TE B CLK CLK t CCD

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 20/47 Write Interrupted by a Read & DM A burst write can be interrupted by a read command of any bank. T he DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, an y residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is required to avoid the data contention Mobile DDR SDRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of t hat of write command. <Burst Length = 8, CAS Latency = 3> 01 234 5678 COMMAND DQS DQ's DQS DQ's NOP NOP NOP NOP READ NOP t DQSS(max ) Dina0 Dina1 WRITE Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 t DQSS(min) DM Dout0 Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 CLK CLK DM NOP NOP Hi-Z Hi-Z t WPRES t WTR Hi-Z Hi-Z t WTR t WPRES Dout1 Dout0 Dout1 The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the memory. 1. For Read commands interrupting a Write burst, the minimum Wr ite to Read command delay is 2 clock cycles. The case where the Write to Read delay is 1 clock cycle is disallowed. 2. For read commands interrupting a Write burst, the DM pin must be used to mask t he input data words which immediately precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation. 3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be releas ed by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the Mobile DDR SDRAM drives them during a read operation. 4. If input Write data is masked by the Read command, the DQS inputs are ignored by the Mobile DDR SDRAM. 5. It is illegal for a Read command interru pt a Write with auto precharge command.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 21/47 Write Interrupted by a Precharge & DM A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM. <Burst Length = 8> 01 234 5678 COMMAND DQS DQ's DQS DQ's NOP NOP NOP NOP NOP t DQSS(max ) Dina0 Dina1 WRITE A Dina2 Dina3 t DQSS(min) DM Dinb0 Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 Dinb1 CLK CLK DM PrechargeA Hi-Z Hi-Z t WPRES t WR Hi-Z Hi-Z t WR NOP WRITE B t DQSS(max ) t WPRES t DQSS(min) t WPRESt WPRES Precharge timing for Write operations in Mobile DDR SDRAM requir es enough time to allow “Write recovery” which is the time required by a Mobile DDR SDRAM core to properly store a full “0” or “1” level before a Precharge operation. For Mobile DDR SDRAM, a timing parameter, t WR, is used to indicate the required of time bet ween the last valid writ e operation and a Precharge command to the same bank. tWR starts on the rising clock edge after the last possible DQS edge t hat strobed in the last valid and ends on the rising clock e dge that strobes in the precharge command. 1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for wri te recovery is defined by tWR. 2. When a precharge command interrupts a Wr ite burst operation, the data mask pin, DM, is used to mask input data during the time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. 3. For a Write with auto precharge command, a new Bank Activate command may be issued to the same bank after t WR + t RP where tWR + tRP starts on the falling DQS edge that stro bed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate commands. During write with auto precharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above. 4. In all cases, a Precharge operation cannot be initiated unless t RAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Write wi th auto precharge commands where t RAS(min) must still be satisfied su ch that a Write with auto precharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 22/47 Burst Terminate The Burst Terminate command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock (CLK). The Burst Terminate command has the fewest restriction making it the easiest method to use when terminating a burst read operation before it has been completed. Wh en the Burst Terminate command is issued during a burst read cycle, the pair of data and DQS (Data Strobe) go to a high impedance st ate after a delay which is equal to the CAS latency set in the mode register. Th e Burst Terminate command, however, is not supported during a write burst operation. <Burst Length = 4, CAS Latency = 3 > 01 234 5678 COMMAND READ A NOP NOP NOP NOP NOP NOP NOPBurst Terminate CLK CLK DQS DQ's Dout 0 Dout 1 Hi-Z Hi-Z The burst read ends after a deley equal to the CAS lantency. The Burst Terminate command is a mandatory feature for Mobile DDR SDRAM. The following functionality is required. 1. The BST command may only be issued on t he rising edge of the input clock, CLK. 2. BST is only a valid command during Read burst. 3. BST during a Write burst is undefined and shall not be used. 4. BST applies to all burst lengths. 5. BST is an undefined command during Read with auto precharge and shall not be used. 6. When terminating a burst Read command, the BST command must be issued L BST (“BST Latency”) clock cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations. 7. When the burst terminates, the DQ and DQS pins are tristated. The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 23/47 DM masking The Mobile DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the data mask is activated (DM high) during write operation, Mobile DDR SDRAM does not accept the corresponding data. (DM to data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe. <Burst Length = 8> 01 234 5678 COMMAND WRITE NOP NOP NOP NOP NOP NOP NOP CLK CLK NOP DQS DQ's t DQSS DM Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 t WPRES Hi-Z Hi-Z mas k ed b y D M =H

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 24/47 Read with Auto Precharge If a read with auto precharge command is in itiated, the Mobile DDR SDRAM automatic ally enters the precharge operation BL/2 clock later from a read with auto precharge command when t RAS(min) is satisfied. If not, the star t point of precharge operation will be delayed until t RAS(min) is satisfied. Once the prec harge operation has started the bank cannot be reactivated and the new command can not be asserted until the precharge time (tRP) has been satisfied <Burst Length = 4, CAS Latency = 3> 01 234 5678 COMMAND Bank A ACTIVE NOP NOP NOP NOP NOP NOP NOP Read A Auto Precharge CLK CLK DQS DQ's Dout 0 Dout 1 Dout 2 Dout 3 t RP 9 10 NOP NOP Bank can be reactivated at completion of tRP1) Auto-Precharge starts Hi-Z Hi-Z t RAS (min) Note: The row active command of the precharge bank can be issued after tRP from this point. For Same Bank For Different Bank Asserted Command 5 6 7 5 6 7 READ READ + No AP Illegal Illegal Legal Legal Legal READ + AP1 READ + AP Illegal Illegal Legal Legal Legal Active Illegal Illegal Illegal Legal Legal Legal Precharge Legal Legal Illegal Legal Legal Legal Note: 1. AP = Auto Precharge

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 25/47 Write with Auto Precharge If A10 is high when write command is issued, the write with auto precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is complet ed. The internal precharge begi ns at the rising edge of the CL K with the tWR delay after the last data-in. <Burst Length = 4> 01 234 5678 9 1 0 1 11 2 COMMAND DQS DQ's Bank A ACTIVE NOP NOP NOP NOP NOP NOP NOP DIN 0 DIN 1 Write A Auto Precharge DIN 2 DIN 3 *Bank can be reactivated at completion of t RP t WR t RP Internal precharge start CLK CLK NOP NOPNOP NOP Note: The row active command of the precharge bank can be issued after tRP from this point. For Same Bank For Different Bank Asserted Command 5 6 7 8 9 10 5 6 7 8 9 WRITE WRITE + NO AP WRITE + NO AP Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal WRITE + AP1 WRITE + AP WRITE + AP Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal READ Illegal READ + No AP + DM2 READ + No AP+ DM READ + No AP Illegal Illegal Illegal Illegal Illegal Legal Legal READ + AP Illegal READ + AP+ DM READ + AP+ DM READ + AP Illegal Illegal Illegal Illegal Illegal Legal Legal Active Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal Precharge Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal Note: 1. AP = Auto Precharge 2. DM: Refer to “Write Interrupted by Precharge & DM”

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 26/47 Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of the clock(CLK). All banks must be precharged and idle for t RP(min) before the auto refresh command is applied. No control of the external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle h as completed, all banks will be in the idle state. A delay bet ween the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tRFC(min). A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given Mobile DDR, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 x tREFI. COMMAND CKE = High t RP PRE Auto Refresh CMD t RFC CLK CLK Self Refresh A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock (CLK). Once the self refresh command is in itiated, CKE must be held low to keep the device in self refresh mode. During the sel f refresh operation, all inputs except CKE ar e ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSR. COMMAND CKE t XSR(min) Self Refresh Auto Refresh NOP t IS CLK CLK NOP NOP NOP NOP NOP t IS Note: After self refresh exit, input an auto refresh command immediately.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 27/47 Power Down Power down is entered when CKE is registered Low (no accesses can be in progress). If power down occurs when all banks are idle, this mode is referred to as precharge power-down; if power down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power down deactivates the input and output buffers, excluding CLK, CLK and CKE. In power down mode, CKE Low must be maintained, and all other input signals are “Don’t Care”. The minimum power down duration is specified by tCKE. However, power down duration is limited by the refresh requirements of the device. The power down state is synchronously exited when CKE is registered High (along with a NOP or DESELECT command). A valid command may be applied tXP after exit from power down. COMMAND CKE CLK CLK Precharge Read Enter Precharge power-down mode tIS tIStIStIS tXP Active Exit Precharge power-down mode Enter Active power-down mode Exit Active power-down mode tXPtCKE tCKEtRP Functional Truth Table Truth Table – CKE [Note 1~10] CKE n-1 CKE n Current State COMMAND n ACTION n NOTE L L Power Down X Maintain Power Down L L Self Refresh X Maintain Self Refresh L L Deep Power Down X Maintain Deep Power Down L H Power Down NOP or DESELECT Exit Power Down 5,6,9 L H Self Refresh NOP or DESEL ECT Exit Self Refresh 5,7,10 L H Deep Power Down NOP or DESELECT Exit Deep Power Down 5,8 H L All Banks Idle NOP or DESELECT Precharge Power Down Entry 5 H L Bank(s) Active NOP or DESELECT Active Power Down Entry 5 H L All Banks Idle AUTO REFRESH Self Refresh Entry H L All Banks Idle BURST TERMINATE Enter Deep Power Down H H See the other Truth Tables Notes: 1. CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge. 2. Current state is the st ate of Mobile DDR immediately prior to clock edge n. 3. COMMAND n is the command registered at clock ed ge n, and ACTION n is the result of COMMAND n. 4. All states and sequences not shown are illegal or reserved. 5. DESELECT and NOP are functionally interchangeable. 6. Power Down exit time (t XP) should elapse before a command other than NOP or DESELECT is issued. 7. SELF REFRESH exit time (t XSR) should elapse before a command other than NOP or DESELECT is issued. 8. The Deep Power Down exit procedure must be followed the figure of Deep Power Down Mode Entry & Exit Cycle. 9. The clock must toggle at least once during the t XP period. 10. The clock must toggle at least once during the t XSR time.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 28/47 Truth Table – Current State Bank n Current State CS RAS CAS WE COMMAND / ACTION NOTE Command to Bank n [Note 1~12] H X X X DESELECT (NOP / continue previous operation) Any L H H H No Operation (NOP / continue previous operation) L L H H ACTIVE (select and activate row) L L L H AUTO REFRESH 9 Idle L L L L MODE REGISTER SET 9 L H L H READ (select column & start read burst) L H L L WRITE (select column & start write burst) Row Active L L H L PRECHARGE (deactivate row in bank or banks) 4 L H L H READ (select column & start new read burst) 5 L H L L WRITE (select column & start write burst) 5, 12 L L H L PRECHARGE (truncate re ad burst, start precharge) Read (Auto Precharge Disabled) L H H L BURST TERMINATE 10 L H L H READ (select column & start read burst) 5,11 L H L L WRITE (select column & start new write burst) 5 Write (Auto Precharge Disabled) L L H L PRECHARGE (truncate wr ite burst, start precharge) 11 Command to Bank m [Note 1~3,6, 11~16] H X X X DESELECT (NOP / continue previous operation) Any L H H H No Operation (NOP / c ontinue previous operation) Idle X X X X Any command allowed to bank m L L H H ACTIVE (select and activate row) L H L H READ (select column & start read burst) 16 L H L L WRITE (select column & start write burst) 16 Row Activating, Active, or Precharging L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column & start new read burst) 16 L H L L WRITE (select column & start write burst) 12,16 Read (Auto Precharge disabled) L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column & start read burst) 11,16 L H L L WRITE (select column & start new write burst) 16 Write (Auto Precharge disabled) L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column & start new read burst) 13,16 L H L L WRITE (select column & start write burst) 12,13,16 Read with Auto Precharge L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column & start read burst) 13,16 L H L L WRITE (select column & start new write burst) 13,16 Write with Auto Precharge L L H L PRECHARGE Notes: 1. The table applies when both CKE n-1 and CKE n are HIGH, and after t XSR or tXP has been met if the previous state was Self Refresh or Power Down.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 29/47 2. DESELECT and NOP are functionally interchangeable. 3. All states and sequences not shown are illegal or reserved. 4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging. 5. The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled. 6. Current State Definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: a WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 7. The following states must not be interrupted by a comma nd issued to the same bank. DESELECT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and the part of Command to Bank n, according to the part of Command to Bank m. Precharging: starts with the registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the ‘row active’ state. Read with AP Enabled: starts with the registration of the READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP has been met, the bank will be in the idle state. Write with AP Enabled: starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 8. The following states must not be interrupted by any exec utable command; DESELECT or NOP commands must be applied to each positive clock edge during these states. Refreshing: starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the device will be in an ‘all banks idle’ state. Accessing Mode Register: starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the device will be in an ‘all banks idle’ state. Precharging All: starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. 9. Not bank-specific; requires that all banks are idle and no bursts are in progress. 10. Not bank-specific. BURST TERMINATE affects t he most recent read burst, regardless of bank. 11. Requires appropriate DM masking. 12. A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command must be issued to end the READ prior to asserting a WRITE command. 13. Read with AP enabled and Write with AP enabled: the Read with Auto Precharge enabled or Write with Auto Precharge enabled states can be broken into two parts: the access period and the precharge period. For Read with AP, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all the data in the burst. For Write with AP, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the Read with AP enabled or Write with AP enabled states, ACTIVE, PRECHARGE, READ, and WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands to the other banks may be applied. In either case, all other related limitations apply (e.g. contention between READ data and WRITE data must be avoided). 14. AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle. 15. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 16. READs or WRITEs listed in the Command column includ e READs and WRITEs with Auto Precharge enabled and READs and WRITEs with Auto Precharge disabled.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 30/47 Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3) CKE CS RAS CAS BA0, BA1 ADDR (A0~An) WE DQS DQ 01 234 567891 0 HIGH DM COMMAND A 10 /AP t CK t IS t IH t WPRE t DQSS Qa0 Qa1 Qa2 Qa3 t DQSS t RPST t DQSH t DQSL t WPST Hi-Z Hi-Z READ WRITE CLK CLK t CL t RPRE t AC 11 12 13 t CH Ra Ra CbCa Hi-Z Hi-Z t DQSCK Hi-Z t WPRES Db0 Db1 Db3Db2 Active Hi-Z t DS tDH 10122B32R.B t QH t DQSQ t LZ t HZ t QHS t DSH t DSS t DQSSBAaBAa BAb Note: tHP is lesser of tCL or tCH clock transition collectively when a bank is active.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 31/47 Multi Bank Interleaving READ (@BL=4, CL=3) CKE CS RAS CAS BA0, BA1 WE DQS DQs 01 234 567891 0 HIGH DM COMMAND A 10 /AP ADDR (A0~An) Qb0 Qb1 Qb3Qb2 ACTIVE Ra Rb Ra Qa0 Qa1 Qa3Qa2 ACTIVE READ tRCD READ tRRD t CCD Rb CLK CLK 11 12 13 Ca Cb Hi-Z Hi-Z 10122B32R.B BAa BAb BAa BAb

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 32/47 Multi Bank Interleaving WRITE (@BL=4) CKE CS RAS CAS BA0, BA1 WE DQS DQ 01 234 567891 0 HIGH DM COMMAND A 10 /AP ADDR (A0~An) Db0 Db1 Db3Db2 ACTIVE Ra Rb Ra Ca Cb Da0 Da1 Da3Da2 ACTIVE WRITE tRCD WRITE t RRD tCCD Rb CLK CLK Hi-Z Hi-Z 10122B32R.B BAa BAb BAa BAb

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 33/47 Read with Auto Precharge (@BL=8) CKE CS RAS CAS BA0, BA1 WE DQS(CL=3) DQ(CL=3) 01 234 567891 0 HIGH DM A 10 /AP ADDR (A0~An) Qa4 Qa5 Qa7Qa6 t RP Qa0 Qa1 Qa3Qa2 Ca Auto precharge start Note CLK CLK Ra Ra Hi-Z Hi-Z READ ACTIVECOMMAND 10122B32R.B BAa BAa Note: The row active command of the precharge bank can be issued after tRP from this point.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 34/47 Write with Auto Precharge (@BL=8) CKE CS RAS CAS BA0, BA1 WE DQS DQ 01 234 567891 0 HIGH DM COMMAND A 10 /AP ADDR (A0~An) Da4 Da5 Da7Da6 t RP Da0 Da1 Da3Da2 ACTIVEWRITE Ca Auto precharge start Note1 Ra Ra t WR CLK CLK tDAL 10122B32R.B BAa BAa Note: The row active command of the precharge bank can be issued after tRP from this point.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 35/47 Read Interrupted by Precharge (@BL=8) CKE CS RAS CAS BA0, BA1 WE DQS DQs 01 234 567891 0 HIGH COMMAND A 10 /AP ADDR (A0~An) Qa0 Qa1 READ Ca PRE CHARGE CLK CLK Qa2 Qa3 Qa4 Qa5 DM Hi-Z Hi-Z 2 t CK Valid 10122B32R.B BAa BAa

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 36/47 Read Interrupted by a Read (@BL=8, CL=3) CKE CS RAS CAS BA0, BA1 WE DQS DQs 01 234 567891 0 HIGH DM COMMAND A 10 /AP ADDR (A0~An) Qa0 Qa1 Qb1 Qb0 READ Ca Cb Qb2 Qb3 Qb5Qb4 Qb7Qb6 READ CLK CLK Hi-Z Hi-Z 10122B32R.B BAa BAb

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 37/47 Read Interrupted by a Write & Burst Terminate (@BL=8, CL=3) CKE CS RAS CAS BA0, BA1 WE DQS DQs 01 234 567891 0 HIGH DM COMMAND Qa0 Qa1 READ Db0 Db5Db1 Db4Db3Db2 Db6 Cb Burst Termina te WRITE Db7 CLK CLK A 10 /AP ADDR (A0~An) Ca Hi-Z Hi-Z 10122B32R.B BAa BAb

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 38/47 Write followed by Precharge (@BL=4) CKE CS RAS CAS BA0, BA1 WE DQS DQ 01 234 567891 0 HIGH DM COMMAND A 10 /AP ADDR (A0~An) t WR Da0 Da1 Da3Da2 PRE CHARGEWRITE Ca CLK CLK 10122B32R.B BAa BAa

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 39/47 Write Interrupted by Precharge & DM (@BL=8) CKE CS RAS CAS BA0, BA1 WE DQS DQ 01 234 56789 1 0 HIGH DM COMMAND A 10 /AP ADDR (A0~An) Da0 Da1 Da3Da2 PRE CHARGEWRITE WRITE Ca CLK CLK Cb Da4 Da5 Da6 Da7 Db0 Db1 Db3Db2 Db5Db4 t WR 10122B32R.B BAa BAbBAa

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 40/47 Write Interrupted by a Read (@BL=8, CL=3) CKE CS RAS CAS BA0, BA1 WE DQS DQ 01 234 567891 0 HIGH DM COMMAND t WTR Da0 Da1 Da3Da2 WRITE READ Ca CLK CLK Cb Da5Da4 Qb0 Qb1 Qb3 Qb2 Qb4 Qb5 Maskecd by DM A 10 /AP ADDR (A0~An) Hi-Z Hi-Z 10122B32R.B BAa BAb

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 41/47 DM Function (@BL=8) only for write CKE CS RAS CAS BA0, BA1 WE DQS(CL=3) DQ(CL=3) 01 234 567891 0 HIGH DM COMMAND A 10 /AP ADDR (A0~An) Da4 Da5 Da7Da6Da0 Da1 Da3Da2 WRITE Ca CLK CLK 10122B32R.B BAa

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 42/47 Deep Power Down Mode Entry & Exit Cycle Note: DEFINITION OF DEEP POWER MODE FOR Mobile DDR SDRAM: Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory of the device. Once the device enters in Deep Power Down Mode, data will not be retained. Full initialization is required when the device exits from Deep Power Down Mode. TO ENTER DEEP POWER DOWN MODE 1) The deep power down mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of the clock. While CKE is low. 2) Clock must be stable before exited deep power down mode. 3) Device must be in the all banks idle state prior to entering Deep Power Down mode. TO EXIT DEEP POWER DOWN MODE 4) The deep power down mode is exited by asserting CKE high. 5) 200 μs wait time is required to exit from Deep Power Down. 6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands and a load mode register sequence.

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 43/47 Mode Register Set CKE CS RAS CAS ADDR (A0~An) Precharge Command All Bank DQS DQs MRS Command Any Command BA0, BA1 A10/AP WE DM ADDRESS KEY t RP CLK CLK t MRD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 HIGH KEY KEY KEY Hi-Z Hi-Z COMMAND 10122B32R.B

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 44/47 Simplified State Diagram PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write = Write w/o Auto Precharge Write A = Write with Auto Precharge Read = Read w/o Auto Precharge Read A = Read with Auto Precharge PRE = Precharge BST = Burst Terminate DPDS = Enter Deep Power-Down DPDSX = Exit Deep Power-Down

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 45/47 PACKING DIMENSIONS 144-BALL FBGA DDR DRAM (12x12mm) Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max A 1.14 1.40 0.049 0.055 D1 8.80 0.346 E1 8.80 0.346 e 0.80 0.031 aaa 0.10 0.004 bbb 0.10 0.004 ddd 0.12 0.005 eee 0.15 0.004 fff 0.08 0.006 MD/ME 12/12 12/12

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 46/47

Revision History

0.1 2011.12.30 Original 0.2 2012.06.25 Delete CAS Latency: 2 1.0 2014.02.21 1. Delete "Preliminary" 2. Modify the specification of IDD2NS, IDD3P, IDD3PS

ESMT M53D256328A (2F) Elite Semiconductor Memory Technology Inc. Publication Date :Feb. 2014 Revision : 1.0 47/47 Important Notice All rights reserved. No part of this document may be reproduc ed or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the product s or specification in this document without notice. The information contained herein is presen ted only as a guide or examples for the application of our products. No res ponsibility is assumed by ESMT for any infringement of patents, copyrights, or ot her intellectual propert y rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inhere ntly a certain rate of failure. To minimize risks associated with custom er's application, adeq uate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or caus e physical injury or property damage. If products described here are to be used for such kinds of applicat ion, purchaser must do its own quality assurance testing appropriate to such applications.

Product Information

M53D256328A-2F specifications and overview.

Summary

Internal pipelined double-data-rate architecture, two data

Description

Internal pipelined double-data-rate architecture, two data

Source title M53D256328A-2F Datasheet(PDF) - Elite Semiconductor Memory Technology Inc.

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