M52D128324A-2E

M52D128324A-2E ESMT | Alldatasheet

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ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 1/31 M o b i l e S D R A M 1M x 32Bit x 4Banks Mobile Synchronous DRAM

FEATURES

z 1.8V power supply z LVCMOS compatible with multiplexed address z Four banks operation z MRS cycle with address key programs - CAS Latency (2 & 3 ) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) z EMRS cycle with address key programs. z All inputs are sampled at the positive going edge of the system clock z Burst Read Single-bit Write operation z Special Function Support - PASR (Partial Array Self Refresh ) - TCSR (Temperature Compensated Self Refresh) - DS (Driver Strength) z DQM for masking z Auto & self refresh z 64ms refresh period (4K cycle) GENERAL DESCRIPTION The M52D128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of syst em clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

ORDERING INFORMATION

Freq. Package Comments M52D128324A -5BG2E 200MHz 90 Ball BGA Pb-free M52D128324A -6BG2E 166MHz 90 Ball BGA Pb-free M52D128324A -7BG2E 143MHz 90 Ball BGA Pb-free BALL CONFIGURATION (TOP VIEW) (BGA90, 8mmX13mmX1.0mm Body, 0.8mm Ball Pitch) 1 2 3 4 5 6 7 8 9 A DQ26 DQ24 VSS VDD DQ23 DQ21 B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19 C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ E VDDQ DQ31 NC NC DQ16 VSSQ F VSS DQM3 A3 A2 DQM2 VDD G A4 A5 A6 A10 A0 A1 H A7 A8 NC NC BA1 A11 J CLK CKE A9 BA0 CS RAS K DQM1 NC NC CAS WE DQM0 L VDDQ DQ8 VSS VDD DQ7 VSSQ M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 R DQ13 DQ15 VSS VDD DQ0 DQ2

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 2/31 FUNCTIONAL BLOCK DIAGRAM PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System Clock Active on the posit ive going edge to sample all inputs. CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, column address : CA0 ~ CA7 BA0, BA1 Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write Enable Enables write operation and row precharge. Latches data in starting from CAS , WE active. DQM0~3 Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. DQ0~31 Data Input / Output Data inputs/ outputs are multiplexed on the same pins. VDD/VSS Power Supply / Ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data Output Power / Ground Isolated power supply and ground for the output buffers to provide improved noise immunity. NC No Connection This pin is recommended to be left No Connection on the device. DQM0~3 DQ Mode Register Control Logic Column Address Buffer Refresh Counter Row Address Buffer Refresh Counter Bank D Row Decoder Bank A Bank B Bank C Sense Amplifier Column Decoder Data Control Circuit Latch Circuit Input & Output Buffer Address Clock Generator CLK CKE Command Decoder CS RAS CAS WE

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 3/31 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to VSS V IN,VOUT -1.0 ~ 2.6 V Voltage on VDD supply relative to VSS V DD,VDDQ -1.0 ~ 2.6 V Operation ambient temperature T A 0 ~ +70 ℃ Storage temperature T STG -55 ~ + 150 ℃ Power dissipation P D 0.7 W Short circuit current I OS 50 mA Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V) Parameter Symbol Min Typ Max Unit Note Supply voltage V DD,VDDQ 1.7 1.8 1.95 V 1 Input logic high voltage V IH 0.8 x V DDQ 1.8 V DDQ+0.3 V 2 Input logic low voltage V IL -0.3 0 0.3 V 3 Output logic high voltage V OH V DDQ - 0.2 - - V I OH =-0.1mA Output logic low voltage V OL - - 0.2 V I OL = 0.1mA Input leakage current I IL -2 - 2 uA 4 Note: 1. Under all conditions. VDDQ must be less than or equal to VDD. 2. VIH (max) = 2.2V AC. The overshoot voltage duration is ≤3ns. 3. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤3ns. 4. Any input 0V ≤ V IN ≤ V DDQ. Input leakage currents include Hi-Z output leakage fo r all bi-directional buffers with tri-state outputs. CAPACITANCE (VDD = 1.8V, TA = 25℃, f = 1MHz) Pin Symbol Min Max Unit CLOCK C CLK 2.0 4.0 pF RAS , CAS , WE , CS , CKE, DQM0~3 CIN 2.0 4.0 pF ADDRESS C ADD 2.0 4.0 pF DQ0 ~DQ31 C OUT 3.5 6.0 pF

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 4/31 DC CHARACTERISTICS (Recommended operating condition unless otherwise noted) Version Parameter Symbol Test Condition -5 -6 -7 Unit Note Operating Current (One Bank Active) ICC1 Burst Length = 1 tRC ≥ t RC (min), tCC ≥ t CC (min), IOL= 0mA 55 50 45 mA 1 ICC2P CKE ≤VIL(max), tCC =15ns 900 uA Precharge Standby Current in power-down mode ICC2PS CKE ≤VIL(max), CLK ≤VIL(max), tCC = ∞ 900 uA ICC2N CKE ≥VIH(min), CS ≥VIH(min), tCC =15ns Input signals are changed one time during 30ns 10 mA Precharge Standby Current in non power-down mode ICC2NS CKE ≥VIH(min), CLK ≤VIL(max), tCC = ∞ Input signals are stable 10 mA ICC3P CKE ≤VIL(max), tCC =15ns 3 Active Standby Current in power-down mode ICC3PS CKE ≤VIL(max), CLK ≤VIL(max), tCC = ∞ 1 mA ICC3N CKE ≥VIH(min), CS ≥ V IH(min), tCC=15ns Input signals are changed one time during 2clks All other pins ≥ V DD-0.2V or ≤ 0.2V 20 mA Active Standby Current in non power-down mode (One Bank Active) ICC3NS CKE ≥VIH (min), CLK ≤VIL(max), tCC= ∞ Input signals are stable 7 mA Operating Current (Burst Mode) ICC4 IOL= 0mA, Page Burst All Bank Activated, tCCD = tCCD (min) 100 90 80 mA 1 Refresh Current ICC5 t RFC ≥tRFC(min) 70 65 60 mA 2 TCSR range 45 85 C° Full array 950 1000 1/2 array 900 950 1/4 array 850 900 Self Refresh Current ICC6 CKE ≤0.2V 1/8 array 800 850 uA Deep Power Down Current ICC7 CKE ≤0.2V 10 uA Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min). 2. Refresh period is 64ms. Addresses are changed only one time during tCC(min).

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 5/31 AC OPERATING TEST CONDITIONS (VDD= 1.7V~1.95V) Parameter Value Unit Input levels (Vih/Vil) 0.9 x V DDQ / 0.2 V Input timing measurement reference level 0.5 x V DDQ V Input rise and fall time tr / tf = 1 / 1 ns Output timing measurement reference level 0.5 x V DDQ V Output load condition See Fig.2 OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Version Parameter Symbol -5 -6 -7 Unit Note Row active to row active delay t RRD(min) 10 12 14 ns 1 RAS to CAS delay tRCD(min) 15 18 21 ns 1 Row precharge time t RP(min) 15 18 21 ns 1 tRAS(min) 40 42 42 ns 1 Row active time tRAS(max) 100 us - @ Operating t RC(min) 55 60 63 ns 1 Row cycle time @ Auto refresh t RFC(min) 55 60 63 ns 1,6 Last data in to new col. Address delay t CDL(min) 1 CLK 2 Last data in to row precharge t RDL(min) 2 CLK 2 Last data in to burst stop t BDL(min) 1 CLK 2 Col. Address to col. Address delay t CCD(min) 1 CLK 3 Mode Register command to Active or Refresh command tMRD(min) 2 CLK - Refresh period (4,096 rows) t REF(max) 64 ms 5 CAS Latency=3 2 Number of valid output data CAS Latency=2 1 ea 4 Note: 1. The minimum number of clock cycles is determined by divi ding the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrup t, auto precharge and read burst stop. The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks. 5. A maximum of eight consecutiv e AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6 μs.) 6. A new command may be given t RFC after self refresh exit. Z0=50 1.8V Output (Fig.2) AC Output Load Circuit 20 pF Vtt =0.5x VDD Q VOH(DC) = VDDQ-0.2V, IOH = -0.1mA VOL(DC) = 0.2V, IOL = 0.1mA 20 pF Output (Fig.1) DC Output Load circuit 10.6K 13.9K

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 6/31 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit Note CAS Latency =3 5 6 7 CLK cycle time CAS Latency =2 tCC 1000 1000 1000 ns 1 CAS Latency =3 4.5 5 6 CLK to valid output delay CAS Latency =2 tSAC 8 8 9 ns 1 Output data hold time t OH 2 2 2.5 ns 2 CLK high pulse width t CH 2 2 2.5 ns 3 CLK low pulse width t CL 2 2 2.5 ns 3 Input setup time t SS 1.5 1.5 2 ns 3 Input hold time t SH 1 1 1.5 ns 3 CLK to output in Low-Z t SLZ 1 1 1 ns 2 CAS Latency =3 4.5 5 6 CLK to output in Hi-Z CAS Latency =2 tSHZ 8 8 9 ns - *All AC parameters are measured from half to half. Note: 1.Parameters depend on programmed CAS latency. 2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3.Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 7/31 MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address BA0~BA1 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function 0 RFU RFU W.B.L TM CAS Latency BT Burst Length Test Mode CAS Latency Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 1 Reserved 0 1 1 3 0 1 1 8 8 Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved

0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved

1 Single Bit 1 1 1 Reserved

Full Page Length: 256 Note: 1. RFU (Reserved for future use) should stay “0” during MRS cycle. 2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled. 3. The full column burst (256 bit) is available only at sequential mode of burst type.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 8/31 Extended Mode Register BA1 BA0 A11 ~ A8 A7 A6 A5 A4 A 3 A 2 A 1 A 0 A d d r e s s b u s 1 0 0* DS TCSR PASR Extended Mode Register Set Note: * BA0, A11~A8 should stay “0” during EMRS cycle. ** MSB: most significant bit. A2-0 Self Refresh Coverage

000 Full array

001 1/2 array (BA 1=0) 010 1/4 array (BA0=BA1=0)

011 Reserved

100 Reserved

(BA1 = BA0 = Row Addr MSB** =0)

110 Reserved

111 Reserved

000 Full Strength

101 Reserved

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 9/31 Burst Length and Sequence (Burst of Two) S t a r t i n g A d d r e s s (column address A0 binary) Sequential Addressing S e q u e n c e ( d e c i m a l ) Interleave Addressing S e q u e n c e ( d e c i m a l ) 0 0,1 0,1 1 1,0 1,0 (Burst of Four) S t a r t i n g A d d r e s s (column address A1-A0, binary) Sequential Addressing S e q u e n c e ( d e c i m a l ) Interleave Addressing S e q u e n c e ( d e c i m a l ) 00 0,1,2,3 0,1,2,3 01 1,2,3,0 1,0,3,2 10 2,3,0,1 2,3,0,1 11 3,0,1,2 3,2,1,0 (Burst of Eight) S t a r t i n g A d d r e s s (column address A2-A0, binary) Sequential Addressing S e q u e n c e ( d e c i m a l ) Interleave Addressing S e q u e n c e ( d e c i m a l ) Full page burst is an extension of the above tables of Se quential Addressing, with the length being 256 for 4Mx32 device.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 10/31 SIMPLIFIED TRUTH TABLE COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11 A9~A0 Note Mode Register Set H X L L L L X OP CODE 1,2 Register Extended Mode Register Set H X L L L L X OP CODE 1,2 Auto Refresh H 3 Entry H L L L L H X X 3 L H H H 3 Refresh Self Refresh Exit L H H X X X X X 3 Bank Active & Row Addr. H X L L H H X V Row Address Auto Precharge Disable L 4Read & Column Address Auto Precharge Enable H X L H L H X V H Column Address (A0~A7) 4,5 Auto Precharge Disable L 4Write & Column Address Auto Precharge Enable H X L H L L X V H Column Address (A0~A7) 4,5 Burst Stop H X L H H L X X 6 Bank Selection V L 4Precharge All Banks H X L L H L X X H X 4 H X X X Entry H L L H H H X Clock Suspend or Active Power Down Mode Exit L H X X X X X X H X X X Entry H L L H H H X H X X X Precharge Power Down Mode Exit L H L H H H X X DQM H X V X 7 H H X X X No Operation Command H X L H H H X X Entry H L L H H L X Deep Power Down Mode Exit L H X X X X X X (V= Valid, X= Don’t Care, H= Logic High, L = Logic Low) Note: 1. OP Code: Operation Code A0~A10/AP, A11, BA0~BA1: Program keys (@MRS). BA1 = 0 for MRS and BA1 = 1 for EMRS 2. MRS/EMRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS/EMRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by “Auto”. Auto / self refresh can be issued only at all banks idle state. 4. BA0~BA1: Bank select addresses. If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected. If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected. If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected. If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected. 5. During burst read or write with auto precha rge, new read/write command can not be issued. Another bank read / write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive go ing edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after (Read DQM latency is 2).

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 11/31 Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency=3, Burst Length=1

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 12/31 Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge. 2. Bank active @ read/write are controlled by BA0~BA1. BA1 BA0 Active & Read/Write 0 0 Bank A 0 1 Bank B 1 0 Bank C 1 1 Bank D 3. Enable and disable auto precharge function are controlled by A10/AP in read/write command A10/AP BA1 BA0 Operating 0 0 Disable auto precharge, leave A bank active at end of burst. 0 1 Disable auto precharge, leave B bank active at end of burst. 1 0 Disable auto precharge, leave C bank active at end of burst. 1 1 Disable auto precharge, leave D bank active at end of burst. 0 0 Enable auto precharge, precharge bank A at end of burst. 0 1 Enable auto precharge, precharge bank B at end of burst. 1 0 Enable auto precharge, pr echarge bank C at end of burst. 1 1 Enable auto precharge, pr echarge bank D at end of burst. 4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted. A10/AP BA1 BA0 Precharge 0 0 0 Bank A 0 0 1 Bank B 0 1 0 Bank C 0 1 1 Bank D

1 X X All Banks

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 13/31 Power Up Sequence 0123456789 CLOCK CKE CS RAS CAS ADDR WE DQ DQM A10/AP t RP Key Key BA1 BA0 High-Z Precharge (All Banks) Auto Refresh Auto Refresh Mode Register Set Extended Mode Register Set :D o n ' tc a r e t RFC t RFC High level is necessary High level is necessary 10 11 12 13 14 15 16 17 18 19 20 RA BS BS RA Row Active t MRD t MRD Power-Up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ - Apply VDDQ 2. Start clock and maintain stable condition for a minimum. 3. The minimum of 200us after stable power and clock (CLK), apply NOP & take CKE high. 4. Issue precharge commands for all banks of the device. 5. Issue 2 or more auto-refresh commands. 6. Issue mode register set command to initialize the mode register. 7. Issue extended mode register set command to set PASR and DS.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 14/31 Read & Write Cycle at Same Bank @ Burst Length = 4 Note: 1.Minimum row cycle times is required to complete internal DRAM operation. 2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3.Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst) Burst can’t end in Full Page Mode. tRCD tRC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE CS RAS CAS ADDR WE DQ DQM A10/AP BA0 BA1 CL=2 CL=3 Ra Ca Rb Cb Ra Rb tOH tOH tSAC tSAC tSHZ tSHZ ReadRow Active Precharge (A-Bank)(A-Bank)(A-Bank) Precharge (A-Bank) Write (A-Bank) Row Active (A-Bank) *Note3 *Note3 : Don't care *Note1 Qa0 Qa1 Qa2 Qa3 Db0 Db3Db1 Db2 Qa0 Qa1 Qa2 Qa3 Db0 Db3Db1 Db2 HIGH *Note2 tRDL tRDL

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 15/31 Page Read & Write Cycle at Same Bank @ Burst Length=4 Note: 1.To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention. 2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 16/31 Page Read Cycle at Different Bank @ Burst Length=4 Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge. 2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. R o w A c t i v e ( A - B a n k ) R o w A c t i v e ( B - B a n k ) R e a d ( A - B a n k ) R o w A c t i v e ( C - B a n k ) R e a d ( B - B a n k ) P r e c h a r g e ( A - B a n k ) R o w A c t i v e ( D - B a n k ) R e a d ( C - B a n k )P r e c h a r g e ( B - B a n k ) R e a d ( D - B a n k ) P r e c h a r g e ( C - B a n k ) P r e c h a r g e ( D - B a n k ) : D o n ' t C a r e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 81 9 CLOCK CKE CS RAS CAS ADDR WE CL=2 DQM A10/AP BA1 BA0 CL=3 RBb CAa RCc CBb RDd CCc CDd *Note1 *Note2 RAa RDd QBb0 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2QAa1QAa0 QAa2 QBb1 QAa0 QAa1 QAa2 QBb0 QCc1 QCc2 QDd0 QDd2QDd1QBb1 QCc0QBb2 RAa RBb RCc HIGH DQ

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 17/31 Page Write Cycle at Different Bank @ Burst Length = 4 Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2.To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 18/31 Read & Write Cycle at Different Bank @ Burst Length = 4 Note: 1.tCDL should be met to complete write.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 19/31 Read & Write Cycle with Auto Precharge @ Burst Length =4 Note: 1.tCDL should be controlled to meet minimum tRAS before internal precharge start (In the case of Burst Length=1 & 2) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE CS RAS CAS ADDR WE DQ DQM A10/AP BA0 BA1 CL =2 CL =3 Row Active ( A - Bank ) Row Active ( D - Bank ) Read with Auto Precharge ( A - Bank ) Auto Precharge Start Point (D-Bank) : D o n ' t C a r e QAa1 QAa2 QAa3 Ddb1 DDb2 DDd3DDb0QAa0 Ra CbRa CaRb Rb QAa1 QAa2 QAa3 Ddb1 DDb2 DDd3DDb0QAa0 Auto Precharge Start Point Write with Auto Precharge (D-Bank) HIGH

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 20/31 Clock Suspension & DQM Operation Cycle @ CAS Latency=2, Burst Length=4 Note: 1. DQM is needed to prevent bus contention.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 21/31 Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length =Full page Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue. 2.About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1, 2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycle”. 3.Burst stop is valid at every burst length. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE CS RAS CAS ADDR WE DQ DQM A10/AP BA1 BA0 RAa CAa CAb RAa QAa0 QAa1 QAb1QAb0 QAb2 Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) :Don't Care HIGH CL=2 CL=3 QAa2 QAa3 QAa4 QAb3 QAb4 QAb5 QAa0 QAa1 QAb1QAb0 QAb2QAa2 QAa3 QAa4 QAb3 QAb4 QAb5 1 1 2 2 Precharge (A-Bank) *Note2 *Note1 *Note1

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 22/31 Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page Note: 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 2. Burst stop is valid at every burst length.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 23/31 Burst Read Single bit Write Cycle @ Burst Length=2 Note: 1. BRSW modes is enabled by setting A9 “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge command will be issued after two clock cycles. CLOCK CKE ADDR CL=2 DQM A10/AP BA RAa RAc RAa QAb0 Row Active (A-Bank) Write (A-Bank) :Don't Care HIGH QAb1 Precharge (A-Bank) CAa RBb CAb CBc CAd RAc DBc0 DQ DAa0 QAb0 DBc0QAb1CL=3 Row Active (B-Bank) Row Active (A-Bank) Write with Auto Precharge (B-Bank) Read (A-Bank) DAa0 QAd0 QAd1 QAd0 QAd1 *Note1 CS RAS CAS WE RBb *Note2 Read with Auto Precharge (A-Bank)

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 24/31 Active/Precharge Power Down Mode @ CAS Latency=2, Burst Length=4 Note: 1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK+tss prior to Row active command. 3. Can not violate minimum refresh specification. (64ms) CLOCK CKE CS RAS CAS ADDR WE DQ DQM A10/AP BA0 Active Power-down Exit Precharge : Don't care *Note3 *Note2 *Note1 t SS t SS t SS Ra Ra Qa0 Qa1 Qa2 t SHZ Precharge Power-Down Entry Precharge Power-Down Exit Row Active Active Power-down Entry Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Ca BA1

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 25/31 Deep Power Down Mode Entry & Exit Cycle Note: DEFINITION OF DEEP POWER MODE FOR Mobile SDRAM: Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory of the device. Once the device enters in Deep Power Down Mode, data will not be retained. Full initialization is required when the device exits from Deep Power Down Mode. TO ENTER DEEP POWER DOWN MODE 1) The deep power down mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of the clock. While CKE is low. 2) Clock must be stable before exited deep power down mode. 3) Device must be in the all banks idle state prior to entering Deep Power Down mode. TO EXIT DEEP POWER DOWN MODE 4) The deep power down mode is exited by asserting CKE high. 5) 200 μs wait time is required to exit from Deep Power Down. 6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands and a load mode register sequence.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 26/31 Self Refresh Entry & Exit Cycle Note: TO ENTER SELF REFRESH MODE 1. CS ,RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including th e system clock can be don’t care except for CKE. 3. The device remains in self refresh mode as long as CKE stays “Low”. cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS Starts from high. 6. Minimum t RFC is required after CKE going high to complete self refresh exit. 7. 4K cycles of burst auto refresh is r equired immediately before self refresh entry and immediately after self refresh exit.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 27/31 Mode Register Set Cycle Auto Refresh Cycle CLOCK CKE ADDR Key :Don't Care HIGH CS RAS CAS HIGH *Note3 Ra *Note1 DQ Hi-Z DQM 12 345 6 01 2 345 67 89 1 0 Hi-Z *Note2 t RFC MRS New Command Auto Refresh New Command WE BA0 BA1 BS BS * All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note: 1. CS ,RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 28/31 Extended Mode Register Set Cycle CLOCK CKE ADDR Key :Don't Care CS RAS CAS HIGH *Note3 Ra *Note1 DQ Hi-Z DQM 12 345 6 *Note2 EMRS New Command WE BA0 BA1 BS BS *All banks precharge should be completed before Extended Mode Register Set cycle. EXTENDED MODE REGISTER SET CYCLE *Note: 1. CS ,RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 29/31 PACKING DIMENSIONS 90-BALL SDRAM ( 8x13 mm ) Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max Controlling dimension : Millimeter.

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 30/31

Revision History

0.1 2010.01.26 Original 0.2 2010.05.11 Add package descrip tion into ball configuration 1.0 2012.08.24 1. Delete "Preliminary" 2. Add speed grade -6 and delete speed grade -10 3. Correct the specification of tRC and tRFC for speed grade -5 4. Add the specification of tMRD 5. Correct EMRS and Power Up Sequence 6. Correct A(max) of packing dimension 7. Correct typo and figures 8. Modify the specification of ICC1, ICC2P,ICC2PS,ICC4,ICC6 for speed grade -5/-7

ESMT M52D128324A (2E) Elite Semiconductor Memory Technology Inc. P u b l i c a t i o n D a t e : Aug. 2012 Revision : 1.0 31/31 Important Notice All rights reserved. No part of this document may be rep roduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the ri ght to change the product s or specification in this document without notice. The information contained herein is pres ented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted un der any patents, copy rights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inher ently a certain rate of failure. To minimize risks associated with cust omer's application, adequate design and operating safeguards against injury, dam age, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its ow n quality assurance testing appropriate to such applications.