M5296FP | DigiCamel IC Datasheet

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M5296FP RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 7tENESAS Renesas Technology Corp.

MITSUBISHI <Dig./Ana. INTERFACE> +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC

DESCRIPTION

‘The M5296FP is a watchdog timer semiconductor integrated PIN CONFIGURATION (TOP VIEW) circuits which incorporates a 5V constant-voltage power supply. p-ruN input [F]O Ld] Viet To check for system failure and assure safe system opera- Capacitance Vreti tions, the M5296FP has three sequential outputs (HALT, caraceeke’ Fa] aaj fons, pecaclal cr STBY, and RESET) and a watchdog timer output which STBY ouTPuT z Voad intermittently generates a reset pulse when pulse width or teiay 8 one cycle abnormalities are found in the clock signal from the caracirance1 B] 2 vo microcomputer. (The watchdog output terminal is shared by RALT oureut [6] 0 8 the watchdog timer output and sequential output RESET.) RESET OUTPUT {10} tor Further, each output retains the Low reset feature at crouno [B| [3] Ve supply voltages down to 0.8V, thereby preventing system malfunctioning upon power ON. Ciilline 1862 A

FEATURES

© Watchdog timer (clock pulse width and cycle are monitored at the same time). © Power ON reset timer. © Three outputs (HALT output for holding, RESET output for reset, and STBY output for return). © Output voltage (can be fine-tuned with an external resistor) Leet te vette ev eeeeeesereeeeess BVEO.25V @ The delay time can be set using an external capacitor (the setting can be varied from about Imsec to 1sec). © Built-in overcurrent protection circuit (which can be set up with an external resistor). APPLICATION Home and industrial microcomputer systems. BLOCK DIAGRAM — Ve lor B Vo VoAdj HALT @ - (9) @) ae = G ICURRENT LIM TER) | COMPARATOR 1.24v Tae? hence | Vren (15) ET Mrvounee Ee GARCUT (400 18) — EX, ese RISE/FALL OFLA 7h 0.63V WaTCHOOG TES e-RUN (1) a (se D> Adj Cc. C2 Cy stENESAS 7-65

MITSUBISHI <Dig./Ana. INTERFACE> +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC DEFINITION OF TERMS teu): HALT output delay time. titnw) ‘ Watchdog reset pulse width. The time interval between the instant Vo is restored to The width of an about 50% duty intermittent pulse that the VrH1 £AVqH1 level and the instant the HALT is generated from the RESET terminal when the clock output is remove. signal input to the P-RUN terminal has alow input level, te(pw) : P-RUN input minimum pulse width. an insufficient pulse width, an excessively long period, The minimum pulse width for clock signal normality or other problem. detection. Vin-p © P-RUN H input voltage. Cycle t= 2+triaw) The minimum input voltage for P-RUN terminal input clock signal High level detection. taiaw) ° Watchdog time. Vin-pL : The maximum input voltage for P-RUN terminal The time for clock signal monitoring or the maximum input clock signal Low level detection clock cycle during which clock signal normality is de- tected. tain) ‘ RESET output delay time. The delay time from the instant the STBY output is remove to the moment the RESET output is remove tain) ‘ RESET output delay time. The time interval between HALT output fall/rise and RESET output fall/rise in cases where the STBY output is not generated (when Vo does not drop below Vri42). APPLICATION CIRCUIT EXAMPLE Rs : Le 7 e 2 HUE | CO} or RESET?) RESET ourPuT inpuT P-AUN STBY - ‘STBY OuTPUT f yy ic R 22,F (4)} 10d) Yet re a (So Veer HB I] g Ju | 1OnF Gee «l/s )a]s 3 ale a iL. GND Ea Z716 LySTeT eS é74 el PTT otfisisi|s —o eno Cy, Co «Necessary for oscillation prevention and input/ If the watchdog timer function is not to be used, ground output stabilization. Be sure that these devices are used terminal ©). near the IC pins. Cy «+ Required for watchdog time setup. If the watch- Rg -- Required for current limiting setup. If the dog timer function is not to be used, ground terminal current limiting function is not to be exercised, short @. terminals @ and @. Cg se Required for reset delay time setup for STBY Ri agj 7 Resistor for delay time (ty(mw) to tecpw)) setup output generation (V7}42 detection). When terminal @ constant current determination. A standard setting of is open, the delay time for STBY output is equal to that 18kQ should be employed. for HALT output. Ri, Rz"Resistor for threshold voltage Vry1 setup. taiR)= tan) For the setup procedure, see the later section entitled Ry «+ As STBY and RESET are open-collector outputs, “PERIPHERAL CIRCUIT CONSTANT SETUP AND load resistor R,_ is needed. USAGE PRECAUTIONS.” Cry, Crz + Used when voltage detection terminals (3 and Cy Necessary for watchdog reset pulse width setup. @ are unstable due to power line noise or other factor. 2tENESAS 7-67

MITSUBISHI <Dig./Ana. INTERFACE> +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC These devices are not needed when no such problems —tgipw)) that are not to be detected as the clock signal, exist. intermittent pulses (pulse width ti(aw) having a duty ratio cR Necessary for RESET output chattering pre- of about 50% are outputted from the RESET terminal. vention. The setup must be such that Cr - Ri24.0 x When the entered clock signal has a pulse width of te (pw) 10-5 (F+Q) or more, the RESET intermittent operation stops and the signal goes High so that the watchdog timer (time setting: TIMING DIAGRAMS trimw) actuates. If no clock signal having a pulse width of 1. Watchdog Timer te (pw) OF more is entered for a time period of tz (Rw) after When the clock signal input is not give to the P-RUN input _clock signal input, the RESET output starts an intermittent terminal or the entered signal has pulse widths (less than operation. \\ \\ 1 ' , H i ® \\ ® ' @ \\ @ ' Ste atte att —=_- — 4 1 H Hi i a j t 1 f<tecow) T>tecew) [E> terrw ; tee) 1 \\ I ' ' ; RESET OUTPUT ! tcaw) 1 2tcmw | ' tinw) 1 enw) i es ee (1) The clock signal input is give to the P-RUN input ter- However, as the clock signal cycle is rendered longer minal. However, as the pulse width is smaller than than the watchdog time t2 (Rw). RESET starts an inter- te (pw), the clock signal input is not detected as a signal mittent operation. so that RESET generates intermittent pulsing. (4) The RESET intermittent operation starts tz (mw) after (2) As the signal input has @ pulse width of ts (pw) oF clock signal input due to the same operations as more, the RESET intermittent operation stops and the indicated in paragraph (3) above. Even if the clock High output is generated. Further, as the clock signal signal input is fed while the RESET level is Low with cycle is not longer than the watchdog time t2(Rw), intermittent operations performed, RESET does not RESET keeps its High output. immediately go High so that the Low pulse width (3) RESET maintains its High output by performing the (ty (aw) is assured. same operations as indicated in paragraph (2) above. VOLTAGE MONITORING TIMING DIAGRAM (P-RUN INPUT NORMALITY) —_—— SSS eel = Vent % Joo NAN + 1 aval Ven ' rt Vea vy ! it in 1 1! ! I i HALT ouTPut sc oe Htc | r aa \\ 4 1 : STBY ouTPUT tos ' ' ' , of 4 ' a 1 bow i ' Lt tron i RESET ouTPUT ¢ 4 hee TO H thou tho ' tin tan tow ton) 7tENESAS 7-68

MITSUBISHI <Dig./Ana. INTERFACE> +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC 2. Voltage Monitoring Timing Diagram NOTE 1: VrH1 must be set up so that Vrw1 > Vin2- (P-RUN Input Normality) NOTE 2: If malfunctioning occurs due to noise or other HALT output problem, connect an about 1000pF capacitor When Vo drops below the threshold voltage VTHi, between terminals @ and GND to assure HALT generates a Low level. HALT is reset ts (u) after stable operations. Vo is restored to the VTH; +AVTH; level. . STBY output 2. Delay Time Setup When Vo drops below the threshold voltage VTH; The MS296FP uses an external capacitor to set up three (VTH) <VTH;), STBY generates a Low level. When Vo _ different delay times (watchdog reset pulse width ti (nw). is restored to the VTH, level, STBY is reset watchdog time tr(pw), and RESET output delay time RESET output tary) When the decreased Vo level is between VTH2 and VTHi (VTH2 < Vo < VTHi), RESET output genere- tion takes place ta iq) after HALT fall/rise. When Vo is (1) tiwnw) Setup lower than VTH3, RESET rise occurs t3(p) after STBY | When the clock signal input to the P-RUN terminal is rise. abnormal, intermittent pulsing having a duty ratio of about However, t3(q)> ts (H)- 50% is generated from the RESET terminal. The oscillation cycle 2-t: mw) is to be set up using C; as PERIPHERAL CIRCUIT CONSTANT SETUP indicated below. AND USAGE PRECAUTIONS 2etyam=6.72% 10°C: (s) 1. Threshold Voltage Setup As indicated in the timing diagram on the preceding page, (2) ta(rw) Setup the M5296FP checks for output voltage decrease on the ‘The watchdog time t2(Rw) 's used for clock signal moni- basis of two preset values (threshold voltages 1 and 2 toring purposes. It denotes the clock signal cycle limit. If [Vai and Vrugl). Veni can be set as desired with an the clock signal cycle becomes longer than tzinw), inter external resistor (however, Vr. > VrH2). Vru2 is set to‘ mittent pulses preset by C, are generated from the RESET 3.0V Typ by the built-in resistor; however, it is possible terminal. The value tz(qw) is to be set up by Co. to raise it slightly using the Vref2 terminal. tainw) = tuaw)t 1.53 x 10®x C2 (s) (3) tain) Setup OVo The RESET output delay time t3,,) refers to the elapsed ) () time from the instant the STBY output is reset to the Re moment RESET output is reset. It is to be set up by C tain)= 1.18% 10°x Cs (s) (8) 3. Output Voltage Vo Adjustment Vo 1 8 3.76 | | 8. 2k In the above circuit, Vrw1 is calculated as follows. ® ' 1. 24V R. 1.24 | Vr1=0.63x2F2 (y) | For Vry1 detection purposes, hysteresis is provided to @) avoid operation instability which may be caused by noise ripple or other factor, and its value is as indicated below. As shown above, the VoAqj terminal permits output AVe 7x82 (my) voltage fine adjustment. However, as a 8.2k2 resistor is R, series-connected to the VoAqj terminal, the approximate adjustment range is from -20% to +10%. 7tENESAS 769

MITSUBISHI <Dig./Ana. INTERFACE> MS5296FP +SV CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC 4. Overcurrent Protection Setup (Io Peak Current Setup) Rs Veo Vo OMOROIC f mene * In the circuit shown at left, the load current flowing 1 1 through the detection resistor Rg is detected as a voltage value (detection voltage: 130mV) for current limiting purposes. | | is 130(mV) ‘in : 2 Rs (2) @) NOTE 3: The current flowing through Rg contains the IC bias current Ig. Therefore, the setup must be such that Ig <130/Rs (mA). TYPICAL CHARACTERISTICS THERMAL DERATING (MAXIMUM RATING) BIAS CURRENT VS. INPUT VOLTAGE 1000 32, = RRR et | piseeeeeessescaad = so 2 SCE é EE at Oe E © 2a & cof —} . SCO g 8 SOOO 2 1 oN = wtiAd He HH 400 38 ACCeCCeeee eee

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= IS 6 shi eee 2 200 . Coco z S Score ee & a SCE E4 0 oC ET Terr ttre oO 25 50 75 100 125 02 4 6 8 10 12 14 16 AMBIENT TEMPERATURE Ta (°C) INPUT VOLTAGE Vg (V) OUTPUT VOLTAGE (Vo) VS. OUTPUT VOLTAGE (Vo) VS. INPUT VOLTAGE (Vg) LOAD CURRENT (i,) 10 8 . TT ELT TT tentee| eh RA a 27 °

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£ “COPPPC oo e LITT TT a 8 7 im 5 | w=o7 [Tt 5 SP ys eae ee ipccoaeeees BSD oI TT at TT tt 4 INPUT VOLTAGE Vg (V) LOAD CURRENT |, (A) ztENESAS 7—70

MITSUBISHI <Dig./Ana. INTERFACE> MS296FP +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC CRITICAL OPERATION VOLTAGE CRITICAL OPERATION VOLTAGE CHARACTERISTICS CHARACTERISTICS 1.0 1.0 ERT ERT a 0.8 [| tt | r 08 > “LETTE aa SULT Tt Te a ar ee 3 i e° AW gC Aye ECCT AWS 5 oat | TVW ry) 4 \\\\\\" 5 ayaa Aes EB 4 We, — E02 || Z| 11 We 02 SU Amen | g AGnEoENS— B Vie AC== i I | CSS A Tit) |) Ss OUTPUT VOLTAGE Vo (V) OUTPUT VOLTAGE Vo (V) CRITICAL OPERATION VOLTAGE CHARACTERISTICS SATURATION VOLTAGE VS. SINK CURRENT 1.0 100 5 ee ee) pr eae S ae rT TTT 2 Fve=t2v FAR es a a & UOC

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ae Oa a Oa 0 |\\\\\\ VA © combi pit EASY 2 0.4 AW B= 2k | 3 SOOm ESSE EHH ae ETT TAL Wk 2 pra ae 3 A.—aka| § combate ea ee 0.2 } | A AAA A= 10k a > ray RESETDe Co Bo. AS = 50m je sSSestneenastes| g lA, | WY 5 on aS =| tae tt ecesmens oA_| a — rom LOE TUT TT TT] 0 0.2 0.4 06 0.8 1.0 10 100 ye Im 10m 100m OUTPUT VOLTAGE Vo (V) SINK CURRENT Isink (A) WATCHDOG RESET PULSE WIDTH VS. DELAY CAPACITANCE WATCHDOG TIME VS. DELAY CAPACITANCE = 10 10 z Pixgi= 18k 0-H 4 ———— © oom UE S ieee

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MITSUBISHI <Dig./Ana. INTERFACE> MS296FP +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC RESET OUTPUT DELAY TIME VS. OUTPUT VOLTAGE VS. DELAY CAPACITANCE AMBIENT TEMPERATURE _ ne 7 cz 5.5) 7 © eon LTT TIT saftpt ttt t | r Rhee ei Ae w | ttt | | |

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B AA ee o 4.7, CLE LL B Dae 1 CHL tH he TREE EE 0.001 0.91 0.1 1.0 —60 —40-20 0 20 40 60 80 100 DELAY CAPACITANCE Cy wiF} AMBIENT TEMPERATURE Tg ec THRESHOLD VOLTAGE VS. WATCHDOG RESET PULSE WIDTH VS. AMBIENT TEMPERATURE AMBIENT TEMPERATURE ce ee ee ee 2 60 S120 get || IT Ti tT zo Lt TT ef PE | sot! | TTT | sett ttt eel 2 CCCP ee ao, TTT TTT 2 +1) | tty vd || tT TT ¢ ott TTT oe 3 1 | 1 { | tT I —60—40 —20 0 20 40 60 80 100 g —60 —40 —20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ts (°C) AMBIENT TEMPERATURE Tz (°C) RESET OUTPUT DELAY TIME VS. WATCHDOG TIME VS. AMBIENT TEMPERATURE AMBIENT TEMPERATURE 400; a = Mo = Ee) SEES 2 ct eH Z ieee ¢ oft 1 TT TT eT | CRY 2 200) a 70 Saad aaa ett TT : aan eo | 1) TTT Ty SCL LTT TTT E 2 att) Tt 4 Att TTI TT | —60—40—20 0 20 40 60 80 100 —60—40—20 0 20 40 60 80 100 AMBIENT TEMPERATURE Tg (°C) AMBIENT TEMPERATURE T; {°C} zRENESAS 7—72 .

MITSUBISHI <Dig./Ana. INTERFACE> MS296FP +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC RESET OUTPUT DELAY TIME vs. HALT OUTPUT DELAY TIME vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE 400; 5005 a fT [1] Ringj=18kQ q (Ly 7] [J Riagi=18k 2 s"(T TTC 3 ot OS PA REE PES Fatt 2 tT 5 op RTT 2 TPT S80 4 | ce SESE TEE 3 E bolt ttt is F LL TT TTT Sr A —60—40-—20 0 20 40 60 80 100 —60—40—-20 0 20 40 60 80 100 AMBIENT TEMPERATURE Tg (°C) AMBIENT TEMPERATURE Ta (°C) P-RUN INPUT MINIMUM PULSE WIDTH VS. = AMBIENT TEMPERATURE BIAS CURRENT VS. AMBIENT TEMPERATURE 3 16, SA) AS eeeceeee ete og et KOE 2 ag ET eof | NI TT TT Bese ceaeeeee beceennes 2 : 2" TTrTrrtTei § TPEEEELET 2 of | EET a 4 BT TTL JET TT TT = gt ttrrtr ey titi iti | Fd —60—-40-20 0 0 40 60 80 100 —60—40-—20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) ztENESAS 7-73

Product Information

M5296FP specifications and overview.

Summary

+5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC

Description

+5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC

Source title M5296FP Datasheet(PDF) - Renesas Technology Corp

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