M52957AFP RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: pROVIDED bY alldatasheet.com(free datasheet download site)
  • PDF pages: 14

Technical content

Features

  • Wide supply voltage range Vcc=2.2 to 5.5V
  • Includes clamp level switching circuit (Switch is 16 kinds by outside control)
  • Includes STANDBY function
  • Includes POWER ON RESET function Application Auto focus control for the CAMERA Sensor for short distance etc Recommended Operating Condition

Rev.1.0, Sep.19.2003, page 2 of 13 Pin Configuration Outline 16P2E 51 2 16PSDN CHN (TESTN) N C STB GND2 GND1 CHF PSDF 11CINT RESET SOUT INT HOLD CLALV Vcc (TESTF) N C M52957AFP Note: pin4,13 is connected only engineering sample Block Diagram CINT GND1 CHN SOUT PSDN STATIONARY LIGHT REMOVE I/V TRANSFORM AMP RECKON PULSE WIDTH TRANSFORM (DOUBLE INTEGRATION) BIAS REFERENCE VOLTAGE NC TESTF CHF SEQUENTIAL CONTROL LOGIC CLALV HOLDINT 9 10 CLAMP LEVEL SWITCHING CLAMP CIRCUIT Vcc GND2 HOLD HOLD HOLD PSDF 14 12 11 8 I1+I2 STB RESET TESTN NC I/V TRANSFORM AMP STATIONARY LIGHT REMOVE Note: pin4,13 is connected only engineering sample

Rev.1.0, Sep.19.2003, page 3 of 13 Absolute Maximum Ratings (Ta = 25°C, unless otherwise noted.) Parameter Symbol Ratings Unit Remark Supply voltage VCC 7.0 V note 1 Power dissipation Pd 320 mW Ta=25 °C Thermal derating K θ −3.2 mW/ °C Ta ≥25°C Pin supply voltage VIF 7.0 V Pin5, 7, 8, 9, 10, 11 Another pin supply voltage VI/O −0.3 to VCC + 0.3 V note 2 Output pin inflow current Isout 0.5 mA NPN open collector Operating temperature Topr −10 to 50 °C Storage temperature Tstg −40 to 125 °C Notes : 1. As a principle, do not provide a supply voltage reversely. 2. As a principle, do not provide the terminals with the voltage over supply voltage or under ground voltage.

Rev.1.0, Sep.19.2003, page 4 of 13

Electrical characteristics

(Ta = 25°C, VCC = 5.0V, unless otherwise noted.) Limits Classification Parameter Symbol Min. Typ. Max. Unit Test conditions Note Operating supply voltage range VCC 2.2 3.0 5.5 V Consuming current Usual consuming current ICC1  5.9 7.7 mA While Rapid charge consuming current 1 ICC2  17.7 23.0 mA While CH rapid charge consuming current While Rapid charge consuming current 2 ICC3  19.0 24.7 mA While CH and CINT rapid charge consuming current While STAND BY consuming current ICC4   1.0 µA *1 HOLD pin HOLD "H" input voltage VHOH 1.1  7.0 V HOLD "L" input current VHOL 0  0.3 V HOLD "H" input current IHOH   1.0 µA VIH=5.5V HOLD "L" input voltage IHOL −100 −75 −50 µA VIL=0V INT pin INT "H" input voltage VINH 1.1  7.0 V INT "L" input voltage VINL 0  0.3 V INT "H" input current IINH   1.0 µA VIH=5.5V INT "L" input current IINL −100 −75 −50 µA VIL=0V CLALV pin CLALV "H" input voltage VCLH 1.1  7.0 V CLALV "L" input voltage VCLL 0  0.3 V CLALV "H" input current ICLH   1.0 µA VIH=5.5V CLALV "L" input current ICLL −100 −75 −50 µA VIL=0V RESET pin RESET "H" input voltage VREH 1.1  7.0 V RESET "L" input voltage VREL 0  0.3 V RESET "H" input current IREH   1.0 µA VIH=5.5V RESET "L" input current IREL −100 −75 −50 µA VIL=0V STB pin STB "H" input voltage VSTH VCC −0.3  7.0 V STB "L" input voltage VSTL 0  0.3 V STB "H" input current ISTH   3.0 µA VIH=5.5V STB "L" input current ISTL −150 −100 −50 µA VIL=0V HOLD C CH rapid charge current ICHQC −2000 −1000 −500 µA IPSD=5µA , VCH=0V CH stationary charge current ICHC −30 −20 −10 µA VCH=0V *1 CH stationary discharge current ICHD 10 20 30 µA VCH=1.5V *1

Rev.1.0, Sep.19.2003, page 5 of 13 Electrical characteristics (cont.) (Ta = 25°C, VCC = 3.0V, unless otherwise noted.) Limits Classification Parameter Symbol Min. Typ. Max. Unit Test conditions Note Double integration CINT rapid charge current ICINTC 84 120 156 µA VCI=1V (CINT stable period) CINT reference voltage VCINT 1.6 1.8 2.0 V GND criterion *1 The first integration current ICI1 4.06 5.80 7.54 µA VCINT=1.5V *1 The second integration current ICI2 −3.20 −2.46 −1.27 µA VCHF=2V , VCHN=0V The first integration current stability percentage ∆ICI1   10 % *2 The second integration current stability percentage ∆ICI2   10 % *2 The first and second integration current ratio ICI12 2.12 2.36 2.60 | ICI1 | / | ICI2 | AF output time(9:1)-1 D(9:1) - 1 11.78 13.40 15.02 msec Near side9 : Far side1 *3 AF input condition 1 AF output time(6:4)-1 D(6:4) - 1 7.77 8.95 10.13 msec Near side6 : Far side4 *3 AF output time(3:7)-1 D(3:7) - 1 3.77 4.51 5.25 msec Near side3 : Far side7 *3 AF slope -1 ∆AF - 1 6.57 8.89 11.21 msec *3 AF linearity-1 LAF - 1 0.9 1.0 1.1 *3 AF output time(9:1)-2 D(9:1) - 2 11.78 13.40 15.02 msec Near side9 : Far side1 *3 AF input condition 2 AF output time(6:4)-2 D(6:4) - 2 7.77 8.95 10.13 msec Near side6 : Far side4 *3 AF output time(3:7)-2 D(3:7) - 2 3.77 4.51 5.25 msec Near side3 : Far side7 *3 AF slope -2 ∆AF - 2 6.57 8.89 11.21 msec *3 AF linearity-2 LAF - 2 0.9 1.0 1.1 *3 AF output time(9:1)-3 D(9:1) - 3 11.78 13.40 15.02 msec Near side9 : Far side1 *3 AF input condition 3 AF output time(6:4)-3 D(6:4) - 3 7.77 8.95 10.13 msec Near side6 : Far side4 *3 AF output time(3:7)-3 D(3:7) - 3 3.77 4.51 5.25 msec Near side3 : Far side7 *3 AF slope -3 ∆AF - 3 6.57 8.89 11.21 msec *3 AF linearity-3 LAF - 3 0.9 1.0 1.1 *3 ∆AF output time(9:1) ∆D(9:1)   280 µsec Near side9 : Far side1 (Condition 1-2) AF input condition 1 minus 2 ∆AF output time(6:4) ∆D(6:4)   280 µsec Near side6 : Far side4 (Condition 1-2) ∆AF output time(3:7) ∆D(3:7)   280 µsec Near side3 : Far side7 (Condition 1-2) Data SOUT leak current ISOUTL   1.0 µA VIN = 5.5V SOUT saturation voltage VSOUTS   0.3 V IOUT=500µA Sensor Signal light saturation current ∆INF 3.0   µA *4 Stationary light remove current IPSD   30 µA *4 Clamp level ICLAM −30  30 % Change quantity for Typ. current

Rev.1.0, Sep.19.2003, page 6 of 13

  • *1 : Set up the logic control terminal, correspond to the parameter.
  • *2 : Change ratio between the first integration current and the second integration current at a voltage of CINT that is {CINT reference voltage(VCINT)-0.1V} and 1V. The first integration current (CINT=1V ) The first integration current (CINT=VCINT-0.1V) The second integration current (CINT=1V ) The second integration current (CINT=VCINT-0.1V)
  • *3 : Connect the resistance of 120ΚΩ instead of PSD and establish current output from PHOTO COUPLER correspond to the parameter. And input the varied resistance ratio. And measure the pulse width of SOUT output at that time, obtain AFslope and AF linearity from the equations below. Input condition1: IPSD (Stationary light current)=0 I1+I2=100nA Input condition2: IPSD (Stationary light current)=0 I1+I2=50nA Input condition3: IPSD (Stationary light current)=10µA I1+I2=100nA D(9 : 1) •   The pulse width of SOUT output at input with I1:I2=9:1 D(6 : 4)    The pulse width of SOUT output at input with I1:I2=6:4 D(3 : 7)    The pulse width of SOUT output at input with I1:I2=3:7 AF slope : DAF = D(9 : 1) - D(7 : 3) AF linearity : L(AF) = (D(9 : 1) - D(6 : 4)) / (D(6 : 4) - D(7 : 3)) PSD quite resistance : 120KΩ
  • *4 : The input current of one side channel when stationary light remove circuit and I/V transform AMP is not saturated.

Rev.1.0, Sep.19.2003, page 7 of 13 Description of Pin UnitParameterCircuit diagram Test conditions and note "H"input voltage 1.1 7.0 0.3 1.0 -100 -50 -75 VCC -0.3 7.0 3.0 -150 -50-100 V µA VIH=5.5V VIL=0V VIH=5.5V VIL=0V V µA V µA 0.3 1.0 IOL=500µA VIN=5.5V Pin name HOLD INT CLALV RE SET STB SOUT 0.3 Limits Min. Typ. Max. "L"input voltage "H"input current "L"input current "H"input voltage "L"input voltage "H"input current "L"input current "L"output voltage "H"leak current

Rev.1.0, Sep.19.2003, page 8 of 13 Application Example CINT GND1 CHN SOUT PVcc IRED PSDN PSD RECKON BIAS NC TESTFCHF CLALV HOLDINT 9 10 MICROCOMPUTER Vcc GND2 PSDF 1.0µF 14 12 11 8 4 6 STB RESET 0.068µF 1.0µF TESTN NC STATIONARY LIGHT REMOVE PULSE WIDTH TRANSFORM (DOUBLE INTEGRATION) SEQUENTIAL CONTROL LOGIC CLAMP CIRCUIT I/V TRANSFORM AMP STATIONARY LIGHT REMOVE I/V TRANSFORM AMP HOLD HOLD CLAMP LEVEL SWITCHING HOLD REFERENCE VOLTAGE I1+I2 Controls (1) STB This terminal enables IC to operate. IC is Standby at HIGH in this terminal. IC can operate at LOW in this terminal. (2) RESET This terminal resets the whole IC including a logic. This terminal resets IC at HIGH. This terminal cancel resetting IC at the edge from HIGH to LOW. IC includes power on reset function. The control from external is also possible. The reset term in IC takes OR between power on reset and control signal from external. H L Indefiniteness Reset Reset canceled While this terminal is HIGH,dielectric divide pole countermeasures circuit of integration condenser is active.

Rev.1.0, Sep.19.2003, page 9 of 13 (3)CLALV This terminal sets up clamp level. As including D/A of 4bit, 16way clamp level setting is possible by inputting clock after reset is canceled(include none clamp). Set up current value of each bit is on the right table. The number of input clock and set up clamp level is as follows. bit Set up current (Typ.) 1 0.125 nA 2 0.25 nA 3 0.5 nA 4 1.0 nA Clock value Clamp level(Typ.)

0 None clamp

1 0.125 nA 2 0.250 nA 3 0.375 nA 4 0.500 nA 5 0.625 nA 6 0.750 nA 7 0.875 nA 8 1.000 nA 9 1.125 nA 10 1.250 nA 11 1.375 nA Clock value Clamp level(Typ.) 12 1.500 nA 13 1.625 nA 14 1.750 nA 15 1.875 nA

16 None clamp

17 0.125 nA 18 0.250 nA 19 0.375 nA 0.500 nA Clamp level is established with fall edge of input clock. It repeats the sam e value after 16 clock. (4) HOLD INT These terminals implement the following controls by inputting HIGH/LOW. a. CINT rapid charge ON , OFF b. CHrapid charge ON , OFF c. Stationary light hold ON , OFF d. The first integration ON , OFF e. The second integration ON , OFF Stationary light hold The first integration The second integration Reset canceled HOLD INT CINT rapid charge CH rapid charge

Rev.1.0, Sep.19.2003, page 10 of 13 a. CINT rapid charge After reset is canceled, the capacity of CINT is charged rapidly until INT terminal first falls. b. CH rapid charge After reset is canceled, the capacity of CH is charged rapidly until INT terminal first rises and falls. c. Stationary light hold After reset is canceled, holds the stationary light while HOLD terminal is HIGH. d. The first integration After reset is canceled, as HOLD terminal is HIGH and INT terminal is HIGH, the first integration is implemented while INT terminal is HIGH. Therefore, the first integration must be finished(INT terminal from HIGH to LOW) until stationary light hold will be completed (HOLD terminal from HIGH to LOW) e. The second integration After reset is canceled, the second integration is implemented as HOLD terminal is LOW and INT terminal is HIGH. And, the second integration is completed by exceeding judgment level of CINT terminal although INT terminal is HIGH. (5)SOUT When the second integration starts, This terminal becomes from HIGH to LOW. If CINT terminal exceeds judge level or INT terminal becomes from HIGH to LOW, this terminal becomes from LOW to HIGH. (notice)As the signal from microcomputer, the signal that controls IRED ON/OFF is required except for above mentioned control signals. But applying the timing of HOLD is available.

Rev.1.0, Sep.19.2003, page 11 of 13 Sequential Time Chart Example

Rev.1.0, Sep.19.2003, page 12 of 13 Mask Option (1) The second integration current value can be doubled.( 2.5µ5.0µA) (2) Control terminal variation

1 Full spec (typical)

S O U T C L A L V H O L D I N T 9 10 MICROCOMPUTER 11 8 S T B R E S E T Most simplified type S O U T H O L D I N T 9 10 8 This type uses CLALV,STB,RESET,INT,HOLD,SOUT terminal as I/F terminal to the microcomputer. This is the t ypical type at M52957AFP. This type does not connect CLALV,STB,RESET terminals to the microcomputer. When above mentioned terminals are not connected to the microcomputer without changing mask,connect each terminal to the ground. In this case,clamp level becomes 0 and standby function is lost. Power on reset in IC is used as reset. Explanation of the terminal that can be simplified.3 (a)CLALV In the typical type,16way clamp levels can be set by the external control,but also the terminal can be simplified by mask option as follows. (I) Clamp level fixation Selects 1 point from 16 steps of clamp level and fixes it. (II) Clamp level 2 step changeover Selects 2 points from clamp level and switches it by changing CLALV terminal HIGH/LOW. However,as selecting 2 points,there is a following constraint. Fixes 3 parts of 4 switches correspond to each bit in figure to ON or OFF,controls another part by CLALV terminal . 0.125nA 0.25nA 0.5nA 1.0nA MICROCOMPUTER (b)STB When no standby function required such as VCC is suitched ON/OFF, STB terminal can be eliminated. (c)RESET Since IC include power on reset circuit, RESET terminal can be eliminated, As merit of controlling RESET terminal from outside, distance detection time can be shortened because there is no need to switch VCC to STB terminal ON/OFF at consecutive distance detection.

Rev.1.0, Sep.19.2003, page 13 of 13 Package Dimensions SSOP16-P-225-0.65 Weight(g) JEDEC Code 0.06 Alloy 42 16P2E-A Plastic 16pin 225mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .170 .130 .94 .34 .26 .30 .01 .10 .151 .220 .150 .05 .44 .650 .46 .50 .01 .85 .20 .451 .320 .20 .15 .54 .66 .70 .10 —b2 — 0.35 0˚ — 10˚ e 16 9 HE E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail FDetail G z x —Z1 0.225 0.375 0.13 z G b x M

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