M52791SP RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • Video and stereo sound switches in one package
  • Wide frequency range (video switch): DC to 20 MHz
  • High separation (video switch): Crosstalk –60 dB (Typ) at 1 MHz
  • Two types of packages are provided: SDIP with a lead pitch of 1.778 mm (M52791SP); and SSOP with a lead pitch of 0.8 mm (M52791FP). Application Video equipment Recommended Operating Condition Supply voltage: 4.7 V to 9.3 V Rated supply voltage: 5 V, 9 V Maximum output current: 49 mA (at 9 V)

Rev.2.00 Sep 14, 2006 page 2 of 13 Block Diagram L-MODE R-MODE R M L R M L L-SW R-SW C-SW Y-SW V-SW N VCC 0/6 dB 0/6 dB 0/6 dB 0/6 dB 0 dB 0 dB 0 dB 0 dB 0 dB S N GND BIAS Lch 4 IN Lch 3 IN Lch 2 IN Lch T IN Rch 4 IN Rch 3 IN Rch 2 IN C 4 IN C 3 IN C 2 IN Y 4 IN Y 3 IN Y 2 IN VIDEO 3 IN VIDEO 4 IN VIDEO 2 IN TUNER IN Rch T IN Y/C SEP A V 1 OUT Y 1 OUT C 1 OUT Rch 1 OUT Lch 1 OUT Y 2 OUT C IN Y IN SDA SCL CHIP SELECT I2C ControlBIAS V 2 OUT24 C 2 OUT23 Y/C Sepa. 2219 DA

Rev.2.00 Sep 14, 2006 page 3 of 13 Pin Arrangement 8 29 9 28 10 27 11 26 12 25 13 24 14 23 15 22 16 21 17 20 18 19 (Top view) Outline: PRSP0036GA-B (36P2R-D) Lead pitch: 0.8 mm M52791FP VCC VIDEO 2 IN Lch 2 IN TUNER IN Lch T IN Rch T IN Y/C SEPA Lch 1 OUT Rch 1 OUT Y 1 OUT V 1 OUT C 1 OUT V 2 OUT CHIP SELECT SDA GND SCL Y 2 OUT C 2 OUT C IN Y IN C 2 IN Rch 2 IN Y 2 IN Y 3 IN VIDEO 3 IN Lch 3 IN C 3 IN Rch 3 IN Y 4 IN VIDEO 4 IN Lch 4 IN C 4 IN Rch 4 IN BIAS DA 8 29 9 28 10 27 11 26 12 25 13 24 14 23 15 22 16 21 17 20 18 19 (Top view) Outline: 36P4E Lead pitch: 1.778 mm M52791SP VCC VIDEO 2 IN Lch 2 IN TUNER IN Lch T IN Rch T IN Y/C SEPA Lch 1 OUT Rch 1 OUT Y 1 OUT V 1 OUT C 1 OUT V 2 OUT CHIP SELECT SDA GND SCL Y 2 OUT C 2 OUT C IN Y IN C 2 IN Rch 2 IN Y 2 IN Y 3 IN VIDEO 3 IN Lch 3 IN C 3 IN Rch 3 IN Y 4 IN VIDEO 4 IN Lch 4 IN C 4 IN Rch 4 IN BIAS DA

Rev.2.00 Sep 14, 2006 page 4 of 13 Pin Description Pin No. Name Peripheral Circuit Pins DC Voltage (V) Remarks

1 V CC — 9 V 5 to 9 V

3.6 V Clamp in

29.6 k 30 k 4.7 V C 2 IN C 3 IN C 4 IN C IN 29.6 k 20 k 4.7 V 17 DA VOL max = 0.4 V At lin = 1 mA

18 BIAS

13.9 k 17.1 k 29.6 k 4.2 V

19 GND — —

20 SCL

VIL max = 1.5 V VIH min = 3.0 V

Rev.2.00 Sep 14, 2006 page 5 of 13 Pin No. Name Peripheral Circuit Pins DC Voltage (V) Remarks

21 SDA

VIL max. = 1.5 V VIH min. = 3.0 V VOL max. = 0.4 V At lin = 3 mA

22 CHIP SELECT

0 to 1.5 V: 90H 2.5 to V CC: 92H OPEN: 90H Y 1 OUT C 1 OUT V 1 OUT 5 k 5 k C OUT 4.0 V V OUT Y OUT SYNC CHIP DC = 2.9 V C 2 OUT V 2 OUT Y 2 OUT C OUT 3.3 V V OUT Y OUT SYNC CHIP DC = 2.2 V Rch 1 OUT Lch 1 OUT 1.5 k 1.5 k 1.5 k 4.0 V

31 Y/C SEPA

DC = 2.9 V

Rev.2.00 Sep 14, 2006 page 6 of 13 I2C Bus I2C Bus (Inter IC Bus) is multi master bus system developed by PHILIPS. Two wires (SDA-serial data, SCL-serial clock) realize functions of start, stop, transferring data, synchronization and arbitration. The output stages of device connected to the bus must have an open drain or open collector in order to perform the wired-AND function. MSB SCL SDA LSB LSB AA S 123456789 9 12 P MSB Note: S: Start condition, a high to low transition of the SDA line while SCL is high P: Stop condition, a low to high transition of the SDA line while SCL is high A: Acknowledge Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. Control This IC controls 2-channel switches with 2-byte data (DAT A1 and DATA2). Video switches are controlled by DATA1. Audio switches are controlled by DATA2. S S: Start A: Acknowledge P: Stop SLAVE ADDRESS A DATA1 A DATA2 A P Slave address 100100X0 R/W bit Usually "0" (W: Master transmitter transmits to slave receiver) Possible to select 22 pin High: 1, Low: 0

Rev.2.00 Sep 14, 2006 page 7 of 13 Data Byte Format M52791 FUNCTION TABLE S SLAVE ADDRESS A DATA (D7 to D0) A DATA (DF to D8) A P SLAVE ADDRESS A6 A5 A4 A3 A2 A1 A0 R/W SLAVE ADDRESS 1 0 0 1 0 0 0/1 0 DATA1 (D7 to D0) CONT D7 D6 D5 D4 D3 D2 D1 D0 DATA CONT

0 FIX 0 FIX SEPA AMP Y/C AMP V AMP1 S/N VIDEO SW CONT

S/N (S:1) V-SW D2 D1 D0 V OUT Y/C SEPA Y OUT C OUT 0 0 0 T IN Y IN C IN 0 0 1 V 2 IN Y IN C IN 0 1 0 V 3 IN Y IN C IN 0 1 1 V 4 IN Y IN C IN 1 0 0 Y/C MIX T Y IN C IN 1 0 1 Y/C MIX 2 Y 2 IN C 2 IN 1 1 0 Y/C MIX 3 Y 3 IN C 3 IN 1 1 1 Y/C MIX4 Y 4 IN C 4 IN AMP GAIN CONT DATA AMP DATA AMP DATA AMP D5 SEPA AMP D4 Y/C AMP D3 V AMP 0 0 dB 0 0 dB 0 0 dB 1 6 dB 1 6 dB 1 6 dB DATA2 (DF to D8) CONT DF DE DD DC DB DA D9 D8 DATA CONT AUDIO MODE 0 FIX 0 FIX 0 FIX I/O AUDIO SW CONT AUDIO SW CONT MODE MUTE R/R L/L NORMAL DATA OUT OUT OUT OUT D9 D8 Lch OUT 1 Rch OUT 1 Lch OUT 1 Rch OUT 1 L ch OUT 1 Rch OUT 1 Lch OUT 1 Rch OUT 1 0 0 MUTE MUTE Rch T IN Rch T IN Lch T IN Lch T IN Lch T IN Rch T IN 0 1 MUTE MUTE Rch 2 IN Rch 2 IN Lch 2 IN Lch 2 IN Lch 2 IN Rch 2 IN 1 0 MUTE MUTE Rch 3 IN Rch 3 IN Lch 3 IN Lch 3 IN Lch 3 IN Rch 3 IN 1 1 MUTE MUTE Rch 4 IN Rch 4 IN Lch 4 IN Lch 4 IN Lch 4 IN Rch 4 IN

Rev.2.00 Sep 14, 2006 page 8 of 13 I/O CONT DATA OUT DA DA OUT

0 HIGH

1 LOW

Rev.2.00 Sep 14, 2006 page 9 of 13

Electrical Characteristics

(Ta = 25°C, VCC = 9 V, unless otherwise noted) Item Symbol Min Typ Max Unit Test Condition Supply voltage V CC 4.7 — 9.3 V — 49 64 V CC = 9 V, Vin = 0 Vp-p, Rl = ∞Ω Circuit current I CC — 42 55 mA VCC = 5 V, Vin = 0 Vp-p, Rl = ∞Ω Video –0.5 0 0.5 f = 100 kHz, 1 Vp-p (0 dB) (T →V1OUT) 5.5 6 6.5 f = 100 kHz, 1 Vp-p (6 dB) (T →V1OUT) –0.5 0 0.5 f = 100 kHz, 1 Vp-p (0 dB) (Y →V1OUT) Voltage gain G 5.5 6 6.5 dB f = 100 kHz, 1 Vp-p (6 dB) (Y→V1OUT) –2.0 0 2.0 f = 10 MHz/100 kHz, 1 Vp-p (0 dB) (T →V1OUT) –2.0 0 2.0 f = 10 MHz/100 kHz, 1 Vp-p (6 dB) (T →V1OUT) –2.0 0 2.0 f = 10 MHz/100 kHz, 1 Vp-p (0 dB) (Y →V1OUT) Frequency characteristics F –2.0 0 2.0 dB f = 10 MHz/100 kHz, 1 Vp-p (6 dB) (Y→V1OUT) 4 — — V CC = 9 V (0 dB) (T→V1OUT) 2 — — V CC = 5 V (0 dB) (T→V1OUT) 4 — — V CC = 9 V (0 dB) (Y→V1OUT) Dynamic range D 2 — — Vp-p VCC = 5 V (0 dB) (Y→V1OUT) f = 100 kHz Maximum with distortion <1.0% ZIC 14 20 26 (C, C 2, C3, C4) ZIV — — — Clamp in (T, V 2, V3, V4) Input impedance ZIY — — — kΩ Clamp in (Y, Y2, Y3, Y4) Crosstalk CT — –60 –54 dB f = 1 MHz, 1 Vp-p T →V1OUT (at V2 mode) Audio –0.5 0 0.5 f = 1 kHz, 1 Vp-p (V CC 9 V) (RT→R1OUT) Voltage gain G –0.5 0 0.5 dB f = 1 kHz, 1 Vp-p (VCC 5 V) (RT→R1OUT) Frequency characteristics F –1 0 1 dB f = 100 kHz/1 kHz, 1 Vp-p (R T→R1OUT) Total harmonic distortion THD — 0.01 0.05 % f = 1 kHz, 2 Vp-p, at 400 Hz HPE + 30 kHz LPF (RT→R1OUT) Dynamic range D 5.5 6.0 — Vp-p f = 1 kHz, Maximum with distortion < 0.5% (RT→R1OUT) Output DC offset voltage V OFF –20 0 20 mV (MODE: R T, R2, R3, R4→R1OUT) Input impedance Z1 22 30 38 k Ω (R T, R2, R3, R4, LT, L2, L3, L4) Crosstalk CT — -90 -84 dB 1 kHz, 1 Vp-p R T→R1OUT (at R2 mode) I2C Bus control signal Max. input high voltage V IH 3.0 — 5.0 Min. input low voltage V IL 0.0 — 1.5 Low level output voltage (SDA) VOL 0.0 — 0.4 V SDA = 3 mA High level input current I IH –10 — 10 SDA, SCL = 4.5 V Low level input current I IL –10 — 10 µA SDA, SCL = 0.4 V SCL clock frequency f SCL 0.0 — 100 kHz Time of bus must be free before a new transmission can start t BUF 4.7 — — Hold time at start condition t HD; STA 4.0 — — The low period of the clock t LOW 4.7 — — The high period of the clock tHIGH 4.0 — — Step-up time for start condition tSU; STA 4.7 — — µs

Rev.2.00 Sep 14, 2006 page 10 of 13 Electrical Characteristics (cont.) (Ta = 25°C, VCC = 9 V, unless otherwise noted) Item Symbol Min Typ Max Unit Test Condition Hold time DATA t HD; DAT 5.0 — — Setup time DATA t SU; DAT 250 — — Rise time of both SDA and SCL line tR — — 1000 Fall time of both SDA and SCL line tF — — 300 ns Setup time for stop condition tSU; STO 4.0 — — µs I2C Bus Control Signal SDA SCL tBUF tR tHD; STA tLOW tHIGH tHD; DAT tSU; DAT tSU; STA tF tHD; STA tSU; STO PSrSP

Rev.2.00 Sep 14, 2006 page 11 of 13 Application Circuit Example VCCVIDEO 2 INVIDEO 3 INVIDEO 4 IN M52791SP I/O Expand I2C IN TUNER IN OUT 1 OUT 2 0.01 µF 100 µF 0.47 µF 0.01 µF 10 µF 10 µF 75 Ω 75 Ω 0.47 µF 75 Ω 0.47 µF 0.01 µF 10 µF 10 µF 75 Ω 75 Ω 0.47 µF 75 Ω 0.47 µF 0.01 µF 10 µF 10 µF 75 Ω 75 Ω 0.47 µF 75 Ω 220 Ω 5 V 10 kΩ220 Ω 5 V 10 kΩ 75 Ω 0.47 µF 0.47 µF+ 10 µF 10 µF 0.01 µF+ 10 kΩ 10 µF +75 Ω 75 Ω 75 Ω 75 Ω + + +75 Ω 75 Ω Slave address change (VCC/GND) VCC VIDEO 2 IN VIDEO 3 IN Lch 2 IN Lch 3 IN Rch 2 IN C 2 IN Y 2 IN VIDEO 4 IN Lch 4 IN Rch 4 IN C 4 IN Y 4 IN Rch 3 IN C 3 IN Y 3 IN DA BIAS TUNER IN Lch T IN Rch T IN C IN Y IN SDA SCL GND Y/C SEPA Lch 1 OUT Rch 1 OUT V 1 OUT C 1 OUT Y 1 OUT V 2 OUT CHIP SELECT Y 2 OUT C 2 OUT Y/C Sepa.

Rev.2.00 Sep 14, 2006 page 12 of 13 Note How To Use This IC

  • Input signal with sufficient low impedance to input terminal.
  • The capacitance of output terminal as small as possible.
  • Set the capacitance between VCC and GND near the pins if possible.
  • Assign an area as large as possible for grounding. Power-on Reset
  • The M52791 has an internal power-on reset function that sets each control register to "0" during IC power ON.
  • The power-on reset VTH has 2.5 V.

Rev.2.00 Sep 14, 2006 page 13 of 13 Package Dimensions bp HE y 0.10 e 0.8 c 0° 8° L 0.3 0.5 0.7 0 0.1 0.2 A 2.35 11.63 11.93 12.23 A2 2.05 E 8.2 8.4 8.6 D 14.8 15.0 15.2 Reference Symbol Dimension in Millimeters Min Nom Max 0.3 0.35 0.45 0.18 0.2 0.25 P-SSOP36-8.4x15-0.80 0.5g MASS[Typ.] 36P2R-DPRSP0036GA-B RENESAS CodeJEITA Package Code Previous Code 0.65 0.95 DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. y Index mark 1 18 1936 F E HE D e bp A c Detail F L

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