M52766FP

M52766FP RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 7tENESAS Renesas Technology Corp.

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF

DESCRIPTION

The MS52766FP is a semiconducttor IC with PLL system of | PIN CONFIGURATION (TOP VIEW) Mies SIF. ie 7 - ‘i EQ OUT[4] EQF/B The circuit includes video UF amplifier, PLL video YVIDEOINV.OUT detector, IFAGC, RFAGC,VCO,AFT,LOCK See TER reo etector, Q UNCOATTS APC FILTER RF AGC DELAY DET,EQ,REG,QI|Famplifier,QIF detector,QIF AGC,LIM,FM EQ IN [at VIF IN detector function. : 7 ; vec = VIF IN The circuit realize no abjustment SIF nothing coil AFT. vco COILfé] S GND FEATURES VCO COIL[7} g AFT OUT ® Dynamic AGC realizes high speed AGC with double filtre. IF AGC FILTER[ 8] 4 RF AGC OUT ® The M52766FP can correspond to 2tipe sound career, from VIDEO OUTLg] QIF DET IN change on standard board, with sound LIM input have QIF OUT EO} NFB 2pins (12,13pin). GND AUDIO OUT @ Sound FM detection can correspond to wide SIF signal, with} LIMITER IN (NTSC) LIMITER IN(PAL) PLL system and no abjustment. e The N52766FP correspond to PLL split system and APPLICATION intercareer system. ® AFT coil is necessary. TV sets, VTR tuners. © AFT mute is not used. @ The M52766FP optimum for VTR and color TV, with video RECOMMEND OPERATING CONDITION output-pin,because this IC has a builtin EQ amplifier. @ VCC correspond to 5V,be main strem of tuner in future. Supply voltage range *¢ * * 5.0+0.25V © Flat package is 24-pin SSOP of mini flat (0.8mm pich ), Recommended supply voltage * * * 5.0V suitable for space saving. BLOCK DIAGRAM IF Ne RF AGC = Delay EL 4 tr ~ Veo af RF AGC AF OUT |~ é + ef are z OUT 00) © a OUT, ka if £ = [24] [23] fol fis] f7] fe] 4] (Ue FMDET AMP VIDEO UMAMP i | ox] QIF DET eo La] [3] Ist [6] Is} lol fol a Le) EQ OUT a + Ceo | an 00} OO hs oe —— ¥IDEO OUT 4.5MHz Filter 4.5MHz Trap 2ENESAS (1/15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF Absolute maximum ratings (Ta = 25°C, unless otherwise noted ) Supply Vv Vv Voltage 1 ve Consumption [e) ti peraing Topr | -20 to +75 °c Temperature St 40 to +150 Temperature ‘surge protection wit ee = resistance resistance 02 * There is not all pins problem about surge, but the case of use pay attention about latch up because the ninth pin is weak a few. Temperature Characteristics ( maximum ratings ) Mounting in standard circuit board _ 1750 2 | | | fl | € 1500 F ee ee B 750 [Sai Q Pe 8 ee ee & (e) < -20 0 25 50 75 100 125 150 Ambient temperature Ta (°C ) Recommended Operating Condition ( Ta = 25°C, unless otherwise noted ) Supply Voltage Range (Vcc) e*e*e* 4.75 to 5.25V Rated Supply Voltage (Voc) e*eee* 50V 2tENESAS (2/15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF Electrical Characteristics (Vcc=5V,Ta=25°C unless otherwise noted) VIF Section Parameter |Symbol Test | Test Input Input | switches set to positon 1 Unit |Note' Circuit| Point | Point) SG _ | unless otherwise noted MIN | TYP | MAX Cireult Current 1 | joey A SW5=2 40 | 56 | 72 | ma Veo=5V Video Output swa23=2 DC Voltage 1 Pw fa fen]-|- | gee forlesfoe|v| | Video Output VIF 3 | Voltage 9 Vo det | tes | iy | SGI 085 1.35 | Vp-p Video Output Vo det mia | VIF) ogy 177| 21 | 243 | Vp-p Voltage 1 IN 5 |Video SIN vee tes | VIF | seo swiz2 s1 | 56 SIN IN Video Band Width} BW tea | VIF | ggg] SW23-2 50 | 70 MHz| 2 IN V23=Variable VIN VIF TPIA — pm ffs] | sof f= [a | [een] 9 | Maximum Allowable | VIN VIF TPIA By AGC Control Range Input GR 20 a 5 Maximum IF AGC Vo3H p23 435 | 4.75 Vv Voltage 1 Valage tn vest o wees we] sor] | 200 [2am ano] v | Voltage 1 IN 13 Maximum RF AGG VI7H TP17 VIF sae 413 | 4.75 v Voltage IN Minimum RF AGC| VIF 01] 05] Vv RFAGC VIF Delay Point fe | + [re] ME] sof | me | | a foe | o aaa nhl pau] sos] we] scof | oo | 5 | ~ fame ’ u IN 0 s ina farfs|-|-[-| esos] - [ae ° T 7tENESAS (3/15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF Limits Test | Test | Input 4 Parameter |Symbol| = Pt Input switches set to position 1 Unit /Note} Circuit) Point | Point | SG | uniess otherwise noted TYP | MAX Wy 29 [AFT Maximum | vig | 1 |tpis | VIF | gato 3.85 | 415 Vv | 10 Voltage IN 4 [AFT Minimum Vi8L tpis | VF | sato o7 | 12]| Vv | 10 Voltage IN AFT VIF APT defeat fails fmwfw]- | |eefaslasly| | VIF SW23=2 IM 1 | TPIA 33 | 40 W Inter Modulation pe + from] we | sen V28=Variable Boewo Differential VIF DG 2, 5 | % Differential VIF v9 VIF iS tip level TPIA v 26 | Sync. tip level cl + | IN SG2 0.95 | 1.35 | 1.75 27 | VIF Input RINV| 2 | TP20 1.2 ka Resistor VIF Input 2 5 ony’ | 2 lire P| | fe [| - foe | Maximum IF AGC VIF 30 Voltage 2 v8 TPS IN 3.80 | 4.25 v Minimum IF AGC VIF 31 | voltage 2 ve | 1 | 1P8 | iy | SG7 1.95 | 225) 255) V Video Inversion | Yo det VIF Output Voltage vega] [ome [we sor] [oa] os [o75|vo0 Control Section Measurement Limits Test | Test Input F Parameter |Symbol| ~~ | switches set to position 1 Unit |Note| y Circuit] Point SG__| unless otherwise noted | win | ave [ max’ QIcontrol Loor| + |r| - | - | Swi6=2 | orf vol v ® 2tENESAS (4/15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF Electrical Characteristics (Vcc=5V,Ta=25°C unless otherwise noted) SIF Section Parameter |Symboll Test F Test Input | switches set to position 1 Unit |Note| Circuit] Point SG__| unless otherwise noted TYP | MAX QIF Output VIF IN| s@2 IFA 1 | TP10 QIF Output VIF IN| SG2 QiF2 | 1 | TP10 94 106 | dB

35 Voltage 2 QIF IN| SG14 tn

36 | SIF Detection vos | 1 | tP10| VIF | sais Swi6=2 94 dB Output IN V16=0V AF Output SIF val 1 DC Voltage pm | + [rew| Sf |soo) as fan far) v | | AF Output VoAF SIF SW13=2 vi 38 (4 5MH2) 1 1/114 | ‘| Sats 571 | 800 | 1142 |mvims AF Output VoAF SIF Sw2=2 39] 5 sua) 2 1 |TP14 | SV | saat SwWi2-2 521 | 730 | 1043 |mvims AFOt Di THD AFOutput Distortion | THD SIF SW2=2 a a] (5.5MHz) aro | 1 |TPI4| Sy | saat eWine % Limiting Sensitivity) LIM SIF 1 | TP14 SGI7 = 42) a SMH) ; IN SW13=2 42 | 55 |dBp | 12 Limiting Sensitivity} LIM 1 |rpia| SF | sano sw2=2 43) (6 5MHz) 2 IN swi2-2 42 | 55 | dBy AM Rejection AMR. SIF 1 | TP14 sais SW13=2 13 a (4.5MHz) 1 IN 53 | 62 45 |AM Rejection AMR | 4 | qpia| SIF | sana sw2-2 Pr 13 (5.5MHz2) 2 IN SW12=2 AF SIN (4.5MHz) | AF 1 |rpia| SF | sero SW13=2 53 | 62 4 SIN1 IN 47 |AFSN(G5MHz) | eny| 1 {P14 | SF | soo Sweee 54 4 SIN2 IN SW12=2 Resistor SIF Input cins | 2 | TPi6 4 pF Capacitance 7tENESAS (5/ 15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF Measuring Circuit Diagram 1 VIF IN a Ll Ll I LL Lk | FQ) £51 Veo CU) L, — Veg, t ~— [ yo ° 4 150K: vied £ = 33kz | TP18 42 TPAA 1“ f H 2 O41 | 2Q 04 o22u,_ Um | 150K TPi7 POU 5 27 ca fe) [ swi3 TP2: 1 20K f lig |_| Se oi ot QIF DET G —_— La fe es eee LU] [4] Ls] [2] biol i? a 2) Ya swe a i - io fe) o Swi2 a | | TP8 Swi 6 We yea a | a) 0 i Lt TPI0 7 2 1S 92 3 gu ba 1K if 5549 15u ofl G (@ 330 TPA TP2 wr es 9 TPS F —) 470 Cy) =51 a ie 4.5M Trap sw5 } 0 O Veo P) a * All capacitor is 0.01pF, unless otherwise noted. * The Measuring Circuit 1 is Mitsubishi standard evaluation fixture. 7tENESAS (6 / 15)

MITSUBISHI ICs (TV) M52766FP PLL SPLIT VIF/ SIF Measuring Circuit Diagram 2 Lil Xl RX Lod Rx LoO meter HiO meter HiO t Tr fea] [as] fad [aa] aol_ftol__—fre]_ fz] fre]_ fs] fra] tg Peat beep | | oo oT Yd a Cae oe eo eae L | tft | Vee x All capacitor is 0.01pF, unless otherwise noted. 7tENESAS (7/15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF INPUT SIGNAL fe [to se7ewhz eowvow fe[ to = Sa7eMiz Ow leveivarele |e | 1 = Frequency Variable AM20 KHz 77.8% 90dBu | ae ee 1 f2 - 55.17 MHz 80dBu Cw \\ Mixed Signal £3 = 54.25 MHz 80dBu Cw 2 Syne Tip Level 90 dBuy 2ENESAS (8/15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF Notes 1. Video S/N Input SG2 into VIF IN and measure the video out(Pin 1) noise in r.m.s at TP1B through a 5MHz (-3dB) L.P.F. e/N=20 | ( 0.7xVodet NOISE [dB] 2. Video Band Width: BW 1. Measure the 1MHz component level of Video output TP1A with a spectrum analyzer when SG3(f2=57.75MHz) is input into VIF IN. At that time, measure the voltage at TP23 with SW23, set to position 2, and then fix V23 at that voltage. 2. Reduce fz and measure the value of (f2-fo) when the (f2-fo) component level reaches -3dB from the 1MHz component level as shown below. TPIA 208 a : (f2- fo)

1 MHz BW

3.__ Input Sensitivity: VIN MIN Input SG4 (Vi=90dBy) into VIF IN , and then gradually reduce Vi and measure the input level when the 20KHz component of Video output TP1A reaches -3dB from Vo det level. 4._ Maximum Allowable Input: VIN - MAX 1. Input SG5 (Vi=90dBy) into VIF IN , and measure the level of the 2OKHz component of Video output. 2. Gradually increase the Vi of SG and measure the input level when the output reaches -3dB. 7tENESAS (9 / 15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF 5. AGC Control Range: GR GR=VIN MAX -VIN MIN [dB] 6. RF AGC Operating Voltage: V17 Input SG8 into VIF IN and gradually reduce Vi and then measure the input level when RF AGC output TP17 reaches 1/2 VCC, as shown below. TP17 Voltage Vi7H | VA7L Vi Vi(dBy) 7. Capture range: CL -U 1. Increase the frequency of SG9 until the VCO is out of locked-oscillation. 2. Decrease the frequency of SG9 and measure the frequency fU when the VCO locks. CL-U=fU - 58.75 [MHz] 8. Capture range: CL -L 1. Decrease the frequency of SGQ until the VCO is out of locked-oscillation. 2. Increase the frequency of SG9 and measure the frequency fL when the VCO locks. CL -L = 58.75 - fL [MHz] 9. Capture range: CL - T CL-T=CL-U+CL-L [MHz] 7tENESAS (10 / 15}

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF 10. AFT sensitivity p, Maximum AFT voltage VisH , Minimum AFT voltage Vis_ 1. Input SG10 into VIF IN , and set the frequency of SG10 so that the voltage of AFT output TP18 is 3[V] . This frequency is named f(3). 2. Set the frequency of SG10 so that the AFT output voltage is 2[V]. This frequency is named f(2) 3. IN the graph, maximum and minimum DC voltage are VisH and ViaL, respectively. TP2 Voltage 1000 [mV] View | y= [mV/kHz] : (2) - (8) [kHz] A ee (3) (2) f(MHz) 11. Inter modulation: IM 1. Input SG11 into VIF IN, and measure video output TP9 with an oscilloscope. 2. Adjust AGC filter voltage V23 so that the minimum DC level of the output waveform is 1.0V. 3. At this time, measure TP9 with a spectrum analyzer . The inter modulation is defined as a difference between 0.92MHz and 3.58 MHz frequency components. 7tENESAS (11/15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF 12. Limiting Sensitivity: LIM 1. Input SG17 (SG22) into SIF input, and measure the 400Hz component level of AF output TP 14. 2. Input SG20 (SG25) into SIF input, and measure the 400Hz component level of AF output TP14 . 3. The input limiting sensitivity is defined as the input level when a difference between each 400Hz components of audio output (TP 14) is 30dB, as shown below. Audio Output, (m¥ims, ¢ Audio output while SG17 (SG22) is input. 30dB Audio output while SG20 (SG25) is input. nai (dBy) SIF Input 13._AM Rejection: AMR 1. Input SG18 (SG23) into SIF IN ,and measure the output level of Audio output (TP12). This level is named VAM. 2. AMR is; AMR = 200g ( VOAF (rVr.m.s) | VAM (mVr.m.s) J [dB] 14. AF S/N: AF S/N 1. Input SG19 (SG24) into SIF input ,and measure the output noise level of Audio output (TP 14). This level is named VN. 2. S/N is; WORE . enieeoes (tose ovis __} VN (mVr.m.s) [dB] 15. QIF Control: Cair Lower the voltage of V16 ,and measure the voltage of Vi6 when DC voltage of TP10 begins to change. 7tENESAS (12 / 15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF Structure of package (Cross section) Structure Outer Passivation Inner Lead Plating Pellet Wire Die Bond Lead Flame Back Metalize Lead Flame A Lead Flame Plastic Molding Matrrial Mold resin : Epoxy resin Internal lead : Au wire@ 25um) External lead plating : Solder plating Lead frame : Copper alloy Passivation : Nitride coat Manufacturing place (Wafer process,assembly,final inspection) Mitsubishi Electric Corporation Fukuoka Semiconductor Factory Indications Model Number ae -M52766FP XXXXXX O Mark lot number Lot number constitution The a 08) of the year | Production Running number 2, weekly code factory code (12th week) 7tENESAS (13 / 15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF Package specification IC package : 24P2Q In case of tube shipping In case of emboss tape shipping Tube : 50 pieces / tube (The’ direction of'T1) Interior box : 5000 pieces / interior box Reel : 2000 pieces / reel (100 tubes / interior box) Interior box : 1 reel/ interior Exterior box : 20000 pieces / exterior box Exterior box : 10000 pieces / exterior box (4 interior boxes / exterior box) (5 interior boxes / exterior box) The packing method in case of tube shipping 1. Container tube

1.1 Container tube size

(1) IC tube MPO16PC ’ (2) Stopper plug A cross section o 6.4 Width : 5.5 vt Color : Gray Total length | 550 | Stopper plug Unit : (mm) 7tENESAS (147 15)

MITSUBISHIICs (TV) M52766FP PLL SPLIT VIF/ SIF

1.2 Packing method

(1) The packing direction of the device. (Facing the Pin No.1 with the marking side as shown below.) oma == Pin No.1 Rohe marking side of the tube (2) The prevention of the vibration damage. The stopper plug is pushed into the tube so that devices should not move and are kept plain condition. Take care they do not warp. (3) In case of a fraction * In case IC number does not fill the typical accommodations, the stopper plug is used to fix devices. *"PARTIAL"label is stuck on the fraction tube as shown below. a | |rantiaf ss | | — ee 4h A position of the stopper plug. 2. Interior box and exterior box 2.1 The arrangement of tubes in the interior box. Nine lines and twelve steps c~) © ca ho | One line is in top step. oe : A T17 Unit (mm)

2.2 Damp proof packing

Use the specified PE bag and put a silica gel in it. * Put the sealed interior box in a PE bag. * Put the silica gel on the top step in the box. 7tENESAS (15 / 15)