M52390FP RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: pROVIDED bY alldatasheet.com(free datasheet download site)
  • PDF pages: 23

Technical content

Features

  • RGB encoder-related  Built-in LPF for color discrimination. An external resistor enables cutoff frequency control.  An internal VCA circuit enables gain control of the chroma unit.  A high-precision modulation circuit and clamping circuit realize low carrier leaks.  Burst and synch signals are generated in the IC.
  • Superimpose-related  YS IN (control input) enables switching between two input signals, VIDEO IN and RGB IN.  An internal high-speed analog switch makes it possible to insert fine text.  An internal APC circuit automatically adjusts the color phases of new screen (VIDEO IN) and RGB encoder signals.
  • Overall  The VIDEO OUT signal is output at 2 VP-P, making it possible to configure a 75 Ω drive circuit with a single transistor.  Both NTSC and PAL are supported. Application
  • TVs, VCRs, monitors and other audio/video devices Recommended Operating Conditions
  • Power supply voltage range: 4.7 to 5.3 V
  • Recommended power supply voltage: 5.0 V

Rev.1.0, Sep.22.2003, page 2 of 22 Block Diagram Pin Configuration

Rev.1.0, Sep.22.2003, page 3 of 22 Description of Pin Pin no. Pin name Pin peripheral circuit Pin voltage Notes 1G N D 2 C.SYVC IN AC: Sync input VTH = 2.5 V ± 0.3 V

3 HHK

external resistor. Recommended value: HHK: 3/4H R = 91 k C = 270 p

4 OFFSET R

DC = 3.1 V External recommended value. C = 0.1 µ AC: Chroma Burst: 300 mVP-P External recommended value. L C NTSC : 15 µ 12P PAL : 10 µ 12P 5T R A P [15] Test mode output at 5 V [12] Hi: R-Y output [12] Lo: B-Y output [5] 5 V: Test mode setting [15] Pulse output

Rev.1.0, Sep.22.2003, page 4 of 22 Description of Pin (cont) Pin no. Pin name Pin peripheral circuit Pin voltage Notes

6 OFFSET B

DC: 3.1 V External recommended value C = 0.1 µ The free run frequency is set using the trimmer capacitor.

7 VCXO IN

DC: 3.2 V [7] 0 V: Carrier OFF

8 APC

DC: 3.3 V In Free Run mode: DC: 2.7 V β characteristic Frequency APC voltage External recommended values R = 1.5 k C1 = 0.01 µ C2 = 1 µ Clamping input (burst timing) External recommended value C = 4.7 µ

9 VIDEO IN

AC: VIDEO 1 VP-P Pedestal: 2.9 V [9] 0 V: Free Run mode setting

Rev.1.0, Sep.22.2003, page 5 of 22 Description of Pin (cont) Pin no. Pin name Pin peripheral circuit Pin voltage Notes

10 VIDEO

AC: VIDEO 2 VP-P Pedestal: 1.8 V

11 V CC DC: 5 V Icc: 50 mA

VTH = 1.5 V ± 0.3 V Hi: RGB IN output Lo: VIDEO IN output 12 Ys Switching signal input when using Superimpose Hi: Insertion screen (RGB IN output) [15 Output setting when using 5 V [5] Output External recommended value C = 4.7 µ 13 VRE G DC: 2.1 V 14 Y IN AC: Y 0.5 V P-P Pedestal: 2.1 V AC: Y 1 VP-P Pedestal: 2.1 V

15 Y OUT

(5) Test mode output at 5 V Pulse output [12] 5 V: Test mode setting

Rev.1.0, Sep.22.2003, page 6 of 22 Description of Pin (cont) Pin no. Pin name Pin peripheral circuit Pin voltage Notes

16 B IN

AC: B 0.71 VP-P Sync: 2.9 V Clamping input (burst timing) External recommended value C = 4.7 µ

17 G IN

AC: G 0.71 VP-P Sync: 2.9 V Clamping input (burst timing) External recommended value C = 4.7 µ

18 R IN

AC: R 0.71 VP-P Sync: 2.9 V Clamping input (burst timing) External recommended value C = 4.7 µ

19 COLOR

CONT. DC: 2.5 V Color control for RGB encoder output

5 V: Chroma unit +2 dB

2.5 V: Typ.

0 V: Chroma unit –3 dB

20 fc. CONT. DC: 3.3 V fc of LPF can be adjusted using external resistor. External recommended value R = 30 k

Rev.1.0, Sep.22.2003, page 7 of 22 Absolute Maximum Rating (Unless otherwise noted, Ta = 25°C) Symbol Item Ratings Units Vcc Power supply voltage 7 V Pd Internal current consumption 620 (900) mW Topr Ambient operating temperature –20 to 75 °C Tstg Storage temperature –40 to 125 °C kθ Thermal derating (Ta = 25°C) 6.2 (9.0) mW/°C Note: Values in parentheses are the values when mounted on a typical PCB. Thermal Derating (Maximum Rating)

Rev.1.0, Sep.22.2003, page 8 of 22

Electrical Characteristics

(unless otherwise noted, Ta=25°C, Vcc = 5 V, SG2 = sync) LimitsNo. Symbol Item Measurement conditions Mea- sure- ment point Min. Typ. Max. Unit 1I CC1 Circuit current 1 NTSC MODE, [12] 5 V [11] 35 50 65 mA 2I CC2 Circuit current 2 NTSC MODE, [12] 5 V [11] 37 52 67 mA RGB IN Æ Y OUT 3 ER Matrix ratio R SG18: 1 Vp-p [15] 0.27 0.30 0.33 Vp-p 4 EG Matrix ratio G SG17: 1 Vp-p [15] 0.53 0.59 0.65 Vp-p 5 EB Matrix ratio B SG16: 1 Vp-p [15] 0.09 0.11 0.13 Vp-p 6 EY At RGB 100% Y level SG16, SG17, SG18: 0.71 Vp-p [15] 0.63 0.71 0.79 Vp-p

7 FR R IN Æ Y OUT

SG18: 500 kHz/5 MHz, 0.5 Vp-p CW, SW16, 17, 18:ON [2] 0 V (SG2: OFF) [15] –1.5 0 1.5 dB

8 FG G IN Æ Y OUT

SG17: 500 kHz/5 MHz, 0.5 Vp-p CW, SW16, 17, 18:ON [2] 0 V (SG2: OFF) [15] –1.5 0 1.5 dB

9 FB B IN Æ Y OUT

SG16: 500 kHz/5 MHz, 0.5 Vp-p CW, SW16, 17, 18:ON [2] 0 V (SG2: OFF) [15] –1.5 0 1.5 dB

10 VS1 Sync level 1 NTSC MODE [15] 257 286 315 Vp-p

11 VS2 Sync level 2 PAL MODE (SW13: ON) [15] 270 300 330 Vp-p

Y IN Æ VIDEO OUT 12 G Y Y IN Æ VIDEO OUT gain SG14: 500 kHz, 0.5 Vp-p CW, [12] 5 V [10] 10.5 12 13.5 dB

13 F Y Y IN Æ VIDEO OUT

SG14: 500 kHz, 0.5 Vp-p CW, [12] 5 V [10] –1.5 0 1.5 dB RGB IN Æ TRAP

14 D L(R-Y) Delay (R-Y) SG18: 1 Vp-p

[5] 210 310 410 ns

15 D L(B-Y) Delay (B-Y) SG16: 1 Vp-p

[5] 210 310 410 ns 16 G H(R-Y) Gain (R-Y) VCA: Hi SG18: 500 kHz, 0.5 Vp-p CW, SW4, 6, 17, 18: ON [5] 1 2 3.5 dB 17 G H(B-Y) Gain (B-Y) VCA: Hi SG16: 500 kHz, 0.5 Vp-p CW, SW4, 6, 17, 18: ON [5] 1 2 3.5 dB 18 G L(R-Y) Gain (R-Y) VCA: Lo SG18: 500 kHz, 0.5 Vp-p CW, SW4, 6, 17, 18: ON [5] –4.5 –3 –2 dB 19 G L(B-Y) Gain (B-Y) VCA: Lo SG18: 500 kHz, 0.5 Vp-p CW, SW4, 6, 17, 18: ON [5] –4.5 –3 –2 dB

Rev.1.0, Sep.22.2003, page 9 of 22 Electrical Characteristics (cont) LimitsNo. Symbol Item Measurement conditions Mea- sure- ment point Min. Typ. Max. Unit RGB IN Æ VIDEO OUT

20 V B1 NTSC burst level NTSC MODE

[12] 5 V [10B] 243 286 329 mVp-p

21 V B2 PAL burst level PAL MODE (SW13: ON)

[12] 5 V [10B] 255 300 345 mVp-p

22 V B3 PAL burst level

PAL MODE (SW13: ON) [12] 5 V [10B] –30 0 30 mVp-p

23 P PB PAL burst phase

PAL MODE (SW13: ON) [12] 5 V [10B] 82 90 98 deg 24 V R/B R/burst level ratio SG18: 0.71 Vp-p [12] 5 V [10B] 2.68 3.15 3.62 25 V G/B G/burst level ratio SG17: 0.71 Vp-p [12] 5 V [10B] 2.51 2.95 3.39 26 V B/B B/burst level ratio SG16: 0.71 Vp-p [12] 5 V [10B] 1.91 2.25 2.59

27 V C/B NTSC MODE carrier

[12] 5 V [10B] — –40 –28 dB

28 P R/B R/burst phase

SG18: 0.71 Vp-p [12] 5 V [10B] 96 104 112 deg

29 P G/B G/burst phase

SG17: 0.71 Vp-p [12] 5 V [10B] 233 241 249 deg

30 P B/B B/burst phase

SG16: 0.71 Vp-p [12] 5 V [10B] 339 347 355 deg VIDEO IN Æ VIDEO OUT

31 GVIO VIDEO IN Æ VIDEO

SG9: 500 kHz, 0.5 Vp-p CW, SW9: ON [12] 0 V, [2] 0 V (SG2: OFF) [10] 5 6 7 dB

32 FVIO VIDEO IN Æ VIDEO

SG9: 5 MHz, 0.5 Vp-p CW, SW9: ON [12] 0 V, [2] 0 V (SG2: OFF) [10] –1.5 0 1.5 dB SUPER IMPOSE

33 PDI RGB/VIDEO IN burst

SG9: 3.85 MHz, 286 mVp-p CW, SG12: 1 Vp-p [10B] –5 0 5 deg

34 VOS DC offset SG9: burst, 286 mVp-p CW,

SG12: 1 Vp-p [10] –20 0 20 mV MMV

35 HHK HHK width PAL MODE (SW13: ON)

[5] 5V [2] [15] 40 47 54 µs

36 BFPP BFP position (burst

position) [5] 5V [2] [15] 4.5 5.6 6.7 µs 37 BFPW BFP width (burst width) [5] 5V [15] 2.0 2.5 3.0 µs

Rev.1.0, Sep.22.2003, page 10 of 22 Electrical Characteristics Measurement Method Tables for the various modes (common to all tests) Mode Setting condition Function FREE RUN MODE VCXO FREE RUN PAL MODE Carrier phase for MOD R reversed at each 1H SUPER IMPOSE MODE [10] VIDEO OUT RGB ENCODE signal out VIDEO IN signal out TEST MODE MR TEST MODE MB TEST MODE DR TEST MODE DB [5] Color difference output MOD R-Y out MOD B-Y out DIFF R-Y out DIFF B-Y out TEST MODE P [10] PULSE output PAL MODE: BFP, HHK mix NTSC MODE: BFP V4, V6, V9, V16, V17, V18 Various pin voltages when SYNC is input to [2] (C. SYNC IN) (for clamping)

Rev.1.0, Sep.22.2003, page 11 of 22 Measurement method and method for computing limit values Meas. no. Measurement method and me thod for computing limit values Current flowing into [11] is measured. (8, 9)

Rev.1.0, Sep.22.2003, page 12 of 22 Measurement method and method for computing limit values (cont) Meas. no. Measurement method and me thod for computing limit values (15) (15) (17) (19)

Rev.1.0, Sep.22.2003, page 13 of 22 Measurement method and method for computing limit values (cont) Meas. no. Measurement method and me thod for computing limit values PPS = |PnH burst phase – P(n + 1)H burst phase| (25, 26) (29, 30)

Rev.1.0, Sep.22.2003, page 14 of 22 Measurement method and method for computing limit values (cont) Meas. no. Measurement method and me thod for computing limit values

Rev.1.0, Sep.22.2003, page 15 of 22 Measurement method and method for computing limit values (cont) Meas. no. Measurement method and me thod for computing limit values

Rev.1.0, Sep.22.2003, page 16 of 22 Test Circuit

Rev.1.0, Sep.22.2003, page 17 of 22 Usage Precautions (1) Typical values for input signals (2) Setting the Free Run frequency This IC generates the fsc by means of the VCXO circuit. Consequently, the VCXO oscillation frequency must always be set to fsc before the IC is used, by following the procedure outlined below. 1. Connect [9] (VIDEO IN) to GND, and set the Free Run mode. 2. Set the [2] (OFFSET R) voltage when SYNC was input to [4] (C. SYNC IN) to V 4, and apply a voltage of V4 = 0.5 V to [4] (OFFSET R). 3. Fix C.[2] (SYNC IN) in the High state. (5 V applied) 4. Adjust the output frequency of [5] (TRAP) to the trimmer capacitor of [7] (VCXO IN), and set it to fsc.

Rev.1.0, Sep.22.2003, page 18 of 22 (3) Setting the color difference LPF The frequency characteristic of the color difference LPF built into this IC can be set as shown in Fig. 1, using the [20] (fc CONT.) external resistor. When doing this, the group delay characteristic also changes, as shown in Fig. 2. (4) Setting Y DL The group delay characteristic of the color signal of the RGB encoder output changes in response to the [20] (fc CONT) external resistor, so Y DL should be set in such a way that the group delay characteristic is the amount of group delay obtained from the group delay characteristic of Fig. 2, with 40 ns added. Also, if the [6] (TRAP) circuit is being added, a further delay of +5 to +10 ns should be taken into consideration. (5) COLOR CONT characteristic The gain of the chroma unit can be set as shown in Fig. 3, using the [19] (COLOR CONT) applied voltage. (The burst amplitude is constant.)

Rev.1.0, Sep.22.2003, page 19 of 22 (6) The relationship between BFP and HHK The pulse width of BFP and HHK can be set as shown in Fig. 4, using the [3] (HHK) external CR. (7) Input pin drive Input pins [9], [16], [17], and [18] use clamp input, so they should always be driven with a low impedance. (8) Input/output relationship between SYNC and burst during the V cycle (9) V DL and YS DL settings when the SUPERIMPOSE mode is being used 1) V DL is used to adjust the timing of the RGB encoder signal and the VIDEO IN signal. 2) Y S DL is used to adjust the timing of the RGB encoder signal and the Ys IN signal. 3) When the timing is the same for C. SYNC IN, RGB IN, VIDEO IN and Ys IN, V DL and YS DL should be set using the amount of delay shown below as a guide. V DL = Y DL (item 4) + 10 (ns) YS DL = Y DL – 10 (ns)

Rev.1.0, Sep.22.2003, page 20 of 22 Application Example (1) Example showing RGB video signals being encoded in NTSC/PAL signal

Rev.1.0, Sep.22.2003, page 21 of 22 Application Example (2) Example showing RGB text signals superimposed on NTSC/PAL signals (*The values in brackets show what takes place when the RGB signals of a personal computer or other device are superimposed on NTSC/PAL signals as a sub-screen.) If signals delayed by approximately 350 nm after the text (*sub-screen) RGB signals are created directly, as Ys signals, Ys DL is not necessary. If RGB and Ys are at same timing, the delay time of Ys DL should be set to 350 ns (typical).

Rev.1.0, Sep.22.2003, page 22 of 22 Package Dimensions SOP20-P-300-1.27 Weight(g) JEDEC Code 0.26 Cu Alloy 20P2N-A Plastic 20pin 300mil SOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters HE .350 .180 .512 .25 .57 .40 .271 .10 .81 .40 .20 .612 .35 .271 .87 .60 .251 .627 .20 .12 .50 .250 .712 .45 .18 .80 .10 b2 0.76 0° 8° e 20 11 101 HE E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail FDetail G z x —Z1 0.585 0.735 0.25 z b x M G MMP

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