M52347SP | DigiCamel IC Datasheet

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M52347SP RENESAS | Alldatasheet

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PDF pages: 17

Technical content

Features

Low power consumption with supply voltage of 5 V
Capable of obtaining output information on whether to input synchronous signal, and on polarity
Output of clamp pulse
Equipped with V TIME GATE SW that enables selecting whether or not VD portion pulse is output from pin 14/15.
Equipped with CLAMP SW that enables switching the clamp pulse output position. Application Display monitor Recommended Operating Condition Supply voltage range: V CC = 4.5 to 5.5 V Rated supply voltage: V CC = 5 V Block Diagram CLAMP TIMING CLAMP SW GREEN IN GND COMP/H IN COMP/H DET V IN V TIME GATE SW V DETH.STATE V.STATE V.POL. H.POL. CLAMP+ OUT HD+ OUT VD+ OUT V S/S OUT V S/S IN HD− OUTVCC 20 19 18 17 16 15 14 13 12 11 10987654321 CLAMP GEN EDGE SW V.TIME GATE V.SYNC SEP SYNC SEP H SHAPE H DET LOGIC LOGIC V SHAPE V DET

Rev.2.00 Sep 14, 2006 page 2 of 16 Pin Arrangement M52347SP/FP (Top view) Outline: PRDP0020BA-A (20P4B) [SP] PRSP0020DA-A (20P2N-A) [FP] CLAMP SW GREEN IN GND COMP/H IN COMP/H DET V IN V TIME GATE SW V DET H.STATE V.STATE CLAMP TIMING V.POL. H.POL. CLAMP+ OUT HD+ OUT VD+ OUT V S/S OUT V S/S IN HD− OUT VCC

Rev.2.00 Sep 14, 2006 page 3 of 16 Absolute Maximum Ratings (Ta = 25°C, unless otherwise noted) Item Symbol Ratings Unit Supply voltage V CC 6.0 V Power dissipation Pd 1237.6 (SP), 827.8 (FP) mW Electrostatic discharge Surge ±200 V Operating temperature Topr −20 to +85 °C Storage temperature Tstg −40 to +150 °C

Electrical Characteristics

(Ta = 25°C, VCC = 12 V, unless otherwise noted) Relay Condition 468 1 6 2222 2111 2111 2111 2111 2111 2111 2111 2111 1121 1121 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 6 1 A DC DC *1, *2 *1, *2 DC DC DC DC DC DC TP Condition In put Pin Output pin Output waveform NoteSymbol Circuit current 1 OH 1 OL 2 OH 2 OL 18 OH 18 OL 19 OH 19 OL 14 OH 14 OL ICC Pin 1 output Hi level Pin 1 output Low level Pin 2 output Hi level Pin 2 output Low level Pin 18 output Hi level Pin 18 output Low level Pin 19 output Hi level Pin 19 output Low level Pin 14 output Hi level Pin 14 output Low level Item 40 53 66 mA V V V V V V V V V V 4.0 5.0 5.0 00 . 0 4 0 . 5 4.0 5.0 5.0 00 . 0 4 0 . 5 4.0 5.0 5.0 00 . 0 4 0 . 5 4.0 5.0 5.0 00 . 0 4 0 . 5 4.0 5.0 5.0 0 0.25 0.5 Limits UnitMin. Typ. Max. Input Condition 1 µs 50 kHz

1 VP-P

P-P1 µs 1 µs 50 kHz

0.2 VP-P

1.0 V P-P 1 µs 1 µs 50 kHz 1 µs 1 µs 50 kHz 1 µs 1 µs 50 kHz 1 µs 1 µs 50 kHz 1 µs 1 µs 50 kHz 1 µs 1 µs 50 kHz

0.6 VP-P

1 µs 1 µs 50 kHz 1 µs 1 µs 50 kHz

1.0 VP-P

0.2 V P-P 1 µs V Meas V Meas Notes: 1. The true value table depends on Table 1 2. 0.2 V P-P of input signal is equivalent to NON SYNC.

Rev.2.00 Sep 14, 2006 page 4 of 16 Electrical Characteristics (cont.) 4.0 4.0 4.0 4.0 0.2 2.8 1.0 5.0 0.25 5.0 0.25 5.0 0.25 5.0 0.25 3.1 1.3 5.0 0.5 5.0 0.5 5.0 0.5 5.0 0.5 3.4 1.6 V V V V V V V V V P-P V V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 2.0 2.5 3.0 V 2 1 1 1 Relay Condition 468 1 6 3 1 0 TP Condition In put Pin Output pin Output waveform NoteSymbol 15 OH 15 OL 17 OH 17 OL 13 OH 13 OL 12 OH 12 OL SS-LV V3H V3L V10 Pin 15 output Hi level Pin 15 output Low level Pin 17 output Hi level Pin 17 output Low level Pin 13 output Hi level Pin 13 output Low level Pin 12 output Hi level Pin 12 output Low level Sync-Sep Sync input signal Max. noise amplitude voltage Sync-Sep Sync input signal Min. amplitude voltage CLAMP SW threshold voltage H CLAMP SW threshold voltage H variable V TIME GATE SW threshold voltage variable Item Limits UnitMin. Typ. Max. Input Condition 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 5 V Vari- able Vari- able Vari- able 1 µs 50 kHz 1 µs 1 µs 50 kHz P-P1 µs 1 µs 50 kHz P-P1 µs 1 µs 50 kHz P-P1 µs 50 kHz

2 VP-P

1 µs 50 kHz 1 µs 1 µs 50 kHz 1 µs

3 DC voltage must be

applied. No pulse must be output. No pulse must be output in this portion. 50 kHz 1 µs 50 kHz P-P1 µs 1 µs 50 kHz

0.05 VP-P

1 µs 50 kHz 1 µs 50 kHz applied. DC voltage must be applied. 14, 17 1 µs 50 kHz 1 µs 50 kHz 1 µs 50 kHz 14, 17 V Meas V Meas V Meas V Meas V Meas V Meas V Meas V Meas 5 V1221VP-P0.05SS-NV Notes: 3. Must not operate when input amplitude is 0.05 V P-P or less. (Pseudo noise signal) 4. Must operate when the input amplitude is 0.2 V P-P or more. 5. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then measure the voltage when the output pulse is not output. 6. Checking output pulse for output with a voltage of 0 VDC applied, increase the DC voltage and then measure the voltage when the output pulse is not output. 7. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then measure the voltage when the output pulse becomes narrow.

Rev.2.00 Sep 14, 2006 page 5 of 16 Electrical Characteristics (cont.) 250 3.0 1.3 120 140 120 120 100 150 130 400 100 3.5 1.8 350 350 350 350 350 350 350 350 350 350 350 550 350 350 4.0 2.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns V V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 0 V 0 V Relay Condition 468 1 6 3 1 0 TP Condition In put Pin Output pin Output waveform NoteSymbol HD+-DA HD+-DB HD+-DC HD+-DD HD−-DA HD−-DB HD−-DC HD−-DD CP+-DA CP+-DB CP+-DC CP+-PW VD+-DA VD+-DB V11H V11L HD+-delay time (A) HD+-delay time (B) HD+-delay time (C) HD+-delay time (D) CP+-delay time (A) CP+-delay time (B) VD+-delay time (A) VD+-delay time (B) V Sync-Sep threshold voltage H V Sync-Sep threshold voltage L CP+-delay time (C) CP+-PULSE- WIDTH HD−-delay time (A) HD−-delay time (B) HD−-delay time (C) HD−-delay time (D) Item Limits UnitMin. Typ. Max. Input Condition 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 2.5 V 5 V 0 V 5 V 0 V 5 V 0 V 5 V 0 V 5 V 0 V 5 V 0 V 5 V 0 V 5 V 1 µs 50 kHz P-P1 µs 1 µs 50 kHz P-P1 µs 1 µs 50 kHz 1 µs 1 µs 50 kHz P-P1 µs 1 µs 50 kHz 1 µs 1 µs 50 kHz P-P1 µs 1 µs 50 kHz P-P1 µs 1 µs 50 kHz P-P1 µs 1 µs 50 kHz P-P1 µs 1 µs 50 kHz P-P1 µs 1 µs 50 kHz 1 µs 1 µs 50 kHz 1 µs 1 µs 50 kHz applied. 1 µs 50 kHz applied. 8 1 µs 50 kHz 8 1 µs 50 kHz Input 6 (50%) Output 14 (50%) Input 6 (50%) Output 14 (50%) Time Meas Time Meas Input 8 (50%) Output 13 (50%) Input 8 (50%) Output 13 (50%) Time Meas Time Meas Input 6 (50%) Output 17 (50%) Time Meas Input 6 (50%) Output 17 (50%) Time Meas Input 4 (50%) Output 17 (50%) Output 17 (50%) Time Meas Time Meas Input 4 (50%) Output 14 (50%) Input 4 (50%) Output 14 (50%) Time Meas Time Meas Input 6 (50%) Output 15 (50%) Input 6 (50%) Output 15 (50%) Time Meas Time Meas Input 4 (50%) Output 15 (50%) Input 4 (50%) Output 15 (50%) Time Meas Notes: 8. Checking output pulse for output with a voltage of 0 VDC applied, increase the DC voltage and then measure the voltage when the output pulse is not output. 9. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then measure the voltage when the output pulse is output.

Rev.2.00 Sep 14, 2006 page 6 of 16 Test Circuit R16 A VD+ OUT HD+ OUT CLAMP+ OUT H.POL. V.POL. CLAMP TIMING HD− OUT VCC V S/S IN V11 100 p 43 k TP13 TP14 TP15 5 V 0.01 µ 47 µ TP17 TP18 TP19 TP1 TP2 3.3 µ 75 k 4.7 µ 4.7 µ 10 µ V10 0.0068 µ 4.3 k 220 p V TIME GATA SW V DET V IN COMP/H DET COMP/H IN GND GREEN IN CLAMP SW V.STATE H.STATE V S/S OUT : 5 V Units Resistance: Ω Capacitance: F

Rev.2.00 Sep 14, 2006 page 7 of 16 Pin Description Pin No. Name DC Voltage (V) Peripheral Circuit Function 1 H.STATE 0 V DC or

5 VDC 20 kΩ

Logic output pin for horizontal synchronous signal When pin 6 input signal is POSI, outputs "H"; when NON, outputs "L"; and when NEG, outputs "H". 2 V.STATE 0 V DC or

5 VDC

Same as pin 1 Logic output pin for vertical synchronous signal When pin 8 input signal is POSI, outputs "H"; when NON, outputs "L"; and when NEG, outputs "H".

3 CLAMP

2.2 V when

22 kΩ 20 kΩ20 kΩ 1.3 V 3.1 V 0.1 mA 28 kΩ This SW is available to change the generating position of clamp pulse for input signal. (See Table 2.) V TH L = 0 to 1 V VTH M = 1.6 to 2.8 V VTH H = 3.4 to 5 V

4 GREEN

2.8 V when open 1 kΩ1 kΩ 3.5 V GREEN (SYNC ON VIDEO) input pin Input with negative sync. Comparison of pin 4 input signal and reference voltage within the IC performs synchronous separation.

5 GND   Grounding

6 COMP/H

2.5 V when open 0.3 mA0.3 mA 20 kΩ 20 kΩ 10 kΩ 2.8 V 10 kΩ 2.5 V 10 kΩ 2.2 V 1.5 kΩ 1.5 kΩ Composite sync/H sync input pin. Bias is approx. 2.5 V and impedance is 10 kΩ. The internal double threshold comparator is used for shaping waveform and detecting polarity. Optimum input amplitude is 0.6 V P-P at pin 6. Up to approx. 50% of duty, waveform shaping and polarity detection can be done.

7 COMP/H

2.5 V when open (no signal) 20 kΩ20 kΩ 2.5 V 2.8 V 2.2 V 75 kΩ 12 kΩ12 kΩ External capacitance is required as a filter pin for detecting polarity and detecting non-input. As the value is larger, the ripple is smaller and less malfunction occurs. However, this lowers the response speed of detection. 8 V IN 2.5 V when open Same as pin 6 V sync input pin Same as pin 6 9 V DET 2.5 V when open (no signal) Same as pin 7 Same as pin 7

Rev.2.00 Sep 14, 2006 page 8 of 16 Pin Description (cont.) Pin No. Name DC Voltage (V) Peripheral Circuit Function 10 V.TIME GATE SW 3.2 V when open 0.1 mA 20 kΩ 2.5 V 30 kΩ V TIME GATE SW pin Can select whether to output the pulse of VD portion from pin 14, 15 output pulse. The threshold voltage is approx. 2.5 V. V TH L = 0 to 2 V VTH H = 3 to 5 V

11 V S/S IN 

0.2 mA 0.1 mA 0.2 mA 4 kΩ 1 kΩ 1 kΩ 7.5 kΩ 20 kΩ 5.5 kΩ 1.75 kΩ V S/S IN pin Inputs a signal of having externally integrated composite sync for V sync separation.

12 V S/S OUT 

1 kΩ V S/S pulse output pin No problem occurs when current of approx. 6 mA flows to internal part of the IC. To improve the rising speed, connect a resistance between power supplies.

13 VD +OUT  Same as pin 12 VD + pulse output pin

14 HD +OUT  Same as pin 12 HD + pulse output pin

15 HD −OUT  Same as pin 12 HD − pulse output pin

16 V CC 5 V  Power supply

17 CLAMP +

 Same as pin 12 CLAMP + pulse output pin Same as pin 12 18 H.POL. 0 V DC or Same as pin 1 Logic output pin for horizontal synchronous signal When pin 6 input signal is POSI, outputs "L"; when NON, outputs "L"; and when NEG, outputs "H". 19 V.POL. 0 V DC or Same as pin 1 Logic output pin for vertical synchronous signal When pin 8 input signal is POSI, outputs "L"; when NON, outputs "L"; and when NEG, outputs "H".

20 CLAMP

3.0 V 1.9 V 0.4 mA 0.2 mA

1.9 V3 V

4 kΩ4 kΩ CLAMP TIMING pin The clamp pulse width is determined depending on the external resistance and capacitance. As the resistance value and capacitance value are larger, the clamp pulse width is wider.

Rev.2.00 Sep 14, 2006 page 9 of 16 Table 1 Decorder Logic Output Output Pin Pin 6 Input COMP/H Pin 8 Input V 1 2 18 19 POSI. NON POSI. NEG. H H H L H H L L L L L H NEG. NON POSI. NEG. H H H L H H H H H L L H NON. NON POSI. NEG. L L L L H H L L L L L H Table 2 Clamp Pulse Position Input Signal Pin 17 Output Signal Pin 4 Pin 6 Pin 3 "H" Pin 3 "M" Pin 3 "L" Ο Ο Χ Χ Ο Ο 4 trailing edge 6 leading edge 6 leading edge 4 trailing edge 4 trailing edge Χ 4 trailing edge 6 trailing edge 6 trailing edge Table 3 Output Priority Order Output Signal Input Signal Pin 3 "H" "L" Pin 3 "M" Pin 4 Pin 6 Pin 8 Pins 12, 14, 15, 17 Pin 13 Pins 12, 14, 15, 17 Pin 13 Ο Ο Ο Ο Χ Χ Χ Χ Χ Ο Χ Ο Χ Ο Χ Ο Χ Χ Ο Ο Χ Χ Ο Ο Χ Χ Χ Χ Χ Χ Χ Χ Χ Table 4 Allowable Input Amplitude Voltage Pin 4 input amplitude VV 0 to 2.1 (VP-P) fH = 10 Hz to 200 kHz fV = 10 Hz to 200 HzVS 0.2 to 0.6 (VP-P) Pin 6 input amplitude fH = 10 Hz to 200 kHz VS 0.5 to 2.5 (VP-P) Pin 8 input amplitude fV = 10 Hz to 200 Hz VS 0.5 to 2.5 (VP-P)

Rev.2.00 Sep 14, 2006 page 12 of 16 3) Polarity detection and non-input detection (pins 7 and 8) External capacitance is required as a filter pin to detect polarity and non-input. As the value is larger, the ripple is smaller and less malfunction occurs. However, the response speed for detection is lower. A sufficient external capacitance is 0.05 µF with input of 15 kHz and 10 µF with input of 60 kHz. However, check the frequency of the input signal in use and the filter pin waveform with the duty ratio conditions, and then check that the value is 3.1 V or more (2.8 V in capability) with positive polarity input and 1.9 V or less (2.2 V in capability) with negative polarity input. 4) V S/S IN (pin 11) Input a signal of having externally integrated composite sync for V sync separation. Composite sync input into pin 6 is output to pin 12. Output at 12 is externally integrated and is input into pin 11 for V sync separation. With the waveform at pin 11, check that the H element has been fully dropped. The threshold levels of sync separation, given hysteresis, are 3.5 V and 1.8 V. VTH = 3.5 V Input waveform at pin 6 Output waveform at pin 13 Waveform at pin 11 VTH = 1.8 V 2. Clamp Pulse 1) Clamp pulse width CLAMP TIMING (Pin 20) The clamp pulse width is determined by the external resistance and the capacitance. As the resistance value and capacitance value are larger, the clamp pulse width is wider. The time constant is determined by the current flowing out of pin 20 and the capacitance value of the timing pin. The flow current at pin 20 is determined by the pin voltage and external resistance value. When the external resistance is 4.3 (that is 700 µA) and the external capacitance is 220 pF, the pulse width is 0.4 µs. 2) Clamp pulse position CLAMP SW (pin 3) When pin 3 is "M" or "L", fixing a higher-priority signal to the trailing edge results in occurrence of a clamp pulse. When pin 3 is "H", and only GREEN is input, clamp pulse occurs at the trailing edge. A clamp pulse also occurs at the leading edge when COMP/H only is input or when both COMP/H and GREEN are input. Clamp Timing Capacitance at Pin 20 (pF) Clamp Pulse Width (µs) 10 100 1000 10000 R = 10 kΩ R = 4.3 kΩ

Rev.2.00 Sep 14, 2006 page 13 of 16 3. Sampling Pulse from VD Portion V TIME GATE SW (Pin 10) Whether to output the pulse of VD portion from pins 14 and 15 can be selected. When pin 10 is "H" or OPEN, pulse of the VD portion is output. When pin 10 is "L", the pulse of the VD portion is not output. VD portion Output at pin 14 when pin 10 is "H" or OPEN Output at pin 15 when pin 10 is "H" or OPEN Output at pin 14 when pin 10 is "L" Output at pin 15 when pin 10 is "L" VD portion 4. Output Stage 1) Logic output (pins 1, 2, 18 and 19) The output format is as shown in the diagram below. When the internal load resistance of the IC is 20 kΩ, a current of approx. 3 mA flows to the inside of the IC, no problem will occur. 20 kΩ 2) Pulse output (pins 12, 13, 14, 15 and 17) The output format is as shown in the diagram below. When the internal load resistance of the IC is 1 kΩ, a current of approx. 6 mA flows to the inside of the IC, no problem will occur. To improve the rising speed, connect a resistance between power supplies. Note that the low level of the output pulse goes up. 1 k1 kΩ

Rev.2.00 Sep 14, 2006 page 14 of 16 External Resistance (kΩ) Output Low Level (V) 0.8 0.2 0.4 0.6 04 28 1 0 ∞6 Typical Characteristics SP FP Ambient Temperature Ta (°C) Power Dissipation Pd (mW) 1400 200 400 600 800 1000 1200 −25 0 25 50 75 85 100 125 150 1237.6 827.8 643.6 430.5 Thermal Derating (Maximum Rating)

Rev.2.00 Sep 14, 2006 page 15 of 16 Application Example (fH = 50 kHz, fV = 80 Hz) 10 µ V IN 4.7 µ 100 3 k 18 k COMP/H IN 4.7 µ 4.7 µ 100 3 k 18 k 0.01 µ 0.01 µ VCC 5 V 0.068 µ 4.3 k 220 p : 5 V Units Resistance: Ω Capacitance: F CLAMP TIMING CLAMP SW GREEN IN GND COMP/H DET V TIME GATE SW H L V DETH.STATE V.STATE V.POL. H.POL. CLAMP+ OUT HD+ OUT VD+ OUT V S/S OUT V S/S IN HD− OUT 47 µ 20 19 18 17 16 15 14 13 12 11 10987654321 CLAMP GEN EDGE SW V.TIME GATE V.SYNC SEP SYNC SEP H SHAPE H DET LOGIC LOGIC V SHAPE V DET 100 p43 k (POSI NON NEG) (POSI NON NEG) (POSI NON NEG) (POSI NON NEG) 1.0 µ56 kH M L 4.7 µ 0.01 µ Note: External circuit for input of pins 6 and 8 When amplitude of up to 5 VP-P is entered into this circuit, can be kept constant at approx. 0.6 VP-P. When the duty of input signal at pins 6 and 8 changes, the most broad support range is obtained with amplitude of 0.6 VP-P.

Rev.2.00 Sep 14, 2006 page 16 of 16 Package Dimensions 2.0281.528 4.5 15° e 1.778 c L 3.0 0.51 0.9 1.0 1.3 A E 6.15 6.3 6.45 D 18.8 19.0 19.2 Reference Symbol Dimension in Millimeters Min Nom Max 0.22 0.27 0.34 P-SDIP20-6.3x19-1.78 1.0g MASS[Typ.] 20P4BPRDP0020BA-A RENESAS CodeJEITA Package Code Previous Code bp 0.38 0.48 0.58 e1 7.627.32 7.92 A2 3.3 SEATING PLANE 20 11 101 c E AL A2A1 bpb3e D INCLUDE TRIM OFFSET. DIMENSION "*3" DOES NOT NOTE) DO NOT INCLUDE MOLD FLASH. DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1.421.12 bp HE y 0.1 e 1.27 c 0° 8° L 0.4 0.6 0.8 0 0.1 0.2 A 2.1 7.5 7.8 8.1 A2 1.8 E 5.2 5.3 5.4 D 12.5 12.6 12.7 Reference Symbol Dimension in Millimeters Min Nom Max 0.35 0.4 0.5 0.18 0.2 0.25 MASS[Typ.] 20P2N-APRSP0020DA-A RENESAS CodeJEITA Package Code Previous Code Detail F L A2 A1 y Index mark 1 10 F HE E e bp A c D

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Product Information

M52347SP specifications and overview.

Summary

Sync Signal Processor

Description

The M52347 automatically selects three types of synchronous signals containing separate sync (positive and negative polarities of 0.5 to 2.5 VP-P), composite sync (positive and negative polarities of 0.5 to 2.5 VP-P) and sync-on-video (sync negative polarity), and performs waveform shaping. The IC is optimum to synchronous signal processing for multi-scan type display monitor.

Source title M52347SP Datasheet(PDF) - Renesas Technology Corp

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