Power Management

M51997FP

Renesas Technology Corp

SWITCHING REGULATOR CONTOL

Manufacturer: Renesas Technology Corp

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 7tENESAS Renesas Technology Corp.

MITSUBISHI <Dig./Ana. INTERFACE> M51997P,FP SWITCHING REGULATOR CONTROL

DESCRIPTION

M51997 is theprimary switching regulator controller which PIN CONFIGURATION (TOP VIEW) is especially designed to get the regulated DC voltage from AC power supply. co.ector[] [ayy This IC can directly drive the MOS-FET with fast rise and ¥ cite fast fall output pulse and with a large-drive totempole ovr u output. EMITTER z GND Type MS1997 has the functions of not only high frequency a ove 1-oFF OSC and fast output drive but also current limit with fast GY 3 ie response and high sensibility so the true “fast switching FB v cr regulator” can be realized wer[e] = The M51997 is equivalent to the M51978 with negative cur- rent limit and externally resettable OVP (over voltage REG [2]sorr protection) circuit. Outline 14P4

FEATURES

© 500kHz applicable to MOS FET + Output current 1A >) + Output rise time 6Ons, fall time 40ns coutector[1]O Pé} vec + Modified totempole output method with small through Vourl2] cLM- current MITTER[3 | GND © Compact and light-weight power supply . 3 z Ll + Small start-up current srs 100W A typ. HEAT SINK PIN[4 | q HEAT SINK PIN * Big difference between “start-up voltage” and “stop ove[s] 8 ‘GEE voltage” makes the smoothing capacitor of the power 3 input section small rele] [it] cr Start-up threshold 16V, stop voltage 10V DET TON + Packages with high power dissipation are used to with- stand the heat generated by the gate-drive current of rec[a] [a}sorr MOS FET . 14-pin DIP, 16-pin SOP 1.5W (at 25°C) Outline 16P2N-A © Simplified peripheral circuit with protection circuit and Connect tne heat sink pin to GNO. built-in large-capacity totempole output + High-speed current limiting circuit using pulse-by- pulse method (CLM+pin) + Over-voltage protection circuit with an externally re- settable latch (OVP) + Protection circuit for output miss action at low supply voltage (UVLO) © High-preformance and highly functional power supply + Triangular wave oscillator for easy dead time setting + SOFT start function by expanding period APPLICATION Feed forward regulator, fly-back regulator RECOMMENDED OPERATING CONDITIONS Supply voltage ranges: 12~30V Operating frequency: +: Jess than 500kHz Oscillator frequency setting resistance + T-ON pin resistance Rox’ 10k~75k.Q + T-OFF pin resistance Rorr 2k~30k2 7tENESAS 5-55

MITSUBISHI <Dig./Ana. INTERFACE> MS1997P,FP SWITCHING REGULATOR CONTROL BLOCK DIAGRAM REG (7.4V F/B Vee ; VOLTAGE REGULATOR siev g i Xs IsStKes UNDER Pa VOLTAGE a , LtocKour, be = DET ISHxis pwat Pw | Icompara> © coLLector | en _ TOR LATCH [ [oscar CURRENT roe T-0n O OETECTION (TRIANGLE) es - EMITTER T-OFF Q) Sa fF) - SOFT cm GNO ABSOLUTE MAXIMUM RATINGS _symbot_[ Parameter Conditions Ratings Unit Vee Supply voltage 31 v ‘ SipiVeuredl Pouk Es lo uiput current “Ivrea __| VREG terminal output current __ 6 [ma Vsort | SOFT terminal voltage _ - VREG +0. 2 Vv Vou | CLW— terminal voltage =a +4 Vv Vorr | DET terminal votage Z - 6 Vv love ___, OVP terminal current | _ a mA tee F/Bterminalcurent _ =10 mA tron FON seoninat jopul current _____ a a _ hore __| T-OFF termmal input current ema Pa ___| Power dissipation Ta=OC _ 15 ew Ke Thermal derating i aE 12 mw/c Topr____, Operating temperature _ - ~ —30~+85 c Teta Storage temperature =40~125 c Note 1. "+" sign shows the direction of current flowing into the IC and "—" sign shows the current flowing out from the IC 2. The low impedance voltage suoply should not be applied to the OVP terminal sss 7ENESAS

MITSUBISHI <Dig./Ana. INTERFACE> MS51997P,FP SWITCHING REGULATOR CONTROL ELECTRICAL CHARACTERISTICS (vec= tev, ty=28C, unless otherwise note Limits Block , Symbol Parameter Test Conditions amc] tie mee | unit ~ | _ [Vee] : _ EO 3 Vecrsranys | Operation start up voltage _ 15.2) 162, 2] V % Veeisror | Operation stop votage __ _ 90) 99) 109, v_ 2 Acc | Veo'stanr. Voc stop! difference | NVoc=Veo'sraar Vee stor Ts.of 6.3 76, Vv $ i Vec=14.5V_ Tg=25C 6s| 100! 150 & i lea Stand-by current os uA 2 i Veomi4.bv —300 STas05U 30} 100) 200 gi, | operat vcanen | Veci=15V. t= 188K 23} oul z | lee | Operating enc curent ‘Cemicue [—~s[ at 9) ¢ Veo=25V 13] 20| 3.0) ma B | lccowr | Grout curentin OvF state a tat aot ote cn 2 ieee [ecm | 210) 320) [ Veenane | Current at 0% duty F/@ terminal input current 7 [21] -1.8] —1.01 ma Trsnasio [ewer a maximum duty F/8 terminal input current _ | =0.9] -o6 =o.4} ma F/B | lrg __| Current difference between max and 0% duly | Are=lrawno—lrowxo | 1 35 | 0.99] 0.70] mA 2 in RET cd OVE OTN TOUNONOR anes cngocee evapo os oossa wm 420| 600] 780| 2 *"Venovrn | OVP terminal H threshold vollage en _-. [sa 750/960] mv | Vmove | OVP terminal hysterisis volage 1 BV nove Vrroven—Vinovn 30) | mv T“Inwove | OVP terminal threshold curent _ TT a0| 150) 2507 va Iwove __| OVP terminal input current | Vovr=400mV j= go] 150] 250| uA OVP | Vecovec | OVP reset supply vota 7 0] 10. i eo SST sion OVP terminal is open p28 }_2.01 10.9 ccistoel Nee ee eed peat eon « (ehimpedence) 0.85] 1.20| v | nVecowre | stop andovPreset ee | 7 | i | sian tonsoveorahs Meg 30y a0 [m0 218 L TONPE | tor ove reset _ [Vec=18V_ _ aio! = 140] = 93! | Vancua-| CLM terminal threshold volage 220] 200 180 [mv CLM! Ica | CLM terminal current Tvgwe=aiv 170] = 120] 90] wa [Teocww- | Delay time trom CLM to Vour Fi —_ 150 | — ns _fose___ | Oscillating frequency __ Row=20k9 Ce=220pF 170 188 | 207 | KHZ Toury | Manmum ON duy Roer=I7aO, —SsTasBC a7| 50/53) % 5 |_Yoscn | Upper limit vatage ef oscillation wavetorm | “ae7[ 437) 477 B | Voscu _| Lower limit voltage of oscillation waveform | Row20k 1, Rorr = 1741 1.76| 1.96] 216° Vv Vion | TON terminal voltage | Row=20k 0 Sse] as) sev Vr.orr | TTOFF terminal voltage | Roer=17k 2 29 35) 4.2 v ' Oscitlating trequene Sion 4 bo ant ke foscsort | a reauen cy Vsorr=2Z8V | Ren@20k2, Roge=17422, Cr=220pF My] 131) 181. kHe during SOFT operation : tote a & pte Ace DARIN ts er LOL J | teornn | SOFT terminal mput current Von OS] OT A | Discharge curent of SOFT terminal T i 1 | Isorrois | SOFT terminal discharging current mencaar aay 1h 33) = 2 oma Moe lees than Veo ite eer ps af 1 _ REG | Vaca | Reguiator output votage 1 _ Toe) 7.8; 88 Vv Vou TVee=18V_lo=l0ma = 7 004) oa) ov _Vove ear ' Voc=18V 1o=100mA = | 07 1.4 v Voc wiper tow votage Vec=5V_lo=Ima — 1 0.88) 10 B | Vou Vec=5V_ o=100mA = 1.30] 20° Vv 2 Vows Vec=18V_lo=—10mA. 16.0] 16.7) - ; Vv 6} Yor | outout nigh voltage A Ori Vows |e tenege | ee BV tg 100ma 55) 165) - 1 Vv [Trice | Output voitage rise ime | = 60 ns | Trae | Output voltage falltime jo oe Lat Gy ns & | Voer | Detecting vottage _ 24] 28) 26) Vv Boer _| O€T terminal mput current [seam Vv = 1.0] 3.0! wa S| Gavoer_| Voltage gain of detection amp 30 40, — | a8 2ENESAS 5-57

MITSUBISHI <Dig./Ana. INTERFACE> M51997P,FP SWITCHING REGULATOR CONTROL TYPICAL CHARACTERISTICS CIRCUIT CURRENT VS. SUPPLY THERMAL DERATING VOLTAGE (NORMAL OPERATION) (MAXIMUM RATING) Fey A A ee 1800 Row “1862 | JoyenSOOKH? E . Spee E 100 ——— = ime = = x0 + 4 3 | oe ‘oncnt00ene B s00] ee ee ci eee § 3 roc. i nan}> tyes * LL WT "OE oe oes 80 T5est 100 128 50 oe ne a im a8 mo as a0 AMBIENT TEMPERATURE Ta (°C) SUPPLY VOLTAGE Vee (V) SOFT TERMINAL INPUT VOLTAGE SOFT TERMINAL INPUT VOLTAGE = _ VS. EXPANSION RATE OF PERIOD = VS. EXPANSION RATE OF PERIOD rr fosc™ 100KHZ 1 4 E se fosc=500KHz | st5ry DRon=T5KO Rose 27K 5 AST TTT Rows TSR Rore=27KD B40 DRow= 18D Rorr= 24k 0 B a0 Tern Rore=24k 2. z @Row=22kN Rope =22kO < TT |G RCN 22K Rore= 22K 5 35) @Ron = 24k Rore= 20k 53s Ron =24kQ Rove =20kK2

8 LAT | | arct=z2kn Rore=t2K0 SB TTT [| bron =22k0 Rove =l2Ke

2 30 | TT ORon = 36K Bore =6.2k0 is mit Ron =36KN Rore=6. 242) 2 29) 2 ast or) eee ae ae 2 20) Z2 rol GR Faves a a Oe Zz, WLI Tt a eNGeee eee

1.0 SSS Ceol a) —— Cl

MITSUBISHI <Dig./Ana. INTERFACE> MS51997P,FP SWITCHING REGULATOR CONTROL one TERMINAL VOLTAGE RGMBIENT TEMPERATURE, =z —500, se es = oe > rit 4 . 2 | & —300] a oa aaa So ae & eS 8N 3-20 1 1 + La 5 ZA | Bil A bee 3 neon f Fe 3 To a °o 02 —n4 06 08 —1.0 $0 240 220 0) Ta a0) poi. CLM— TERMINAL VOLTAGE Vous (¥) AMBIENT TEMPERATURE Ta (C) OUTPUT LOW VOLTAGE GS SOURCE CURRENT asp VS: SINK CURRENT = es AE AN CO a ey SO on oe TTT | we settee LITT Sec TT TT TTT Sao PT 8H nie ee 5 i. jit oe ee 5 28

3 SOP BATT TT TT

g§ CO EU TT TATT zie Pee Pye efit ery TT eu tii a ie a 5 ae 95] By 3 aT CLC J oL LLL Li TTT TT | tear eit ei bia se TO! fOrsis PHNOM CONE? SC rOetnssis 10 SOURCE CURRENT fon (A) SINK CURRENT lo (A) DETECTING VOLTAGE ~ DETECTION TERMINAL INPUT CURRENT VS. AMBIENT TEMPERATURE = VS. AMBIENT TEMPERATURE av F godt TT tt HA 8 3 LEN 7 Q z | Baas . & os = | a 2 ar] | _ = i 4 SE gt ae AMBIENT TEMPERATURE Ta () ° AMBIENT TEMPERATURE Ta (0) stENESAS ; —59

MITSUBISHI <Dig./Ana. INTERFACE) M51997P,FP SWITCHING REGULATOR CONTROL VOLTAGE GAIN OF DETECTION ON duty VS, F/B TERMINAL INPUT CURRENT a a5 AMP VS. FREQUENCY {fosc™ 100kHz) s so Trea 2c “Pao Z HAE Py ad \\ aa

3 CON 7 SeANSRESS

Bd co PC CAN=E Se u 29) ‘ 567 rT StU TN TT SSRN

3 He NU py A RS |_|

5 u Ui Tit] | SANT TI rr ooo ce 08 10 12 14 12 18 20 22 FREQUENCY f (Hz) F/B TERMINAL INPUT CURRENT (mA) ON duty VS. F/B TERMINAL INPUT CURRENT ON duty VS. F/B TERMINAL INPUT CURRENT ‘0, (fosc™200kHz)} (fosc=500kH2) Row = 182. = T Ror r= 20%2 Ron = 182 | | {+ Ror F= 202 oP Pe i ! = wate Tamas 7 ness => {Tir ¥ x aa z = an 3 | 3 Zz wea | Z 2 t 10 6 Ay J 0” 04 06.08 1012 1416 18 20 22 oe ga 08 08 TON? 1s 16 18 20 22 F/@ TERMINAL INPUT CURRENT (mA) F/B TERMINAL INPUT CURRENT (mA) s

3 UPPER & LOWER LIMIT VOLTAGE OF OSCILLATOR FREQUENCY

= OSC VS. AMBIENT TEMPERATURE VS. CF TERMINAL CAPACITANCE [Pe ee ee “ooo ‘ite : Ae OFF = 20% = < c gs es g of Ot Neto fa sas - RISERS hil w “* 3 SC teh Net | eet ab siscaias aziz x 40 gs { N

5 Toag =100%H2 3 10 AN

g w4-=4 fore =200002 i Ne e so} fose ™OOKHE ESL Rav=Se2. Ror =6.2ka RTT = 22 x Pj Es ee a r. ae & 20 = = 108 T g J) Pee ee ceeteeeeeaneee g 6 3 3htH PtH = DUT tTii ty a w =40-20 0 20 40 60 a0 100 PDS sq PSA TORPES Qi Eds 40F $ AMBIENT TEMPERATURE Ta (‘C) CF TERMINAL CAPACITANCE (pF) stENESAS 5—60

MITSUBISHI <Dig./Ana. INTERFACE> M51997P,FP SWITCHING REGULATOR CONTROL OSCILLATOR FREQUENCY VS. AMBIENT TEMPERATURE ON duty VS. Rorr (Ron=24k2, Roee=20k 2, Ce=330pF) co (WS To Die TTT

7 SST 3 naa

© isa BINNS 3 100 = J NS 5 co 5 SLL Tr] oe LJ Ce ae Ee TG IO OBO ASS BO TOO 120 140 Rore (kf) AMBIENT TEMPERATURE Ta (°C) OSCILLATOR FREQUENCY VS. AMBIENT TEMPERATURE ON duty VS. AMBIENT TEMPERATURE (Ron ™24k.2, Rore™ 20k, Ce=47pF) (fos 100kHz) “y c00) 80 Seen = 96K Rowe = 6242 = go Se inert 3 200 20 Pt Po Co AMBIENT TEMPERATURE Ta (C) AMBIENT TEMPERATURE Ta ('C) ON duty VS. AMBIENT TEMPERATURE ON duty VS. AMBIENT TEMPERATURE (fose=200kHz) (fosc=500kHz) TTT COMTI rTTtt. ion: lore=6. oo Ron =36k2 Rore=6. 2k g CEE g “OE — Ree ZZKM, Roer= 1201 = Roy 22k0 Rorr=12k2. 2 : 2 a z = ms F OTP PEE Sane CECE EE * CEE CCE . * L OCT js tae tee et eel to. AMBIENT TEMPERATURE Ta ('C) AMBIENT TEMPERATURE Ta (C) z2ENESAS _

MITSUBISHI <Dig./Ana. INTERFACE> MS51997P,FP SWITCHING REGULATOR CONTROL OVP TERMINAL INPUT VOLTAGE OVP TERMINAL THRESHOLD VOLTAGE VS. INPUT CURRENT VS. AMBIENT TEMPERATURE =z im a=: t [ae Lippert ‘ feabteatareses zt 3 ores ETH $ pecan tara ¢ @ fo Foc tacese re 5 Aitaseases ann pcr 7 | 8 os EAH Ht 7 percese | ro Sa ett N Pe E 1000 Jguesenae thr circees 3 oe] SSE iresncie vatage 3 g CRS 2 oe Boob PARE S JS z z T + pelageckhies, 3 eee TEs Es Z +14 & pe eeceeect ie SeSSeee ast eee ra ee th PAR - 5 Ht s WT SEE wll 6F0.3 0.2 04 06 O8 1.0 -40 -20 0 2 4 60 80 100 OVP TERMINAL INPUT VOLTAGE Vove (V AMBIENT TEMPERATURE Ta ('C) CIRCUIT CURRENT VS. SUPPLY CURRENT FROM OVP TERMINAL FOR VOLTAGE (OVP OPERATION) OVP RESET VS. SUPPLY VOLTAGE 6 orem TTT Suanaane = 60 (| z Hi | a : 1 HH 3 oof {J --—- rye 8 @.ervi—30c) | | S —-— Ty=-NT 2 0p t+ = rT a is ry 8 VST) | Pi CT & 500, ~ 4 i B .o[S aver) roe Pn ft = Saeeenenee yee so eeeens a EEE ea 3 ix H SEEBEEEBDZTa7a ae bat S 2 05-++ + we | oR ee eiarsesater 7: g ae t ec aan 200} | a GEE z t ee zg Cr C B44 ps caen $e FA faae> _-seeeeeene Eq opt + ° .enaneeee 8 ttt tH oO ° 10.0 2,0 3A #8 o 5) 610 1S 20 MS 30 88 AO SUPPLY VOLTAGE Vee (V) SUPPLY VOLTAGE Vec (V. OUTPUT THROUGH CURRENT WAVEFORM AT FALLING EDGE OF OUTPUT PULSE AT RISING EDGE OF OUTPUT PULSE VY PPT aia an 2 | it ,{/ | LTT TP | Lit itt | Horizontal axis | 20ns/div Horizontal axis » 20ns/div Vertical axis | S0mA/div Vertical axis: SMA/diw stENESAS 5—62

MITSUBISHI <Dig./Ana. INTERFACE> MS51997P,FP SWITCHING REGULATOR CONTROL a FUNCTION DESCRIPTION parts can be reduced and also parts can be replaced by Types M51997P and M51997FP are especially designed for reasonable one. off-line primary PWM contorl IC of switching mode power __N the following circuit diagram. MOS-FET is used for out- supply to get DC voltage from AC power supply. put transistor, however, bipolar transistor can be replaced Using this \\C, smart SMPS can be realized with reasonable —_—with no problem. cost and compact size as the number of external electric ~ ral { 3 || = _ t - "ale ee | Z . Sip * oc oureur EI {

4 Bre Yeo COMECTOR] on iS

acwpur| = or] aa ewe | | ee | F4 4] ewirTeR | SH an we ono ET ie | MS51997P/FP oc 1,_| 1 2 ove #78 t- ON GF T- OFF | __CF® | 3 reeopace pM wei} ‘o>? Tuas) | Fig.1 Application example for feedforward regulator Es oe" _ ge t oc ourrur | Res 4 || | ea Cen Vee couteoroR] el « | fe Awd Kd 68 Vour p—ww—] bur | 8 o-| ot ont ont aw bp acimput | & ont Fee | M51997P/FP | ewrten | | ono fa Ld fad | Ton _ce_t-orr | fom ret | } bad Sheu fs Fig.2 Application example for fly-back regulator -)SSSSSSSSSSSSSSSSSSSsSSs 2tENESAS sa

MITSUBISHI <Dig./Ana. INTERFACE> MS51997P,FP SWITCHING REGULATOR CONTROL Start-up circuit section where Voscn=44V The start-up current is such low current level as typical Voscr *2.0V 100A, as shown in Fig. 3, when the Voc voltage is in- creased from low level to start-up voltage Vec start) Cy is discharged by the summed-up of Rore current and In this voltage range, only a few parts in this IC, which has ‘one sixteenth (1/16) of Row current by the function of Q2 the function to make the output voltage low level, is alive Qs and Qs when SW,, SW, are switched to “discharge and Icc current is used to keep output low level, The large side” voltage difference between Voc isrant) and Vee istor makes start-up easy, because it takes rather long duration | 5.8v from Veo: start) t0 Vecisror) H Q, T-ON V6 CHARGING 5 3e Swi FROM s ie m7 AT-OFF SOFT SIGNAL ‘ é z Ve=4.2V ‘switcHeD By a ae an 'CHARGING AND SS =llma isan Ne ISI 5 ot [* swe Fs > Ss, = a, 3 | DISCHARGING a Hy 3 =100uA t H MS51997_ . __ © Vecistor) Vecisrant 5 =a. =16 2 Fig. 4 Schematic’diagram of charging and discharging control circuit for OSC. capacitor Cr SUPPLY VOLTAGE Vee (V) Fig. 3 Circuit current vs. supply voltage be Vosen

82 Ri P----7

Bz i ; . ; = ! ' Oscillator section EE Vosc| 5 : : The oscillation waveform is the triangle one. The ON- Zz SEM a ' H : duration of output pulse depends on the rising duration of 2°, the triangle waveform and dead-time is decided by the fall- 33 ing duration SE The rising duration is determined by the product of external OZ Von + - resistor Ron and capacitor Cr and the falling duration is Er mainly determined by the product of resistor Rose and be2 Vo. capacitor C, 2&2 e e 3r6 (1)Oscillator operation when SOFT circuit does not Fig. 5: (OSC;"wavefarm/at'normsl condition (no-operation of intermittent action operate and OSC. control circuit) Fig 4 shows the equivalent charging and discharging cir- fall 1 OF termi cuit diagram of oscillator So fall rate of CF terminal is given as. The current flows through Rox from the constant voltage Vr-oFF Vy.0N wi) A source of 5.8V. Cy is charged up by the same amplitude as ~ RorrXCr + 16XRonxc, ‘Y/S) i Ron Current, when internal switch SW,, SW, is switched to 7 “charging side”. The rise rate of CF terminal is given as Theiminium eff uration approximately: le. glven as (Voscn—Voset)XCi ~VtoN (yg) yy eps Mos RCE g) ct : 4 “Rowxc, ‘V/* . Vr-orr 4 _Vron Rore 16% Ron where Vr.on=4.5V where Vr.ore=3.5V The maximum on duration is approximately given as The cycle time of oscillation is given by the summation of ~ (Voscn Voset) X RonX Cr (s) . 2 Equations 2 and 4 Vr.on net The frequency including the dead-time is not influenced by the temperature because of the built-in temperature con- pensating circuit 2ENESAS 5—64

MITSUBISHI <Dig./Ana. INTERFACE> MS1997P,FP SWITCHING REGULATOR CONTROL (2)Oscillator operation when the SOFT (soft start) circuit z is operating z Output transistor is protected from rush current by CLM zz Starts trom 0V function at the start time of power on SOFT terminal is BF Vosenp = ---= 545 - used to improve the rising response of the output voltage of Za, do t { power supply (prevention of overshooting) FO Vose——-— Pio —— = : The ON duration of output is kept constant, and the OFF Lae ot Hi ' 7 T duration is extended as the SOFT terminal voltage becom- ozs wedeeeece chee ep eg” The tirst

2522 VYopo-t output puise

es lower by the soft start circuit of this IC ease [ No output oulse The maximum value of extension is set internally at approx- ore Veco + imately sixteen times of the maximum ON duration $828 oF ‘ The features of this method are as follows 1 It is ideal tor primary contro! as IC driving current is F!98 Relationship between oscillator waveform and supplied from the third widing of the main transformer Output waveform at start-up at the start-up because constant ON duration is obtained from start-up Fig. 7 shows the relationship between oscillator waveform

2 It is possible to get a wide dynamic range for ON/OFF aNd output pulse

ratio by pulse-by-pulse current limit circuit It the SOFT terminal voltage is Vsorr, the rise rate of CF

2 The response characteristics at power-on is not — ‘efminal is given as

affected by input voltage as the pulse-by-pulse limit =p (ws) 5 current value is not affected by the input voltage one Fig. 6 shows the circuit diagram of the soft start. if SOFT ‘Te fall rate of oscillation waveform is given as terminal voltage is low. T— OFF terminal voitage becomes = Ngo ep on ws) 6 tow and V1-orr in equations \\3) and '4) become low OE ve: ac Aled where Vsors; SOFT termina! applied voltage TO REG TERMINAL Vee™0.85V | | ro Res | WVsrr-Vee<0, VsorrVoe=0 + {TERMINAL F— Mf Vsorr—Vae > Vr~orr (=3.5V), Vsor1—Vae=Vr— ore Rsorr - i ms | PWM comparator, PWM latch and current imi : + limit latch section | | | trope Fig. 9 shows the schematic diagram of PWM comparator bn 25, = and PWM latch section. The on-duration of output waveform Corr i poset if [5 ji. jo ; GH coincides with the rising duration of CF terminal waveform DISCHARGING TRANSISTOR * when the no output current flows from F/B terminal snieWigeciiam When the F/B terminal has finite impedance and current flows out from F/B terminal, "A" point potential shown in Fig.6 Circuit diagram of SOFT terminal section and Fig. 9 depends on this current. So the “A” point potential is T-OFF terminal section close to GND level when the flow-out current becomes large “A” point potential is compared to the CF terminal oscillator 53 waveform and PWM comparator, and the latch circuit is set 22 0 OZ 4 when the potential of oscillator waveform is higher than “A” oe Voss. cw point potential. The latch circuit is reset during the dead ZS =2.0v/ 7 : , ¢ time of oscillator circuit (falling duration of oscillator = i i i i circuit), So the “B” point potential or output waveform of . tof toa ‘ latch circuit is the one shown in Fig. 10. The final output 833 ' ' ' H wavetorm or “C" point potential is got by combining the “B” 252g Oy point signal and dead-time signal logically Coxe (please refer to Fig. 10) 2 5S + —= 3828 ‘ Fig.7 Oscillator waveform when the SOFT circuit is operating 7tENESAS . ~65

MITSUBISHI <Dig./Ana. INTERFACE> MS1997P,FP SWITCHING REGULATOR CONTROL tiv sev | { 4 ! OSC WAVEFORM 4h 1< BS OF CF TERMINAL ; ont & s 8 8 gg az g'tom Ole 2 FO testes > ST pe WAVEFORM OF ia. nue CLM— TERMINAL roel PUN] -N_----N-- FeO OP dey Nd , 1 Vrracane= 200m | WR. 2

4 Pont 0] i i CURRENT LIMIT | |

ANN "From ose Sertaren #1.Resistor to determine current limit sensivity WAVEFORM OF + 2;High-level during dead time Voor TERMINAL Fig.9 PWM comparator, PWM latch and current limit latch section Fig.11 Operating waveform of current limitting circuit Oscillator wavetorm { Wavetorm at point A To eliminate the abnormal operation by the noise voltage, A A the low pass filter, which consists of Rye and Cyr is used as waveronmor f ZN SNS shown in Fig. 12 OSC & POINT A 1 uy st Wy, Ny we It is recommended to use 10~ 1002 for Rue because such trot yt 1 Be dl range of Rye is not influenced by the flow-out current of POINTR | ' iz i 1 some 200A from CLM— terminal and Cyr is designed to = — aH have the enough value to absorb the noise voltage POINT C — Lr Fig.10 Waveforms of PWM comparator input point A, ; ale latch circuit points B and C fe van Pe J Current limitting section ono When the current-limit signal is applied before the crossing fe instant of “A” point potential and CF terminal voltage shown 7 in Fig. 9, this signal makes the output “off” and the off state cum get will continue until next cycle. Fig. 11 shows the timing rela- —-- tion among them. If the current limitting circuit is set, no waveform is gener- _Fig.12 Connection diagram of current limit circuit ated at output terminal, however this state is reset during the succeeding dead-time a So this current limitting circuit is able to have the function in Voltage detector circuit (DET) section . The DET terminal can be used to control the output voltage every cycle, and is named “pulse-by-pulse current limit which is determined by the winding ratio of fly back trans- There happen some noise voltage on Rem during the former in fly-back system or in case of common ground cir- switching of power transistor due to the snubber circuit and cuit of primary and secordary in teed forward system stray capacitor of the transformer windings The circuit diagram is quite similar to that of shunt regulator type 431 as shown in Fig. 13. As weil known from Fig. 13 and Fig. 14, the output of OP AMP has the current-sink ability, when the DET terminal voltage is higher than 2.5V _ 2tENESAS

MITSUBISHI <Dig./Ana. INTERFACE> MS51997P,FP SWITCHING REGULATOR CONTROL AV It is necessary to input the sufficient larger current (800): A pe 5000 | ~8mA) than I; for triggering the OVP operation The reason to decrease ly is that it is necessary that Ic at 1s he ie the OVP reset supply voltage is small [4 0 It is necessary that OVP state holds by circuit current from R, in the application example, so this IC has the character- eT istic of small Icc at the OVP reset supply voltage (~ stand- 5.4K by current + 20,/A) } On the other hand, the circuit current is large in the higher supply voltage, so the supply voltage of this 1C doesn't be- 10.8 come so high by the voltage drop across Ry This characteristic is shown in Fig, 16 i. The OVP terminal input current in the voltage lower than the OVP threshold voltage is based on |, and the input cur- 1.2k | rent in the voltage higher than the OVP threshold voltage is the sum of the current flowing to the base of Qy and the current flowing from the collector of Q; to the base. For holding in the latch state, \\t is necessary that the OVP Fig.13 Voltage detector circult section (DET) terminal voltage is kept in the voltage higher than Vee of So if the capacitor is connected between the OVP terminal but it becomes high impedance state when lower than and GND, even though Q; turns on in a moment by the 2.5V. DET terminal and F/B terminal have inverting phase surge voltage, eto, this latch action does not hold if the characteristics each other, so it is recommended to connect OVP terminal voltage does not become higher than Vee of the resistor and capacitor in series between them for phase. by charging this capacitor compensation. It is very important one can not connect by Er resetting OVP state. it is necessary to make the OVP resistor directly as there is the voltage difference between terminal voltage lower than the OVP L threshold voltage or them and the capacitor has the OC stopper function. make Vcc lower than the OVP reset supply voltage As the OVP reset voltage Is settled on the rather high vol- 7 tage of 9.0V, SMPS can be reset in rather short time from 5000 the switch-off of the AC power source if the smoothing capacitor is not so large value 1s 6S pe fa e) DET S| fe) ba 25v ve Gi rowwa & e t—, a, Fig.14 Schematic diagram of voltage detector circuit a8 A) | section (DET) r C OVP circuit (over voltage protection circuit) ay section | OVP circuit is basically positive feedback circuit con- g structed by Q2, Qs as shown in Fig. 15. bvro= : Moy Q2, Q, turn on and the circuit operation of IC stops, when pe oa the input signal is applied to OVP terminal (threshold vol- She 1 tage=750mv) GNOo—— I —— | The current value of Iz is about 150A when the OVP does lum0isition OvP-oparens not operates but it decreases to about 2A when OVP ig .15 Detail diagram of OVP circuit operates. stENESAS _

MITSUBISHI <Dig./Ana. INTERFACE> M51997P,FP SWITCHING REGULATOR CONTROL 8.0[ Te T RECTIFIED DC sade e tinasc to VOLTAGE FROM —>—~-——p—» MAIN TRANSFORMER 7.0) ty=-e | i] SMOOTHING CAPACITOR [ t OVP RESET POINT _| RA, E 60} een-we) | on 8 8. 94V(25C) ve sof 22085) oo re ae z ee | | 2 sop eh i 2 O Vee | THIRD WINDING OR 5 | “| | S BIAS WINDING & sof ++ | 3 3 ool M5197 Cee fF ie) eo" \\ 1.0 “a ty ° rca H GND | Fig. 17 Start-up circuit diagram when it is not necessary SUPPLY VOLTAGE Vcc |V to set the start and stop input voltage Fig.16 CIRCUIT CURRENT VS. SUPPLY VOLTAGE (OVP OPERATION) Just after the start-up, the lec current is supplied trom Cycc, however, under the steady state condition, IC will be Output section supplied from the third winding or bias winding of transfor- {t is required that the output circuit have the high sink and Me. the winding ratio of the third winding must be de- source abilities for MOS-FET drive. It is well known that the Signed so that the induced voltage may be higher than the totempole circuit has high sink and source ability. Howev- _ Pration-stop voltage Vacisror) Prernes sateneioniainy «renee The Voc voltage is recommended to be 12V to 17V as the For example, the through current may reach such the high "mal and optimum gate voltage is 10 to 15V end the out- current level of 1A, if type M51997 has the “conventional” _PUt voltage (Vox) of type M51997P, FP is about (Voc—2V) totempole circuit, For the high frequency application such _!* iS not necessary thal the induced voltage is settled high- as higher than 100kHz, this through current is very impor- _@ than the operation start-up voltage Vcc (starr), and the tant factor and will cause not only the large Icc current and _‘igh gate drive voltage causes high gate dissipation, on the the inevitable heat-up of IC but also the noise voltage other hand, too low gate drive voltage does not make the This IC uses the improved totempole circuit, so without de- MOS-FET fully on-state or the saturation state teriorating the characteristic of operating speed, its through current is approximately 100mA (2)The start-up circuit when it is necessary to set the start and stop input voltage APPLICATION NOTE OF TYPE M51997P,FP___'tis recommend to use the third winding of "forward wind- Design of start-up circuit and the power ("9° © "posttive polarity” as shown in Fig. 18, when the DC supply of IC source voltages at both the IC operation start and stop must (1)The start-up circuit when it is not necessary to set the _¢ Settled at the specified values start and stop input voltage The input voltage (Viysrarr)), at which the IC operation Fig. 17 shows one of the example circuit diagram of the Starts, is decided by R; and Ry utilizing the low start-up start-up circuit which is used when it is not necessary to set “urrent characterisitics of type M51997P, FP. the start and stop voltage necrineo oc YN It is recommended that the current more than 300A flows EOE eaescrt0n Ne pear mentee through R, in order to overcome the operation start-up cur- pe Tarcronust rent lecisranr) aNd Cyco is in the range of 10 to 47F. The ne ==} product of R; by Cycc causes the time delay of operation, so the response time will be long if the product is too much | fae _ large O Vee ne 3 Benge io SY OF FAN OA R, + M51997 i Cree Fig. 18 Start-up circult diagram when It is necessary to set the start and stop input voltage . RENESAS

MITSUBISHI <Dig./Ana. INTERFACE> MS1997P,FP SWITCHING REGULATOR CONTROL The input voltage (Vy stop), at which the IC operation (4)Power supply circuit for easy start-up stops. is decided by the ratio of third winding of trans- When IC start to operate, the voltage of the Cycc begins to former decrease till the Cyc becomes to be charged from the The Vin stant and Vin stop are given by following equa- third winding of main-transformer as the Ico of the IC in- tions creases abruptly. in case shown in Fig. 17 and 18, some “unstable start-up” or “fail to start-up” may happen, as the Vin sien=Ri= leech CRE Voce start 7 charging interval of Cycc is very short duration; that is the ° charging does occur only the duration while the induced Vin stop = (Vcc stop Vr) * q+ tv IN RE EP 8 winding voltage is higher than the Cycc voitage. if the in- duced winding voltage is nearly equal to the “operation- where stop voltage” of type M5197 lccu '$ the operation start-up current of IC It is recommended to use the 10 to 474F for Cycc:, and ab- Vee sraar iS the operation start-up voltage of IC out 5 times capacity bigger than Cyces for Cyece Vceistor! is the operation stop voltage of IC Ve is the forward voltage of rectifier diode Vin pp. is the peak to peak ripple voltage of ZR, ° oe, San b ead | << TRANSFORMER It is required that the Vix sraar) must be higher than Viv + + THIRD WINDING When the third winding is the “fly back winding” or “reverse ! | polarity”, the Viy:sraar) can be fixed, however, Vin. stop. can | | not be settled by this system, so the auxiliary circuit is re- QGND | L quired. — — Fig. 20 DC source circuit for stable start-up (3)Notice to the Vcc, Vec line and GND line To avoid the abnormal IC operation, it is recommended to. QP circuit design the Vcc is not vary abruptly and has few spike vol-—_(4)To avoid the miss-operation of OVP tage, which is induced from the stray capacity between the it is recommended to connect the capacitor between OVP winding of main transformer terminal and GND for avoiding the miss operation by the To reduce the spike voltage, the Cycc, which is connected spike noise between Vcc and ground, must have the good high fre- The OVP terminal is connected with the sink current source quency characteristics (=150A)in IC when OVP does not operate, for absorbing To design the conductor-pattern on PC board, following the leak current of the photo coupler in the application cautions must be considered as shown in Fig. 19. So the resistance between the OVP terminal and GND for ‘2 To separate the emitter line of type M51997 from the —_|eak-cut is not necessary the GND line of the IC If the resistance is connected, the supply current at the b. To locate the Cyc¢ as near as possible to type M51997 OVP reset supply voltage becomes large and connect directly As the result, the OVP reset supply voltage may become © To separate the collector line of type M51997 from the —_ higher than the operation stop voltage Voc line of the IC In that case, the OVP action is reset when the OVP is trig- d To connect the ground terminals of peripheral parts of gered at the supply voltage a little high than the operation (Cs to GND of type M51997 as short as possible stop voltage <<< => So it should be avoided absolutely to connect the resist- ance between the OVP terminal and GND [eure & vee NS pain + SRANsronmen Stxiko +—o-} 51997 Cree S WINDING. EMITTER 4 | cia o GNDO / Fig. 19 How to design the conductor-pattern of type M51997 on PC board (schematic example) 2ENESAS _

MITSUBISHI <Dig./Ana. INTERFACE> MS1997P,FP SWITCHING REGULATOR CONTROL TO REG ot Vez — ¥ - “3 a ok i TRANSFORMER Pen THIRD WINDING ove 2470 Cyc mM Lo M51997 4 oe LATE aa M51997 _ Lesie COUPLER GNO T love I Ss ee

7 GND Fig 23 OVP setting method using the induced third

| winding voltage on fly back system (4)Method to control for ON/OFF using the OVP terminal Fig. 21. Peripheral circuit of OVP terminal You can reset OVP to lower the OVP terminal voltage lower than Vrrovet. . So you can control tor ON/OFF using this nature (2)Application circuit to make the OVP-reset time fast The application is shown in Fig. 24 The reset time may becomes problem when the discharge The circuit turns off by SW OFF and turns on by SW ON in time constant of Cry * (Ry +Re) is long. Under such the cir- —thig application cuit condition, it is recommended to discharge the Cycc Of course you can make use of the transistor or photo- forcedly and to make the Vcc low value; This makes the transistor instead of SW. OVP-reset time fast REG (3)OVP setting method using the induced third winding voltage on fly back system M51997 For the over voltage protection (OVP), the induced fly back Salle type third winding voltage can be utilized, as the induced ove third winding voltage depends on the output voltage. Fig 23 shows one of the example circuit diagram © sw an TT to%™ TO Mal i am | | eR, TRANSFORMER Fig. 24 Method to control for ON/OFF using the | / | TJ] | OVP terminal as ain Current limitting circuit L jo ¢ % Nee (1)Peripheral circuit of CLM — terminal QO \\ | a ‘ 4 at M51997 Fig.25 shows the example circuit diagrams around the CLM ' : Lod | Fa, Tevec — terminal. It is required to connect the low pass filter. in aaa | [ono oder to reduce the spike current component, as the main =o $4 ——___J current or drain current contains the spike current especial- THE TIME CONSTANT ly during the turn-on duration of MOS-FET Ce snoee snouto 1,000pF to 22,000pF is recommended for Cup and the Rye, and Rwro have the functions both to adjust the “current Fig. 22. Example circuit diagram to make the detecting-sensitivity” and to consist the low pass filter OVP-reset-time fast p= Fe.

MITSUBISHI <Dig./Ana. INTERFACE> M51997P,FP SWITCHING REGULATOR CONTROL Se bos GNO M51997 o—+ i ae oe = 3 OcLM— Cur Res CURRENT eo” - mir Rue SIGNAL ta (b) Primary and secondary current Fig. 26 Primary and secondary current waveforms under the current limitting operation Fig. 25 Peripheral circuit diagram of CLM— terminal condition on feed forward system To design the Rue; and Ryrz, it is required to consider the -“ influence of CLM — terminal source current (Imcum —) » 2 which value is in the range of 90 to 270A. zi In order to be not influenced trom these resistor paralieled ra value of Ruy and Ryez (Rwei//Ryr2) is recommended to Fa be less than 1009 3 The Roum Should be the non-inductive resistor. (2)Over current limitting curve OUTPUT CURRENT {a)_ In case of feed forward system Fig. 27 Over current limiting curve on teed forward Fig. 26 shows the primary and secondary current wave- system forms under the current limiting operation. At the typical application of pulse by pulse primary current PIC SEAPP e ye pulse emery The demerit of the pulse by pulse current limitting system detecting circuit, the secondary current depends on the is that the output pul idth t red tot h r primary current. As the peak value of secondary current is a HOUL pulse widlnt cannot tecuce;teless wien some value because of the delay time of low pass filter limitted to specified value, the characteristics curve of out- connected to the CLM — terminal and propagation delay put voltage versus output current become to the one as shown in Fig. 27 time Tpocim — from CLM — terminal to output terminal of ‘9 type M51997. The typical Tepcim— is 150ns. As the frequency becomes higher, the delay time must be le shorter. And as the secondary output voltage becomes > —-0 higher, the dynamic range of on-duty must be wider; it = + means that it is required to make the on-duration much T more narrower. So this system has the demerit at the high- er oscillating frequency and higher output voltage applica- t tions. = To prevent that, the SOFT terminal is used to lower the fre- quency when the curve starts to become vertical ToiC GND y 3 Row ToCLM— <4 (a) Feed forward system er! stENESAS 5-71

MITSUBISHI <Dig./Ana. INTERFACE> M51997P,FP SWITCHING REGULATOR CONTROL =i REG ae + BIAS WINDING OF OVvec O BE Coc THE MAIN TRANSFORMER 3k 500 _ , O 1s 6s M51997 TO OUTPUT Pie Ry TRANSISTOR SOFT o H c 51997 _| Ore fo) > ; oR Fig. 28 Relationship between REG terminal and Re F/B terminal ' It the curve becomes vertical because of an excess cur- rent, the output voltage is lowered and no feedback current puoto-couPLen flows from feedback photo-coupler, the PWM comparator FGA PEED BACK SIGNAL operates to enlarge the duty sufficiently, but the signal from the CLM+ section operates to make the pulse width nar- Fig. 29 Circuit to tower frequency during over current rower Under the condition in which Ip in Fig. 26 does not become Your, sort YO poe 0, the output voltage is proportional to the product of the in- put voltage Vm (primary side voltage of the main + transformer) and on duty. If the bias winding is positive, + Vce is approximately proportional to Viv and the smoothed output voltage of the IC is proportional to Viv. The exist- ence of feed back current of the photo-coupler is known by TO MAKE -THE KNEE POINT, HIGH measuring the F/B terminal voltage which becomes less Vour than 2Vp¢ in the internal circuit of REG terminal and F/B SOFT terminal it the output current flows from the F/B terminal mame a Fig. 29 shows an application example. L Q, is turned on when normal output voltage is controlled at T a certain value. The SOFT terminal is clamped to a high- level voltage. If the output voltage decreases and the curve TO MAKE THE KNEE POINT LOW starts to drop, no feed back current flows, Q, is turned off and the SOFT terminal responds to the smoothed output —F'9: 90 pha toeontrol/the ‘knee (point of frequency voltage. It is recommended to use an Ry and Rz of 10k ~30kN. An Ry of 20~ 100k 9 and C of 1000pF ~ 8200pF should be used, To change the knee point of frequency drop. use the circuit in Fig. 30. To have a normal SOFT start function in the circuit in Fig 29, use the circuit in Fig. 31. It is recommended to use an R, of 10k _ stENESAS

MITSUBISHI <Dig./Ana. INTERFACE> MS1997P,FP SWITCHING REGULATOR CONTROL enn eel eenedeleichdeceiati w ". 7 BIAS WINDING OF 8 OVec O BE Cvcc | THE MAIN 5 basa COLLECTO oT > TRANSFORMER: g 5 > —— POINT THAT Vec VOLTAGE Vour & Pid OR THIRD WINDING o 2 wm VOLTAGE DECREASES M51997 TO OUTPUT rae UNDER “OPERATION-STOP Fs 2 TRANSISTOR 8] -- VOLTAGE sort f OTR 0C OUTPUT CURRENT | °7 | Fig. 32. Over current limiting curve on fly back system Ry Rsorr i @: i fe \\esorr’ | Q, | 7 1 D. ho COLLECTOR af ice Ry: “*-—— PHOTO-COUPLER FOR FEEDBACK SIGNAL M51997 aor | Oo Fig. 31 Circuit to use frequency drop during the over Ore Ores “ current and normal soft start | Rae | (b)IN case of fly back system The DC output voltage of SMPS depends on the Veg vol- Re tage of type M51997 when the polarity of the third winding To photo-coupler for feed back signal is negative and the system is fly back. So the operation of 9) an y' ss PI Fig. 33 Circuit to lower the frequency during the over type M51997 will stop when the Vcc becomes lower than current In the fly back eystors ‘Operation-stop voltage” of M51997 when the DC output voltage of SMPS decreases under specified value at over load condition Output circuit However, the MS1997 will non-operate and operate inter- 4) The output terminal characteristics at the Voc mittently, as the Voc voltage rises in accordance with the lta Vor Cie ik *Coparaiaeatg? woltags decrease of Icc current The fly back system has the constant output power charac- to main teristics as shown in Fig. 32 when the peak primary current TRANSFORMER and the operating frequency are constant | To avoid an increase of the output current, the frequency is 51997 iowered when the DC output voltage of SMPS starts to drop Vout using the SOFT terminal. Vec is divided and is input to the | SOFT terminal as shown in Fig, 33, because the voltage in g once Rou proportional to the output voltage is obtained trom the bias | winding. in this application example, the current flowing to | R; is added to the start-up current. So please use high re- sistance or 100k 2~200k2 for Ro. The start-up current is not affected by Ry if Ro is connected to Cyccs in the circuit shown in Fig. 20 Fig. 34 Circuit diagram to prevent the MOS-FET gate 9 9 potential rising eee ENESAS _

MITSUBISHI <Dig./Ana. INTERFACE> MS1997P,FP SWITCHING REGULATOR CONTROL The output terminal has the current sink ability even though » the Vcc voltage lower than the “Operation-stop” voltage or li : i Vecisror). (It means that the terminal is “Output low state” > ‘a a et and please refer characteristics of output low voltage ver- Fig} ++ vos 80v | bt sus sink current.) y Voel-200y Wi onan This characteristics has the merit not to damage the MOS- & 1 | Voee320V WW a Tho FET at the stop of operation when the Vcc voltage dew 8 10 f° wit, creases lower than the voltage of Vcc ‘stop’, as the gate 8 eae ware oT se charge of MOS-FET, which shows the capacitive load char- § i? len acteristics to the output terminal, is drawn out rapidly g yt lt vos—+ The output terminal has the draw-oul ability above the Voc |'/ source voltage of 2V, however, lower than the 2V, it loses the abil- o / ity and the output terminal potential may rise due to the of —— tL leakage current. In this case, it is recommended to connect the resistor of TOTAL STORED GATE CHARGE (nC) 100k between gate and source of MOS-FET as shown in Fig. 34 Fig. 35. The relation between applied gate-source voltage and stored gate charge (2)MOS-FET gate drive power dissipation Fig. 35 shows the relation between the applied gate vol- tage and the stored gate charge 1) To attach the heatsink to type M51997 In the region CD, the charge 1s mainly stored at Cos as the (2) To use the printed circuit board with the good ther- depletion is spread and Coo is small owing to the off-state maliconductivity, of MOS-FET and the high drain votage 3) To use the buffer circuit shown next section In the region 2), the Coo is multipiied by the “mirror effect as the characteristics of MOS-FET transfers trom oft-state _(9)Output butter circuit tae It is recommended to use the output buffer circuit as shown In the region «2, both the Cao and Cos affect to the charac- 1" FI. 96, when type M51997 drives the large capacitive teristics as the MOS-FET is on-state and the drain voltage 084 OF bipolar transistor, is tow The charging and discharging current caused by this gate ' charge makes the gate power dissipation. The relation be- | tween gate drive current Ip and total gate charge Qasu is Vout ‘a shown by following equation; [ mr PHD es lo=Qasi * fosc i aaa) ~ Where fose is switching frequency Fig. 36 Output buffer circuit diagram As the gate drive current may reach up to several tenths DET milliampere at 500kHz operation, depending on the size of Fig. 37 shows how to use the DET circuit for the voltage MOS-FET, the power dissipation caused by the gate cur- —_detector and error amplifier rent can not be neglected For the phase shift compensation, it is recommended to In this case, following action will be considered to avoid connected the CR network between DET terminal and F/B heat up of type M5197, terminal _ ENESAS

MITSUBISHI <Dig./Ana. INTERFACE> M51997P,FP SWITCHING REGULATOR CONTROL A pulse width narrow only for a few pulse at the start of op- é c PA —" eration 0.14F is recommended for the C. SQ ot VOLTAGE F/B Md Fe Tt M5197 msi997 | | toon 8 ' TorHoro 1. a couren oF Re 4 bees Fig. 39 How to get the narrow pulse width during the start of operation Fig. 37 How to use the DET circult for the voltage detector How to synchronize with external circuit Type M5197 has no function to synchronize with external Fig. 38 shows the gain-frequency characteristics between circuit, however, there is some application circuit for syn- point B and point C shown in Fig. 37. chronization as shown in Fig. 40 The G,,@, and «2 are given by following eugations; Rs Gaim 410) Ca Rs M51997 “oo 12) T-ON CF T-OFF o 4 At the start of the operation, there happen to be no output é pulse due to F/B terminal current through C; and Co, as the Ron 5 nT oer potential of F/B terminal rises sharply just after the start of ch — the operation. ‘SYNCHRONOUS Not to lack the output pulse, is recommended to connect PULSE the capacitor C, as shown by broken line. Please take notice that the current flows through the R; and Ry are superposed to Icc (stant). Not to superpose, R, is connected to Cycc2 as shown in Fig. 20 gz Lae} ze . . z x —~ Gavoer 3s ov e (DC VOLTAGE GAIN) bel Rs = 22 BG 22 BG Es ov be KK £5 WDM OF MAXIMUM PULSE WIDTH OF eh 2 ®%” SYNCHRONOUS SYNCHRONOUS PULSE tooo 2 PULSE Fig. 38 Gain-frequency characteristics between point Fig. 40 How to synchronize with external circult B and C shown in Fig. 37 How to get the narrow pulse width during the start of operation Fig. 39 shows how to get the narrow pulse width during the start of the operation. if the pulse train of forcedly narrowed pulse-width continues too long, the misstart of operation may happen. so it is recommended to make the output 7tENESAS _ —75

MITSUBISHI <Dig./Ana. INTERFACE> M51997P,FP SWITCHING REGULATOR CONTROL a poo \\ il) Vee t 9 COLLECTOR J : Vee he Vour " M51997 M +—71—-+. (-2v~-5v) ] E — — i es j | cc Ee 2 Fig. 41 Driver circuit diagram (1) for bipolar transistor Driver circuit for bipolar transistor dependency of forward voltage of pn junction, and IC pack- When the bipolar transistor is used instead of MOS-FET, age temperature is measured by “thermo-viewer", and also the base current of bipolar transistor must be sinked by the the IC is mounted on the “phenol-base" PC board in normal negative base voltage source for the switching-otf duration, atmosphere in order to make the switching speed of bipolar transistor So it is concluded that the maximum case temperature fast one (surface temperature of IC) rating is 120°C with adequate In this case, over current can not be detected by detecting margin resistor in series to bipolar transistor, so it is recommended to use the CT(current transformer) For the low current rating transistor, type M51997 can drive it directly as shown in Fig. 42 COLLECTOR Vee Your BIPOLAR M51997 k- TRANSISTOR Ni EMITTER Fig. 42 Driver circuit diagram (2) for smalt bipolar transistor Attention for heat generation The maximum ambient temperature of type M51997 is + 85°C, however, the ambient temperature in vicinity of the IC is not unitorm and varies place by place, as the amount of power dissipation is tearly large and the power dissipation is generated locally in the switching regulator. So it is one of the good idea to check the IC package temperature. The temperature difference between IC junc- tion and the surface of IC package is 15°C or less, when the IC junction temperature is measured by temperature So SEE 2tENESAS 5-76

Product Information

M51997FP specifications and overview.

Summary

SWITCHING REGULATOR CONTOL

Description

SWITCHING REGULATOR CONTOL

Source title M51997FP Datasheet(PDF) - Renesas Technology Corp

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