M51995

M51995 RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 7tENESAS Renesas Technology Corp.

MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL

DESCRIPTION

M51995A is the primary switching regulator controller which 18 Ein CONFIGURATION (TOP VIEW) especially designed to get the regulated DC voltage from AC power supply. This IC can directly drive the MOS-FET with fast rise and fast fall coLLector [7] [is] Veo output pulse. Vout [is] CLM+ Type M51995A has the functions of not only high frequency OSC ewrten ] = [a] com and fast output drive but also current limit with fast response and a high sensibility so the true “fast switching regulator” can be baa Fy oN? ON/OFF [5] cT realized. > It has another big feature of current protection to short and over ove [s| 0 T-OFF current,owing to the integrated timer-type protection circuit,if few DET [10] CF parts are added to the primary side. FB [s| [9] T-ON ‘The M51995A is equivalent to the M51977 with extemally re- Outline 16P4 settable OVP(over voltage protection)circuit.

FEATURES

© 500kHz operation to MOS FET cottector [1] [20] vec Output CUFTENE....sssscssssseecesesesesssesunsnssnssasansceeeeseeeseeedtOA, Vout [19] CLM+ Output rise time 60ns fall time 40ns EMITTER [1a] CLM- *Modified totempole output method with small through current VE = GND © Compact and light-weight power supply fl & fal “Big diference between “startup voltage" and “stop voltage GNOEE S a makes the smoothing capacitor of the power input section small. ove] 7 T-OFF Start-up threshold 16V,stop voltage 10V *Packages with high power dissipation are used to with-stand the vet [| CF heat generated by the gate-drive current of MOS FET. Fe T-ON 16-pin DIP,20-pin SOP 1.5W(at 25°C) Outline 20P2N-A © Simplified peripheral circuit with protection circuit and built-in large-capacity totempole output Connect the heat sink pin to GND. *High-speed current limiting circuit using pulse-by-pulse method(Two system of CLM+pin,CLM-pin) *Over-voltage protection circuit with an extemally re-settable latch(OVP) *Protection circuit for output miss action at low supply voltage(UVLO) @ High-performance and highly functional power supply «Triangular wave oscillator for easy dead time setting APPLICATION Feed forward regulator fly-back regulator RECOMMENDED OPERATING CONDITIONS Oscillator frequency setting resistance (1/27) 7tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL BLOCK DIAGRAM Vec FIB DET GND 500 UNDER ON/OFF (C)—} voLTaGe or AeE ' LOCKOUT REGULATOR ae 1S [Hs Ovp(shut down) ) coy 2.5V I () co.tector Pw PWM )s Vout | mae ' ©) emitter ~ INTERMITTENT | 7 ‘OSCILLATOR RESISTANCE T-ON| OSCILLATOR +CURRENT -CURRENT INTERMITTENT] mai aa (TRIANGLE) LIMIT LATCH ‘OSCILLATOR RESISTANCE T- OFF) ve) } i _H— CLM+ CLM- cT +CURRENT LIMIT = -CURRENT LIMIT INTERMITTENT OPERATION DETERMINE CAPACITANCE ABSOLUTE MAXIMUM RATINGS Symbol Supply voltage rs Collector voltage a | fo | Output current A Vi terminal voltage a | ON/OFF terminal voltage ce | CLW-terminal voltage at 0 CLMsterminal votage 0810 8.0 OVP terminal current | DET terminal voltage a | DET terminal input current a | F/B terminal voltage a | T-ON terminal input current | -OFF terminal input current | [Ps | Power dissipation Tac25'C es [ Ke | Thermal derating factor Tas25°C Operating temperature a | Tae | Storagetemperature | SSC*dSCSSC tO [TT sunetiontemperatwre PCS CdYY Note 1."+" sign shows the direction of current flow into the IC and *-" sign shows the current flow from the IC. 2.This terminal has the constant voltage characteristic of 6 to 8V,when current is supplied from outside. The maximum allowable voltage is 6V when the constant voltage is applied to this terminal.And maximum allowable current into this terminal is 5mA. 3.The low impedance voltage supply should not be applied to the OVP terminal. (2/27) 2tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL ELECTRICAL CHARACTERISTICS (vcc=18V, Ta=25°C, unless otherwise noted) | Min. | Typ. [ Max. | Operating supply voltage range | costo | 85 || : Operation start up voltage Po 2 | 16.2 | 172 | Vv |

5 Operation stop voltage [90 98 | to9 |v |

3 Difference voltage between =

dine [Quarries [omnes [se | aa | re |v g La § | tea Stand-by current Veo=14.5V,Ta=25°C | 50 | 90 | 140 | wa 3 Voo=14.5V,-30sTas85°C [ 40 [90 | 190 | ua | § [eco | Operating stcutcurent | Veowsoy 0 fas fat | & | icocr | cout ourem in timer OFF state [Voos5v sfc [20 fa Fs Wee=aV [760 | 280 | Circuit current in OVP state [Vooszsv tT 20 | 8.0 | ma | [Vit oNoFe| ONOFF terminal highthreshold witage | | et | ee | ot TV | [Viiowort ONOFFterminallowthrestoldvotage [| | a | 29 Tv | © |AViHoworr] ONOFF terminal hysteresis votage [dT | oe | 80 TV | |_Iremino | Current at 0% duty F/B terminal input current [-24 | -1.54 | -1.0 | ma | Current at maximum du F/B terminal input current [-090 | -0.55 | -0.40 | mA _| [Ars | Curenciowressenesnnacardosaiy | Ala=irawno-rawixo «185 | -0.99 | -0.70 | mA | Terminal voltage F/B terminal input current=0.95mA_ [49 [59 | 71 [ vi | | Rr | Terminalresistance | 420 | 600 | a0 | | 3 Input current of detection amp Voet=2.5V [— [10 [30 | pa_|

8 Voltage gainofdetectionamp | E80 |g |B

OvP terminal Hthreshold voltage | 840 | 750 | 960 | mV | [avrnove | OVP terminal hysteresis voltage | aVimovVinownVmomm «Tg | mv | OvP terminal threshold current | T8150 | 250 | UA | OVP terminal input current [Voveea0on 80150280 wa] [Vocoves | OVP reset supply votes? | ov terminal 75_[ 8. v Vecovec_| OVP reset supply voltage OVP terminalis open. 5 | 90 Vco(stoP) | Difference supply voltage between | (high impedance) : ig 0.55 | 1.20 v -Vecovec | operation stop and OVP reset Current from OVP terminal for | Voc=30V mows | Ove reset Voo=t8V aa Timer frequency Cr=4.7F [027 | 040 | 060 | _He_| | immech | Timer charge current Ta=25°C [-7e | -127 | -94 | pa F Tac85°C OFF imelON time ratio Oe ¢ CLM- terminal threshold voltage ~5STas85°C | -220 [| -200 | -180 [| mv | a CLM: terminal current [Vom=01V to | 125 | -90 | uA | ° Delaytime fromCLM-toVour [| Tt 00 | os = CLM terminal threshold voltage _| -S<Tas®5°C [180 | 200 | 220 | mv _| = CLM terminal curent [Vewe=0V 2-205 [=A | a Delay time from CLM+toVour [00 Ts] (3/27) 7tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL ELECTRICAL CHARACTERISTICS (Vcc=18V,Ta=25'C, unless otherwise noted)(CONTINUE) est conditions [ Min. [ Typ. | Max. | ‘lati Ron=20kQ,ROFF=17kQ. Oscillating frequency Geeaoprcecrasaerc 170 | 188 | 207 | kHz s Maximum ON duty 47.0 | 50.0 | 530 | %

3 Upper limit voltage of oscillation waveform | fosc=188kHz

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL TYPICAL CHARACTERISTICS THERMAL DERATING CIRCUIT CURRENT VS.SUPPLY VOLTAGE 4800 (MAXIMUM RATING) (NORMAL OPERATION) 22m RON=18KS2 tem| rene 1080=500KH 1500 fosoagookt iz = _ N £ J 16m @ 1200 a 7 z 2 14m] = as 2 5 — < 900 Dom Ai ¥ G [3 fosc=100kH2 3 3 tom| a = oe = 5 rs = 100p 2 300 N\\ bj — taxa0°e —, Ta=25°C » 50y — Tan85°C A Bs 0 2 50 7585 100 125 150 0 10 20 30 40 SUPPLY VOLTAGE Vec(V) AMBIENT TEMPERATURE Ta(°C) CIRCUIT CURRENT VS.SUPPLY VOLTAGE CIRCUIT CURRENT VS.SUPPLY VOLTAGE a0 (OVP OPERATION) (OFF STATE) ~ | OVP RESET POINT 3.0 7. 8:87V(-30°C) “Ol 8.94V(25°C) _ 9.23V(85°C) z z 60 E & & 8B 50) 5 20 Ta=25°C zg Ta=-30°C & Ta=85°C a 40) bat © =

3 Ta=25°C a Ta=-30°C SL

85" E 3 3.0] Ta=85°C OS 5 5 Q 1.0 3 2.0] g 49) ol 0 = 0 10.0 20.0 30.0 40.0 0 10 20 30 40 SUPPLY VOLTAGE Vee(V) SUPPLY VOLTAGE Vec(V) CIRCUIT CURRENT VS.SUPPLY VOLTAGE S OVP TERMINAL THRESHOLD VOLTAGE (TIMER OFF STATE) ry, VS.AMBIENT TEMPERATURE 3.0 z we 1.0 oO z * z 0.9 g ey Ta=25°C ao os H threshold voltage , 9 ol 5 | alec 3 A riover) = Ta=-30°C: > G o7 5 © a ° -E 06 L threshold voltage 5 10 Z (VtHoveL) oO zZ 05 Es = o c wo o4 = a 0 6 03 0 10 20 30 40 40-200 20 40 60 80 100 SUPPLY VOLTAGE Vec(V. AMBIENT TEMPERATURE Ta(°C) (5/27) 7tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL THRESHOLD VOLTAGE OF ON/OFF THRESHOLD VOLTAGE OF ON/OFF 2 ‘TERMINAL VS.AMBIENT TEMPERATURE 4 TERMINAL VS.AMBIENT TEMPERATURE Z 34 z = z i 32 Zz 20 wi e FE L § a0 & ON-OFF ON+OFF OF 28 S = 20 Z SE ‘4 Be ra Z 26 w 8 g ar < Q OFF*ON iJ mw a A OFF*ON ba 22 a 5.0) 3 3 x G 20 Fa w wi c c = 18 = 0 . “40-20. 0 20 40 60 80 100 al “60-40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(°C) AMBIENT TEMPERATURE Ta(°C) INPUT CURRENT OF VF TERMINAL DISCHARGE CURRENT OF TIMER = VS.INPUT VOLTAGE os VS.AMBIENT TEMPERATURE < +0 < 18 = EY g rT an $ 17 z z = 16} G7 & ia z= 14 “ 6 = > i 6 4 5 14 B a f-4 3 13) & 4 Ta=-30°C > - co) 5 2 Ta=25°C 8 12| ° SV Ta=85°C 0 “ a 10 0 1 2 3 4 5 6 7 8 9 10 60 -40 -20 oO 20 40 60 80 100 VF TERMINAL VOLTAGE WvF(V) AMBIENT TEMPERATURE Ta(°C) ON AND OFF DURATION OF TIMER CHARGE CURRENT OF TIMER VS.AMBIENT TEMPERATURE ‘200 VS.AMBIENT TEMPERATURE ie (INTERMITTENT OPERATION) A = TIMER ONe*CIRCUIT OPERATION ON = -180 t TIMER OFF*CIRCUIT OPERATION OFF zg 3 z E ~ -160 e150 13° «8 [ig oc wo 140 Wy a = 2 TIMER ON = = e = 5-120 6 125) 12 4 z

5 Oo z

[4 =< E c c < nr) 2 TIMER OFF wa w z a F4 a & 0 ik & 6 ‘a 75! 1.0 “Go 40200 2040 60 80 100 60-40-20. 0 +20 40 60 80 100 AMBIENT TEMPERATURE Ta(°C) AMBIENT TEMPERATURE Ta(°C) (6/27) 2ENESAS

MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL VF THRESHOLD VOLTAGE FOR TIMER THRESHOLD VOLTAGE OF CLM+ TERMINAL VS. AMBIENT TEMPERATURE VS. AMBIENT TEMPERATURE g 3 F zi & 35 re 205 E30 Tere 8 200 : 25 3 195 60-40 -20 0 20 40 60 80 100 = 60-40 20.0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(°C) AMBIENT TEMPERATURE Ta(°C) THRESHOLD VOLTAGE OF CLM- TERMINAL CLM+ TERMINAL CURRENT VS. AMBIENT TEMPERATURE VS. CLM+ TERMINAL VOLTAGE z= - -400 = = > 205 g -300 Z 5 ee Tesaore a z \\ a 195 ti +100 3 3 \\ 3 3 ; \\ -60 -40 -20 0 20 40 60 80 100 0 0.1 0.2 0.3 04 05 06 07 08 09 1.0 AMBIENT TEMPERATURE Ta(°C) CLM+ TERMINAL VOLTAGE Vem+(V) CLM- TERMINAL CURRENT OUTPUT HIGH VOLTAGE vs. Sai, VS. CLM- TERMINAL VOLTAGE a OUTPUT SOURCE CURRENT s = 24 Peay | 4p TA 2 soo E LTT PTT E & oo LUT TT 5 sco 8 ot HITT E Tons0"e et IT TUT UE TTT eal fee 8 COCCI CPT Ti Z (fers 2 eT TT IH 3 3 oat UT TT TT TT : ed LL 0 02 04 06 08 10 “im 10m 100m 1 10 CLM. TERMINAL VOLTAGE VeLm-(V) OUTPUT SOURCE CURRENT lon(A (7/27) 2tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL OUTPUT LOW VOLTAGE DETECTION VOLTAGE VS, OUTPUT SINK CURRENT VS, AMBIENT TEMPERATURE 5.0 Tl MAM TIM - > 5 Zz 40 i g 2 = 30 = 250) 2 4 3 20 Voc=18V N y 3 Voo=5v / 5 in i, Q 245 a | a 5 10 LL zal a ; PAT ll 0 ILL 2.40 tm fom 100m 1 10 60-40-20 0 20 40 60 60 100 OUTPUT SINK CURRENT lo1(A) AMBIENT TEMPERATURE Ta(°C) INPUT CURRENT OF DETECTION AMP DETECTION AMP VOLTAGE GAIN _ VS, AMBIENT TEMPERATURE VS. FREQUENCY z 16 a 500 = 8 a 4 3 15 a a Z 400 ae 6 is o \\ = 2 300 . ° . \\ a Ey wo 42 fo} & 20.0 w 14 & \\ z 1.0 fed N Fs 100 N 5 i \\ 2 09 ul \\ a 5 08 ar) IN < -60 -40 -20 0 20 40 60 80 100 100 1k 10k 100k 1M 10M AMBIENT TEMPERATURE Ta(°C) FREQUENCY f(Hz) ON duty ON duty VS. F/B TERMINAL INPUT CURRENT 50; ee TERMINAL INPUT CURRENT (fosc=100kHz) (fosc=200kH2) Ron=18kQ Ron=18kQ

40 ROFF=20kQ 40 RoFF=20k2

Z 30) e 20 6 > Ta=-30°C 2 Ta=-30" z a 8 3 —-

2 Ta=25°C z Ta=25°C

Ta=86°C Ta=85°C ; \\ ; \\ 0 0 F/B TERMINAL INPUT CURRENT Iva (mA) F/B TERMINAL INPUT CURRENT le (mA) (8/27) 7tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL ON duty vs. UPPER & LOWER LIMIT VOLTAGE OF OSC F/B TERMINAL INPUT CURRENT VS. AMBIENT TEMPERATURE 50, es (fosc=500kHz) BE Ron=18kQ RONn=18kQ Og 5.2} Rorr=20ka fosc=500kHz % RorF=20kQ, og fosc=200kHz og 48 fosc=100kHz ~ BS & 2 4.4 > 30 Ta=-30°C $

2 Ta=25°C = 40 :

5 x9 Ta=85°C = of fosoa200KtH2 Fy ° fosc=500kHz 2 2.0 = Fa 1.8 0 5 0 05 10 #15 20 25 60-40 20.0 20 40 60 60 100 F/B TERMINAL INPUT CURRENT IF/e(mA) ENS. TERE ES OR BC) OSCILLATING FREQUENCY VS. CF 10000 TERMINAL CAPACITY 100 ON duty VS. RoFF z sees eee ee ee od eT TT] z a SSN Fem CLIC ERE ARRAS RAN 5 er ee nf SRA

5 Fone22k0 SNR EEE ect | NAAN

9 Re Petey yy

fe} | 10 ee +LTHNT TTT TT Pi 0 1 * 40 * 100 1000 10000 1 eB 10 s 8 7 100 CF TERMINAL CAPACITY (pF) RoFF(kQ) OSCILLATING FREQUENCY VS. OSCILLATING FREQUENCY VS. AMBIENT TEMPERATURE AMBIENT TEMPERATURE 120 700 z RON=24kQ f mm ROFF=20k2 = i 8 ii0 r2330pF 8 600 Cr=47pF > > 2 ee ae 2 500 2 5 To> HL 8 100 3 a oc g “ 400 | iad 3 300 3 5 g Q ° ° 80 200 60-40-20 0 20 40 60 80 100 60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(°C) AMBIENT TEMPERATURE Ta(°C) (9/27) ztENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL ON duty VS. AMBIENT TEMPERATURE 100 __ON duty VS. AMBIENT TEMPERATURE 100 (fosc=100kHz) (fosc=200kHz) 90 90 70 | 70 | z z = 6 ————ronwarrroreetax 5 60 a ronan ora g | FE} 3 50 ————_____ rone2x.rorrazok 3 50 a on-2k rr =20 z fone Rorrnzzk 2 a nek Rorrnzck ° 40 $$ ronrtcrrorrazck 2 40 = rirorrorran l 30 —a—ooooo I FON=15k,ROFFS27K 3) 00 15k, ROFFHO7K 20 20 10 10 0 0 -60 -40 -20 0 20 40 60 80 100 60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(°C) AMBIENT TEMPERATURE Ta(’C) INPUT VOLTAGE OF TERMINAL VS. ON duty VS. AMBIENT TEMPERATURE EXPANSION RATE OF PERIOD 100 5.0 (fosc=500kHz) (fosc=100kHz) 90 S Tv 80 $$ nronesernorres.ax £ 4.9 nS 1) RON=15k,ROFF=27k 70 3 2, RON=18k,ROFF=24k z = 3, RoN=22k,ROF=22k TS 60 20222 OFF = 12K ia 3.0 4 RON=24k, ROFF=20k. . ] # 5, ow 20 Rore=tok ont Ror 208 o - a ronzzekRorrnzck 1B] Rows $64, ROFF6 2k ° 40 $$ Fonstecrorraan Woo Ks a $$ rnc terran | 2 \\ 20 £10 ' ny 0 oL__lelsNeTs Vs -60 -40 -20 0 20 40 60 80 100 0 2 4 6 8 10 12 14 16 18 20 AMBIENT TEMPERATURE Ta(°C) EXPANSION RATE OF PERIOD(TIMES) INPUT VOLTAGE OF TERMINAL VS. OVP TERMINAL INPUT VOLTAGE VS. Pr EXPANSION RATE OF PERIOD 3 INPUT CURRENT x m = (fosc=500kHz) = Ta=85°C . = e Ta=25°C = 40 & Ta=-30°C--7 2 1) Ron=15kROFF=27« 5 - z aba idle a g— Nv S | RON=22k, RoF=20k & uy & 3.0 {4 RON=24k, ROFF=20k 3 rE 5) RON=22k, ROFF=12k 5 fo) (6 RON=36k ROFF=6.2k 2 & 20 & = 4 10) 5 \\ 3 ic] \\ S = 10 Fa J Be Fa ES = 5 ? Da 6 9 tp EXPANSION RATE OF PERIOD(TIMES) OVP TERMINAL INPUT VOLTAGE Vove(V) (10 / 27 ) 7tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL —_ CURRENT FROM OVP TERMINAL FOR OVP us RESET VS. SUPPLY VOLTAGE LS 300, a s = 700 c 2 600 a 2 500

5 Ta=-30°C

i Ta=25°C e 400 Ta=85°C 3 300 2 200 f E a 100 J c 2 0 S) o 5 10 15 20 2 30 35 40 SUPPLY VOLTAGE Veo(V) (11/27) 7tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL FUNCTION DESCRIPTION ‘Type M51995AP and M51995AFP are especially designed for parts can be reduced and also parts can be replaced by off-line primary PWM control IC of switching mode power supply reasonable one. (SMPS) to get DC voltage from AC power supply. In the following circuit diagram,MOS-FIT is used for output Using this IC,smart SMPS can be realized with reasonable transistor,however bipolar transistor can be used with no cost and compact size as the number of external electric problem. 7a ) is 3 || & Voure ~ 3 || € zs i : ' * ' ° 2 ay} et] 3/5 # {vou M51995AP %R2 5 || 5 C Cvec 3 || & [4] [5] +—| +0 i; CP [4 PT FE L] [> [3

4 Ron “RorF La

7 ¥ ON/OFF Pin No.is related with M51995AP- Fig.1 Example application circuit diagram of feed forward regulator ° % Zz x | { P Fs ° [| Vout ove FB | {1s} = Rai, S M51995AP 7 = ° Cvec = [4 [sh FEMME | R22 EF | 5 Ron‘ RoFF Pin No.is related with M51995AP_ Fig.2 Example application circuit diagram of fly-back regulator (12 / 27) 7ENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL Start-up circuit section Cr is discharged by the summed-up of RorF current and one sixteenth (1/16) of Ron current by the function of Q2,Q3 and Q4 The start-up current is such low current level as typical 901 when SW1,SW2 are switched to "discharge side". A,as shown in Fig.3,when the Vcc voltage is increased from low level to start-up voltage Vec(sTant). 5.8V In this voltage range,only a few parts in this |C,which has the | GT Isa J function to make the output voltage low level,is alive and ro fe Qo Due Icc current is used to keep output low level.The large voltage CT an difference between Vcc(start) and Vccistor) makes start-up Fon | ae easy,because it takes rather long duration from VecisTarT) to T-OFF * Veoistor). FROM SWITCHED BY ROFF | VF SIGNAL ‘CHARGING AND ved, DISCHARGING é a SIGNAL E lcco Stang prserrecnnes orf Lyte 5 tL Clie a c1” hy bischarcine s 51995, SO tect . Fe} : Fig.4 Schematic diagram of charging and discharging = Vec Vee control circuit for OSC.capacitor Cr ° (STOP) (START) =9.9V ~16.2V z SUPPLY VOLTAGE Vec(V) 2 Voscu G& =a , Fig.3 Circuit current vs.supply voltage a : % — vosc.| _» : ’ geo ; H Oscillator section i d : : z The oscillation waveform is the triangle one. The ON-duration 7 of output pulse depends on the rising duration of the triangle FS waveform and dead-time is decided by the falling duration. 848 The rising duration is determined by the product of external 539 resistor RON and capacitor Cr and the falling duration is mainly S28 vom determined by the product of resistor RFF and capacitor Cr. Sz (1)Oscillator operation when intermittent action 99 ==6 YC 1 h and OSC control circuit does not operate Fig.4 shows the equivalent charging and discharging circuit Fig.5 OSC.waveform at normal condition (no- diagram of oscillator when the current limiting circuit does not operation of intermittent action and OSC.control operate.It means that intermittent action and OSC control circuit circuit) does not operate. The current flows through Ron from the constant voltage source of 5.8V.Cr is charged up by the same amplitude as RON So fall rate of CF terminal is given as current,when internal switch SW1 is switched to “charging Vecoee Gcon ide". The rise rate of Cr t Lis gi = VT- = side ‘ rise rate of CF terminal is given as For Ce TER Cee ~ _VT-oN oh : seo = Ron X OF (VAS) snssssnssssssssssssoornserressssornnsseese( 1) The minimum off duration approximately is given as ~ (Vosch-Vosct) X Cr where Vr- on = 4.5V PONTO, VION (S)onrnnnnnnnnnmnnnn(l) The maximum on duration is approximately given as Rorr 16 X Ron ~ (Vosci-Vosct) X RON X CF (g) e where Vr - OFF ~ 3.5V where VoscH ~ 4.4V The cycle time of oscillation is given by the summation of Vosci ~ 2.0V Equations 2 and 4. The frequency including the dead-time is not influenced by the temperature because of the built-in temperature compensating circuit. (13/ 27) 7tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL (2)Oscillator operation when intermittent action and OSC control circuit operates. = When over current signal is applied to CLM+ or CLM- $, Age P terminal,and the current limiting circuit,intermittent action and og : OSC control circuit starts to operate.in this case T-OFF terminal $= i voltage depends on VF terminal voltage,so the oscillation 38 Vosct | _» ' Y frequency decreases and dead-time spreads. sh a : : g& d : : The rise rate of oscillation waveform is given as & gs ~ _VT-ON 83 = Ron X Cr De ce ce ee aE TEER | oe, SG5 vow if Zz The fall rate of oscillation waveform is given as <2 8 3338 OL ~ We -WFo Vr ON ROX Ce * TEX Row X Op WS) rnnnl6) Fig.6 OSC.waveform with operation of intermittent Where Vt-on~ 4,5V and OSC.control circuit operation WVF terminal voltage Wro = 0.4V Wr-VF0=0 if Wr-VvFo<0 z START FROM OV Wr-Wro=V1-oFF if Vr-Vvro>VT-oFF=. 3.5V Ro So when VvF>3.5V,the operation is just same as that in the 52 no current limiting operation state. a ee 7S The maximum on-duration is just same as that in the no- td a operation state of intermittent and oscillation control circuit 86 [) and is given as follows; ' 6 ; 2% ! FIRST = (Wosot- Vosct) XROFFXCF gy 7) 53 ' PULSE VT-ON 23> von}--! $55 ‘NO GENERATE The minimum off-duration is approximately given as; wre ‘PULSE Bez i ~~ (WoscH - Voscl) X CF 83s OT Wer-WFo 4 VT-ON (gy @ OPERATION START RoFF XCF ” 16 X RON X Cr SP Fig.7 Relation between OSC. and output waveform circuit operation at start up The oscillation period is given by the summation of Equation(7) and (8). As shown in Fig.7,the internal circuit kills the first output pulse in M51995 the output waveform. The output waveform will appear from the second pulse cycle because the duration of first cycle takes Cr Vout charging time longer comparing with that at the stable operating dete. Rvrre Usually the applied voltage to VF terminal must be proportional VE the output voltage of the regulator. overs So when the over current occurs and the output voltage of the a regulator becomes low,the off-duration becomes wide. There are two methods to get the control voltage, which depends on the output voltage,on primary side.For the fly back Fig.8 Feedback loop with low pass filter from output type regulator application,the induced voltage on the third or to VF terminal bias winding is dependent on output voltage.On the other hand,for the feed forward type regulator application,it can be copii i used that the output voltage depends on the product of induced Sok CON wl Ooninue.6t over load conation mean me voltage and “on-duty’,as the current of choke coil will continue ; : : — : - Fig.8 shows one of the examples for VF terminal application at vet loa condition.it means the “continuous current for the feed forward type regulator. Fig.8 shows one of the examples for VF terminal application for the feed forward type regulator. (14/ 27 ) 7tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL PWM comparator and PWM latch section Current limiting section Fig.9 shows the PWM comparator and latch section. The on- When the current-limit signal is applied before the crossing duration of output waveform coincides with the rising duration of instant of "A" pint potential and CF terminal voltage shown in CF terminal waveform,when the infinitive resistor is connected Fig.9,this signal makes the output "off" and the off state will between F/B terminal and GND. continue until next cycle.Fig.11 shows the timing relation among When the F/B terminal has finite impedance and current flows them. out from F/B terminal,"A" point potential shown in Fig.9 depends The current limiting circuit has two input terminals,one has the on this current.So the "A" point potential is close to GND level detector-sensitivity of +200mV to the GND terminal and the when the flow-out current becomes large. other has -200mV.The circuit will be latched if the input signal is “A" point potential is compared with the CF terminal oscillator over the limit of either terminal. waveform and PWM comparator,and the latch circuit is set If the current limiting circuit is set,no waveform is generated at when the potential of oscillator waveform is higher than "A" output terminal however this state is reset during the point potential. succeeding dead-time. On the other hand, this latch circuit is reset by high level signal So this current limiting circuit is able to have the function in during the dead-time of oscillation(falling duration of oscillation every cycle,and is named "pulse-by-pulse current limit". waveform).So the "B" point potential or output waveform of latch circuit is the one shown in Fig. 10. The final output waveform or "C* point potential is got by combining the "8" point signal and dead-time signal i OSC WAVEFORM logically (please refer to Fig.10) a | Vmicum= 200m¥ =71V WAVEFORM OF 5.8V CLM+ TERMINAL | § x POINT A PC OINTB. QO E 2 aren G— Sureur CURRENT LIMIT Pwm POINTC LATCH FB comp | WAVEFORM OF Vout TERMINAL FROM a osc . M51995A CF (a) +current limit “WS Fig.9 PWM comparator and latch circuit OSC WAVEFORM OF GF TERMINAL (OSC WAVEFORM WAVEFORM OF A FORT: fl i CLM TERMINAL WAVEFORM | Zs oN TO Was 20m oroses — £4 POINT A i ot ae CURRENT LIMIT H : poi st SIGNAL TO SET : po an LATCH POINT B : ; ' " WAVEFORM OF : Vout TERMINAL POINT C (b) -current limit Fig.10 Waveforms of PWM comparator input point A, latch circuit points B and C Fig.11 Operating waveforms of current limiting circuit (15/ 27 ) 2ENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL Itis rather recommended to use not "CLM+" but “CLM-" terminal,as the influence from the gate drive current of MOS-FIT ec ever ona AK =f can be eliminated and wide voltage rating of + 4V to -4V is guaranteed for absolute maximum rating. There happen some noise voltage on Roum during the switching CURRENT UM np of power transistor due to the snubber circuit and stray SNA capacitor of the transformer windings. To eliminate the abnormal operation by the noise voltage,the Berea ENT ep low pass filter, which consists of RnF and CnF is used as shown in Fig.12. itis recommended to use 10 to 1002 for RNF because such SE oe MLE aTTENT: 08 range of RNF is not influenced by the flow-out current of some CONTROL CIRCUIT. 200pA from Cm terminal and Cnr is designed to have the i enough value to absorb the noise voltage. (b) Without current limit signal Fig.13 Timing chart of intermittent and OSC.control circuit +4 + M51995A IE M51995A, | ec | Intermittent action circuit section Intermittent action circuit will start to operate when the output von—— von —— signal from the intermittent action and oscillation control circuit are "high" and also VF terminal voltage is lower than VTHTIME of i fee i about 3V. cums fo) GND fo) Fig.14 shows the block diagram of intermittent action 7 7 circuit Transistor Q is on state when VF terminal voltage is CNF = Rom Cnr 3 Roum higher than VTHTIME of about 3V,so the CT terminal voltage is enn} ane near to GND potential. = When VF terminal voltage is lower than VTHTIME,Q becomes | | “off* and the CT has the possibility to be charged up. ae __ Under this condition, if the intermittent action and oscillation control signal become "high" the switch SWA will close only in (a)In case of CLM+ (b)In case of CLM- this "high" duration and Cr is charged up by the current of 120pA through SWa (SWs is open) and CT terminal potential Fig.12 How to connect current limit circuit will rise. The output pulse can be generated only this duration. Intermittent action and oscillation control When the CT terminal voltage reaches to 8V,the control logic en circuit makes the SWa "off" and SWs “on’,in order to flow in the ITIMEOFF of 15yA to CT terminal. When the internal current limiting circuit states to operate The IC operation will be ceased in the falling duration. and also the VF level decreases to lower than the certain level On the other hand,when CT terminal voltage decreases to lower of some 3V,the dead-time spreads and intermittent action and than 2V,the IC operation will be reset to original state,as the OSC control circuit(which is one of the timer-type-protection control logic circuit makes the SWa *on* and SWe “off. circuit)starts to operate. Therefore the parts in power circuit including secondary rectifier The intermittent action and OSC control circuit is the one to diodes are protected from the overheat by the over current. generate the control signal for oscillator and intermittent action circuit. Fig.13 shows the timing-chart of this circuit.When the output of intermittent action and oscillation control is at "high" level,the waveform of oscillator depends on the VF terminal voltage and fear the intermittent action circuit begins to operate. 4 (=120pA) Vrutie (=3V) A CT ¥ swa| CONTROL oO t swe LOGIC ‘OSC WAVEFORM 5 OF CF TERMINAL ve i, 8 i SH inmeore CT) (=15HA) CURRENT LIMIT SIGNAL Fig.14 Block diagram of intermittent action circuit OUTPUT OF CURRENT LIMIT LATCH _I LJ — OUTPUT OF INTERMITTENT ACTION and OSC. CONTROL CIRCUIT (a) With current limit signal ( 16/ 27 ) 2ENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL of primary and secondary in feed forward system. INO OPERATING The circuit diagram is quite similar to that of shunt regulator DURATION type 431 as shown in Fig.17.As well known from Fig.17 and Fig.18,the output of OP AMP has the current-sink ability,;when 8V the DET terminal voltage is higher than 2.5V but it becomes high impedance state when lower than 2.5V DET terminal and F/B terminal have inverting phase characteristics each other,so it is recommended to connect the resistor and capacitor in (2 series between them for phase compensation. It is very important,one can not connect by resistor directly as there is the voltage difference between them and the capacitor has the DC ‘stopper function. Fig.15 Waveform of CT terminal 27Av 5000 Fig.16 shows the Icc versus Vcc in this timer-off duration. In this duration the power is not supplied to IC from the third winding of transformer but through from the resistor R1 maT ys Bee connected toVcc line. Ober If the R1 shown in Fig.1 and 2 is selected adequate value, Vcc terminal voltage will be kept at not so high or low but adequate value,as the Icc versus Vcc characteristics has such the one L 3 54k shown in Fig. 16. fo 108k (es Fig.17 Equivalent circuit diagram of voltage detector — 15 vo i - 27 Z Ea E 50002 = 1.0 3 18 6s = a B05 © ber 2sv 0 1 0 5 10 15 20 25 30 SUPPLY VOLTAGE V. cot) Fig.18 Equivalent circuit diagram of Fig.16 Icc vs.Vcc in timer-off duration voltage detector of intermittent action circuit To ground the CT terminal is recommended, when the intermittent mode is not used. ae . In this case the oscillated frequency will become low but the IC ON-OFF circuit section will neither stop the oscillation nor change to the intermittent - | action mode,when the current limit function becomes to operate Fig.19 shows the circuit diagram of ON-OFF circuit. The current and the VF terminal voltage becomes low. flown into the ON-OFF terminal makes the Q4 "on" and the switching operation stop.On the other hand.the switching ;, 1 4, operation will recover as no current flown into ON/OFF terminal Voltage detector circuit(DET) section makes Q4 ‘off" As the constant current source connected to Q4 , base terminal has such the hysteresis characteristics of 20UA at The DET terminal can be used to control the output voltage ‘operation and 3A at stopping.So the unstable operation is not which is determined by the winding ratio of fly back transformer appeared even tf the ON/OFF terminal voltage signal varies in fly-back system or in case of common ground circuit slowly. (17 / 27 ) 2ENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL Fig.20 shows how to connect the ON/OFF terminal.The OVP circuit(over voltage protection circuit)section ewiohing ‘operation will stop by swien-off and operate by switctr. OVP circuit is basically positive feedback circuit constructed by . 5 a ‘ Q2,Q3 as shown in Fig.22. Paes ede aie apr Q2,Q3 tum on and the circuit operation of IC stops, when the terminal is directly connected to GND, when it is not necessary one is applied to OVP terminal. threshold voltage = feat Beer 1a ears Uc charactanencs WW OFF Stats The current value of I2 is about 150yA when the OVP does not and Vec will be kept at not so high or low but at the adequate reuse tS iiiat he ico larger curfanileoouA we voltage,when R1 shown in Fig.1 and 2 is selected properly. amAjthan I2 for riggeting the OVP operation, 2k The reason to decrease I2 is that it is necessary that Icc at the ON/OFF OVP rest supply voltage is small. It is necessary that OVP state holds by circuit current from R11 in the application example,so this IC has the characteristic of small Icc at the OVP reset supply voltage(~stand-by current + 20uA) a2 On the other hand,the circuit current is large in the higher ‘supply voltage,so the supply voltage of this IC doesn't become so high by the voltage drop across R1. Q3 This characteristic is shown in Fig.23. The OVP terminal input current in the voltage lower than the Q4 OVP threshold voltage is based on |2 and the input current in the voltage higher than the OVP threshold voltage is the sum of ena ald a Q4.0N 1 i the current flowing to the base of Q3 and the current flowing \\onga AT OPERATING! from the collector of Q2 to the base. ne For holding in the latch state, it is necessary that the OVP terminal voltage is kept in the voltage higher than Vae of Q3. So if the capacitor is connected between the OVP terminal and Fig.19 ON/OFF circuit GND, even though Q2 tums on in a moment by the surge voltage,etc,this latch action does not hold if the OVP terminal voltage does not become higher than Vee of Q3 by charging Veco this capacitor. For resetting OVP state, it is necessary to make the OVP terminal voltage lower than the OVP L threshold voltage or 30k~100kQ M51995A make Vcc lower than the OVP reset supply voltage. ON/OFF As the OVP reset voltage is settled on the rather high voltage of 9.0V,SMPS can be reset in rather short time from the switch-off of the AC power source if the smoothing capacitor is not so i large value. Fig.20 Connecting of ON/OFF terminal 1.6 § 12 FA c 08 a E a tad 0.4 0 5 10 15 20 25 30 SUPPLY VOLTAGE Vec(V) Fig.21 Icc vs.Vcc in OFF state (18 / 27 ) 2ENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL Output section Vec Itis required that the output circuit have the high sink and BS source abilities for MOS-FET drive. It is well known that the OQ} 100pA “totempole circuit has high sink and source ability. However, it 8k ; has the demerit of high through current. uy For example,the through current may reach such the high 12k current level of 1A,if type M51995A has the "conventional" totempole circuit.For the high frequency application such as higher than 100kHz,this through current is very important factor and will cause not only the large Icc current and the inevitable heat-up of IC but also the noise voltage. ro} This IC uses the improved totempole circuit,so without A | deteriorating the characteristic of operating speed, its through current is approximately 100mA. 400 ovro a3 BS APPLICATION NOTE OF TYPE M51995AP/FP ot, Design of start-up circuit and the power supply GNDO of Ic |1=0 when OVP operates Fig.22 Detail diagram of OVP circuit a Me nuscaimnecnaas” not necessary.to set the Fig.24 shows one of the example circuit diagram of the start-up circuit which is used when it is not necessary to set the start 8 and stop voltage. OVP RESET POINT It is recommended that the current more than 300A flows 7|--8.82V(-30°C) through R1 in order to overcome the operation start-up current _ 8,97V(25°C) IccistanT) and Cvcc is in the range of 10 to 47))F.The product of Z| 9.07\\e5°C) R1t by Cvcc causes the time delay of operation,so the response & time will be long if the product is too much large. eB 8 Ta=-30°C ———__+ RECTIFIED DC a eget ee 7 MAIN TRANSFORMER & Tes Tt SMOOTHING CAPACITOR ve —E 3

5 O 3} THIRD WINDING OR

Oo &) BIAS WINDING c 2 ZA tt ove a J o 5 10 1 2 2 30 35 40 SUPPLY VOLTAGE Vee(V) O Fig.23 CIRCUIT CURRENT VS. SUPPLY VOLTAGE (OVP OPERATION) Fig.24 Start-up circuit diagram when it is not necessary to set the start and stop input voltage Just after the start-up, the Ico current is supplied from Cvce,however,under the steady state condition ,IC will be supplied from the third winding or bias winding of transformer,the winding ratio of the third winding must be designed so that the induced voltage may be higher than the operation-stop voltage Vec(sToP). The Vcc voltage is recommended to be 12V to 17V as the normal and optimum gate voltage is 10 to 15V and the output voltage(VoH) of type M51995AP/FP is about(Vcc-2V). (19/ 27 ) ztENESAS

MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL Itis not necessary that the induced voltage is settled higher It is required that the Vin(starT) must be higher than Vin(sToP). than the operation start-up voltage Vec(sTarT),and the high gate When the third winding is the “fly back winding" or “reverse drive voltage causes high gate dissipation,on the other hand, too polarity",the Vinistarr) can be fixed,however, VinsToP) can not low gate drive voltage does not make the MOS-FET fully on- be settled by this system,so the auxiliary circuit is required. state or the saturation state. RECTIFIED DC Wa =) PRIMARY WINDING SMOOTHING CAPACITOR Neg} OF TRANSFORMER (3)Notice to the Vee, Vee line and GND line

4 To avoid the abnormal IC operation, it is recommended to

ra oft design the Vcc is not vary abruptly and has few spike voltage,which is induced from the stray capacity between the “ts winding of main transformer. O Ne THRO WNoINGor To reduce the spike voltage,the Cvco,which is connected

3 TRANSFORMER between Vee and ground,must have the good high frequency

characteristics. To design the conductor-pattern on PC board, following cautions + must be considered as shown in Fig.26. ie CVce {a)To separate the emitter line of type M51995A from the GND line of the IC (b)The locate the Cvcc as near as possible to type M51995A and connect directly O (c)To separate the collector line of type M51995A from the Voc line of the IC (d)To connect the ground terminals of peripheral parts of ICs to GND of type M51995A as short as possible Fig.25 Start-up circuit diagram when it is not necessary to set the start and stop input voltage cowuectonC) —vecC) 3 TRANSFORMER (2)The start-up circuit when it is not necessary to set the = THIRD start and stop input voltage SJ WINDING Itis recommend to use the third winding of “forward winding" O or "positive polarity" as shown in Fig.25,when the DC source creat Vee 24 voltages at both the IC operation start and stop must be settled at the specified values. Pill The input voltage(Vin(sTaRr)),at which the IC operation starts,is decided by R1 and R2 utilizing the low start-up current emitter C) O characteristics of type M51995AP/FP. The input voltage(VinistoP)), at which the IC operation stops,is decided by the ratio of third winding of transformer. The VinisTART) and Vin(sToP) are given by following equations. Fig.26 How to design the conductor-pattern of type M51995A on PC board(schematic example) Vin(sTaRT= RI * Ico + & 41) © VOC(START).sessssneee(9) (4)Power supply circuit for easy start-up Ne 4. When IC start to operate,the voltage of the Cvcc begins to winding of main-transformer as the Icc of the IC increases where abruptly.In case shown in Fig.24 and 25,some "unstable start- Icct is the operation start-up current of IC up" or “fall to start-up" may happen, as the charging interval of Vec(starn) is the operation start-up voltage of IC Cvcc is very short duration;that is the charging does occur only Vocistop) is the operation stop voltage of IC the duration while the induced winding voltage is higher than Vr is the forward voltage of rectifier diode the Cvcc voltage, if the induced winding voltage is nearly equal Vin(p-P) is the peak to peak ripple voltage of to the "operation-stop voltage" of type M51995. - Ne Itis recommended to use the 10 to 47uF for Cvcc1,and about 5 Vee terminal= +) Vin air(e-p) times capacity bigger than Cvcc1 for Cvcca in Fig.27. (20/ 27 ) 2ENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL At

2 TO MAIN

3} MAIN O 3} TRANSFORMER TRANSEORNE

3 THIRD RI

cveca ¥* [| Veo O ° pereee [END Ls] ‘THE TIME CONSTANT OF Fig.27 DC source circuit for stable start-up TES EAR SHOUD Be St0eT Fig.29 Example circuit diagram to make the OVP circuit OVP-reset-time fast (1)To avoid the miss operation of OVP Itis recommended to connect the capacitor between OVP 2 terminal and GND for avoiding the miss operation by the spike O J main noise. 3} TRANSFORMER The OVP terminal is connected with the sink current source 3 vanoins (=150pA) in IC when OVP does not operate, for absorbing the leak current of the photo coupler in the application. AO So the resistance between the OVP terminal and GND for leak- O a cut is not necessary. Vee If the resistance is connected,the supply current at the OVP reset supply voltage becomes large. As the result,the OVP reset supply voltage may become higher O eno than the operation stop voltage. In that case,the OVP action is reset when the OVP is triggered at the supply voltage a little high than the operation stop voltage. FIG.30 OVP setting method using the induced So it should be avoided absolutely to connect the resistance third winding voltage on fly back system between the OVP terminal and GND. (2)Application circuit to make the OVP-reset time fast The reset time may becomes problem when the discharge time constant of CFiN * (R1+R2) is long. Under such the circuit condition, it is recommended to discharge the Cvcc forcedly and to make the Vcc low value. This makes the OVP-reset time fast. O 10k (3)OVP setting method using the induced third winding |} voltage on fly back system For the over voltage protection (OVP),the induced fly back type M51995A G third winding voltage can be utilized,as the induced third ovp PHOTO COUPLER winding voltage depends on the output voltage.Fig.30 shows ze one of the example circuit diagram. O exo Fig.28 Peripheral circuit of OVP terminal (21 / 27 ) 2tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL Current limiting circuit e (1)Peripheral circuit of CLM+,CLM- terminal . A oO Fig.31 and 32 show the example circuit diagrams around the 3 a CLM+ and CLW- terminal.It is required to connect the low pass E> | filter,as the main current or drain current contains the spike current especially during the turn-on duration of MOS-FIT. 1,000pF to 22,000pF is recommended for CnF and the RNF1 4 and RiF2 have the functions both to adjust the "current- aia detecting-sensitivity" and to consist the low pass filter. {= rom (a) Feed forward system rn 24 INPUT CAPACITOR ovaare: + : i ae

22 Ove =

(b) Primary and secondary current Peper | be Fig.33 Primary and secondary current waveforms \\der th it limit ti Fig.31 Peripheral circuit diagram of CLM+ terminal condition on feed forward system crn 7 4 INPUT s SMOOTHING Voc} COLLECTOR 2 3 CAPACITOR omae) vour 3 s g ° & 2 2 Les E O Fig.34 Over current limiting curve on feed forward Fig.32 Peripheral circuit diagram of CLM- terminal syetem: To design the RvF1 and RvF2,it is required to consider the ; influence of CLM terminal source current(lincLM+ or INFCLM-), The demerit of the pulse by pulse current limiting system is that which value is in the range of 90 to 270pA. the output pulse width can not reduce to less than some value In order to be not influenced from these resistor paralleled value because of the delay time of low pass filter connected to the of RNF1 and RNF2,(RNFI/RNF2)is recommended to be less than CLM terminal and propagation delay time Trocum from CLM 1002. terminal to output terminal of type M51995A.The typical Teocum The Re. should be the non-inductive resistor. is 100ns. As the frequency becomes higher, the delay time must be shorter.And as the secondary output voltage becomes (2)Over current limiting curve higher,the dynamic range of on-duty must be wider,it means that it is required to make the on-duration much more narrower. pes ‘case ‘ot feed forward system So this system has the demerit at the higher oscillating Fig.33 shows the primary and secondary current wave-forms: frequency and higher output voltage applications. under the current limiting operation. . To improve these points,the oscillating frequency is set low At the typical application of pulse by pulse primary current using the characteristics of VF terminal.When the current detecting circuit,the secondary current depends on the primary limiting circuit operates under the over current condition,the current.As the peak value of secondary current is limited to oscillating frequency decreases in accordance with the ‘specified value,the characteristics curve of output voltage decrease of VF terminal voltage, if the VF is lower than (22/ 27 ) 7ENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL Under the condition of current limiting operation,the output current I2 continues as shown in Fig.33.So the output voltage w depends on the product of the input primary voltage ViN and the g on-duty. bs \\ If the third winding polarity is positive the Vec depends on $ <— OnHiROWNONG Vin,s0 it is concluded that the smoothed voltage of Vout 5 — VOLTAGE DECREASES terminal depends on the output DC voltage of the SMPS. 5 we UNDER SOPERATIONSTOP So the sharp current limiting characteristics will be got,if the a Vout voltage if feed back to VF terminal through low pass filter 8 ke as shown in Fig.36. 0c OUTPUT CURRENT Fig.37 Over current limiting curve on fly back system M51995A | vour F However,the M51995A will non-operate and operate AvEFe intermittently,as the Vec voltage rises in accordance with the dvr decrease of Icc current. The fly back system has the constant output power Crrre characteristics as shown in Fig.37 when the peak primary current and the operating frequency are constant. To control the increase of DC output current,the operating frequency is decreased using the characteristics of VF terminal . a when the over current limiting function begins to operate. Fig.35 Feed back loop through low pass filter from The voltage which mode by dividing the Vcc is applied to VF Vour to VF terminal terminal as shown in Fig.38,as the induced third winding voltage depends on the DC output voltage of SMPS. . 15kQ or less is recommended for R2 in Fig.38,it is noticed that Itis ceronnenaed to use 15k®2 for Rvrrs,and 10,000pF for the current flows through Rt and Re will superpose on the Cwrra in Fig.25: , lec(staat) current. Fig.36 shows how to control the knee point where the frequency Ifthe Ri is connected to Cvec? in Fig.27,the current flows becomes decrease. through Ri and R2 is independent of the Iccisaan. FROM TOVF FROM TOVF FROM TO VF vor WT voor vor Wet : T t Ove O 3 TO MAKE THE KNEE TO MAKE THE KNEE POINT HIGH POINT LOW Rt M51995A i+ Fig.36 How to control the knee point O Vee (b)In case of fly back system The DC output voltage of SMPS depends on the Vee voltage of type M51995A when the polarity of the third winding is negative and the system is fly back.So the operation of type M51995A Fig.38 Circuit diagram to make knee point low on will stop when the Vcc becomes lower than "Operation-stop fly back system voltage" of M51995A when the DC output voltage of SMPS decreases under specified value at over load condition. (c)Application circuit to keep the non-operating condition when over load current condition will continue for specified duration The CT terminal voltage will begin to rise and the capacitor connected to CT terminal will be charged-up,if the current limiting function starts,and VF terminal voltage decreases below VrxTime(~3V). If the charged-up CT terminal voltage is applied to OVP terminal through the level-shifter consisted of buffer transistor and resistor it makes type M51995A keep non-operating condition. (23 / 27 ) 7tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL Veo cT| cr Ba > M51995A % cai S45 vos-80v 0 ovel i 3 Vos=200V, g vos-320v < cao’ ca 3 cos

3 Gare: vo

= 10 a thecas Fig.39 Application circuit diagram to keep the © 2 “ non-operating condition when over load 3 current condition will continue for specified a 5 aoc ti duration ia i =n o Output circuit 0 ; ais 0 4 8 12 16 20 (1)The output terminal characteristics at the Vec voltage lower than the “Operation-stop" voltage TOTAL STORED GATE CHARGE(nC) TO MAIN Fig.41 The relation between applied gate-source TRANSFORMER voltage and stored gate charge vour en The charging and discharging current caused by this gate charge makes the gate power dissipation. The relation between took Rom gate drive current Io and total gate charge Qcsi is shown by following equation; Fig.40 Circuit di t ft the MOS-FIT gate Where ig.40 Circuit diagram to prevent the MOS-FIT gate «es ewitch 3 ‘potentialrising 9 fosc is switching frequency As the gate drive current may reach up to several tenths The output terminal has the current sink ability even though the milliamperes at 500kHz operation,depending on the size of Vcc voltage lower than the "Operation-stop" voltage or Vcc(stop) MOS-FIT,the power dissipation caused by the gate current can (it means that the terminal is "Output low state” and please refer not be neglected. characteristics of output low voltage versus sink current.) In this case following action will be considered to avoid heat This characteristics has the merit not to damage the MOS-FIT up of type M51995A. at the stop of operation when the Vcc voltage decreases lower (1) To attach the heat sink to type M51995A, than the voltage of Vec(stor),as the gate charge of MOS- (2) To use the printed circuit board with the good thermal FIT,which shows the capacitive load characteristics to the conductivity output terminalis drawn out rapidly. (3) To use the buffer circuit shown next section The output terminal has the draw-out ability above the Vcc voltage of 2V, however, lower than the 2V,\\t loses the ability and the output terminal potential may rise due to the leakage (3)Output butfer circuit current. Itis recommended to use the output buffer circuit as shown in In this case, it is recommended to connect the resistor of 100k2 Fig.42,when type M51995A drives the large capacitive load or between gate and source of MOS-FIT as shown in Fig.40. bipolar transistor. (2)MOS-FIT gate drive power dissipation Fig.41 shows the relation between the applied gate voltage and the stored gate charge. In the region (1) ,the charge is mainly stored at Cas as the depletion is spread and Cap is smalll owing to the off-state of MOS-FIT and the high drain voltage. In the region 2 ,the Cao is multiplied by the "mirror effect” as the characteristics of MOS-FIT transfers from off-state to on- state. In the region 3. ,both the Cap and Ces affect to the characteristics as the MOS-FIT is on-state and the drain voltage is low. (24/ 27 ) 7tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL Not to lack the output pulse,is recommended to connect the capacitor C4 as shown by broken line. Please take notice that the current flows through the R1 and R2 are superposed to Icc(start).Not to superpose,R1 is connected vour to Cvec2 as shown in Fig.27. O a P How to get the narrow pulse width during the start of operation Fig.45 shows how to get the narrow pulse width during the start of the operation. If the pulse train of forcedly narrowed pulse- e — width continues too long,the misstart of operation may Fig.42 Output buffer circuit diagram happen,so it is recommended to make the output pulse width narrow only for a few pulse at the start of operation.0.1pF is DET recommended for the C. Fig.43 shows how to use the DET circuit for the voltage detector re and error amplifier. For the phase shift compensation jit is recommended to M51995A connected the CR network between det terminal and F/B 1002 terminal. topHoTo lL ¢ COUPLER ii 7 ct DETECTING - fs an VOLTAGE Fig.45 How to get the narrow pulse width Fe during the start of operation c2 Ra a se M51995A DET 8 How to synchronize with external circuit a ‘Type M51995A has no function to synchronize with external Re circuit,however, there is some application circuit for synchronization as shown in Fig.46.If this circuit is used,the synchronization may be out of order at the overload condition when the current limiting function starts to operate and VF Fig.43 How to use the DET circuit for the voltage terminal voltage becomes lower than 3V. detector Fig.44 shows the gain-frequency characteristics between point B and point C shown in Fig.43. M51995A The G1o1 and«2 are given by following equations; Gt= F3_ Ton of tore cr PAIR esesssestecsessestntesenetntnsenee(11) ee—t O O O O COS RG spearcsnrracisrasincisiacssnal( 12) ape C1402 a = Che CO 0 FAQ crrenreeeseeetneeseneeneenns(13) RON 12000 At the start of the operation,there happen to be no output pulse q C_| SyNGHRONOD due to F/B terminal current through C1 and C2,as the potential s of F/B terminal rises sharply just after the start of the operation. PULSE —> Gaver (OC VOLTAGE GAIN) g = 8 Zs ge Toe 41 42 go : 9 ge ‘ 4 Fig.44 Gain-frequency characteristics between os point B and C shown in Fig.43 7 ov ze Fate] y BE ow MINIMUM PULSE“ k™ WIDTH OF MAXIMUM PULSE WIDTH OF ieee NOUS SYNCHRONOUS PULSE Fig.46 How to synchronize with external circuit (25 / 27 ) 2ENESAS

MITSUBISHI (Dig./Ana. INTERFACE) SWITCHING REGULATOR CONTROL o 9 sense ve os j Vour M51995A O “vss Oo 9 Fig.47 Driver circuit diagram (1) for bipolar transistor COLLECTOR | Driver circuit for bipolar transistor When the bipolar transistor is used instead of MOS-FIT, the vee vour base current of bipolar transistor must be sinked by the BIPOLAR negative base voltage source for the switching-off duration, in M51995A TRANSISTOR order to make the switching speed of bipolar transistor fast one. In this case,over current can not be detected by detecting GND EMITTER resistor in series to bipolar transistor,so it is recommended to use the CT (current transformer). For the low current rating transistor, type M51995A can drive it directly as shown in Fig.48. Fig.48 Driver circuit diagram (2) for bipolar transistor Attention for heat generation The maximum ambient temperature of type M51995A is +85°C,however,the ambient temperature in vicinity of the IC is not uniform and varies place by place,as the amount of power dissipation is fearfully large and the power dissipation is generated locally in the switching regulator. So it is one of the good idea to check the IC package temperature. The temperature difference between IC junction and the surface of IC package is 15°C or less,when the IC junction temperature is measured by temperature dependency of forward voltage of pin junction,and IC package temperature is measured by "thermo- viewer",and also the IC is mounted on the “phenol-base* PC board in normal atmosphere. So it is concluded that the maximum case temperature(surface temperature of IC) rating is 120°C with adequate margin. ‘As type M51995 has the modified totempole driver circuit, the transient through current is very small and the total power H-Axis : 2onsidiv dissipation is decreased to the reasonable power level.Fig.49 V-Axis: SOmA/div shows the transient rush (through)current waveforms at the rising AT RISING EDGE OF OUTPUT PULSE and falling edges of output pulse,respectively. H-Axis : 20ns/div V-Axis : 10mA/diV AT RISING EDGE OF OUTPUT PULSE Fig.49 Through current waveform of totempole driver circuit at no-load and Vcc of 18V condition (26 / 27 ) 2tENESAS

MITSUBISHI (Dig./Ana. INTERFACE) M51995AP/FP SWITCHING REGULATOR CONTROL APPLICATION EXAMPLE Feed forward types SMPS with multi-output. 3\\| 5 Voure AC >| 311 € COLLECTOR | S = Your Voc >| i = = 7 VouT1 M51995AP Re 3 | wi zo 3 Fa o ens C 9 HE — Pe RS ir LA ion. \\RorF A ™¥ ON/OFF (27/ 27) 7tENESAS

Summary

SWITCHING REGULATOR CONTROL

Description

M51995A is the primary switching regulator controller which is especially designed to get the regulated DC voltage from AC power supply.

Source title M51995 Datasheet(PDF) - Renesas Technology Corp

Read M51995 online.