M51362SP RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 7tENESAS Renesas Technology Corp.

MITSUBISHI ICs (TV) - PLL-SPLIT VIF/SIF DESCRIPTION: 7 PIN CONFIGURATION (TOP VIEW) The MS1362SP is a semiconductor IC consisting of IF signal processor suitable for color TV sets and VCRs with AV : i AF AGC OUTPUT (REVERSE) [So VIDEO INPUT uebich is aicevision) of MBtSeecr, VIDEO NEGATIVE FEEDBACK [2s] CONTROL OUTPUT The circuit includes VIF amplifier, Video detector, VCO, APC | equaLizeR OUTPUT [4] [a] VIDEO OUTPUT detector, AFT, video equalizer, IF/RF AGC, SIF detector, RF AGC DELAY G4] (27) SIF limiter, FM detector functions. Nec WIP) Ca} fy J AFT COL g : IF AGC FILTER [6] = [Barc FILTER GND (vif) Z} 2 fd GND (vco) ia sleet caeuaina € F input { ie 8 2 } veo com @A full synchronous detector circuit using PLL as video enD (sift fA Vcc avon detector provides excellent DG, DP, 920kHz beat and SIF det. INPUT [i [20] CONTROL FILTER cross color characteristics. Vec (SIF) [i] [is] AUDIO OUTPUT @ The PLL-SPLIT method in which video IF and audio IF LIMITE ease Ea 5 }rm det. COIL signal processings are separated and VCO output is used SIF det. OUTPUT [5] fig} AFT OUTPUT to obtain intercarrier provides good sound sensitivity and reduces buzz. In consumer sets, intercarrieris alsoavailable from the video detector output. Outline 30P4B © Built-in video equalizer is suitable for VCRs and color TV sets equipped with video output terminals. @ The quadrature detector circuit for FM detector has good linearity with a simple coil. @ The M51362SP has better video S/N ratio than MS1365SP by 2~4aB.

APPLICATIONS

TV sets, VCR tuners RECOMMENDED OPERATING CONDITIONS Supply voltage range ...cscsscecctseetntestetienteeB=10V Rated Supply Voltage ..ecesecsovcsscuetnenerentaeaee OV BLOCK DIAGRAM AUDIO AFT voo OUTPUT FM DET. VIDEO COL APC Cok CONTROL colt H GND (vco) ppl @ i | “ @1) vec (VCO) Lock PHASE FM VIDEO INPUT GO) i. C1 (16) AFT OUTPUT BE || [eee I unvesrer| | [DETECTOR |} ‘ ! [seat LIMITER GND (viF) (7) ss a 12) Voc (SIF) AMPLIFIER EQUALIZER RF iF 1 GND (SIF) (0) 3 AGC AGC fk Y 1ST IF SIF | (9 SIF DET RF AGC AMPLIFIER: DETECTOR OUTPUT ourput (1) H (REVERSE) T | video EQUALIZER =| IF AGC — SIF DET. UIMITER BYPASS NEGATIVE OUTPUT pe lage FILTER IF INPUT INPUT INPUT FEEDBACK DELAY 2-176 2tENESAS

MITSUBISHI ICs (TV) PLL-SPLIT VIF/SIF a ABSOLUTE MAXIMUM RATINGS Ratings | Pa | Power dissipation 1250 = 20~75, . = 40~125 ELECTRICAL CHARACTERISTICS (Ta = 25°C, Vcc = 9V unless otherwise noted) VIF SECTION Test Test_conditions Symbol Parameter : %* Switches should Tr Max. | Unit point Vie [SIFT] Vi | Ve | Vz0| usually be set to 1. ue: [ tcc (VIF)| Circuit current (VIF) [iT At| = | = [3 | = [| = [swi=2 [33 [45 [57 | ma | Video detector output i [vm | oer [:]rre| -[- | 2 [0 | - [swa2 a| se) &| 7 Video detector output = | Vo ett | Video detector outout i] [TPe|sci] — [3 | = [= | | Vo cere | Video detector outout 41 [Te2|sci] = [3 [= | = | | 16 [195 [23°] Ve-r | | P/N | Video S/N frtojsce] = [3 | = | = [swe=2 coen[ 44 | sat | 8 | | Bw | Vieeo treauncy charsteristies [7 [TP9|SG3] = [3 [= [= | Gated] 85 | 75 |_| Miz | [ Vin (mind [input sensitivity [1 [TPelscal = [3 [= [= | a | Vin (mas) | Maximum af lovable input| 1 [TP9|scs] ~ [3 [ - | = | care | 107 | 110 [Bu | | GR | AGC control range [7 - | = |= [=| - | =| coe | 68 | 64] | a8 | IF AGC maximum voltage |1|TP3| - | - | 3 | - |= | | 65 | 86{ | Vv | Vu | IF AGC minimum voltage [1 |TP3|sG7| - | 3 [= | = | [34 { 39] 44} Vv] SIF det. [ves | tency [4528] 2 | - | - | | 194 | 190 | 14 | eee | Vo sie-2 | SIF det. Tp4|sc2|sc9| 3 dB uw 4, 5MHz_ output (8048 1.) [ Vie | AFT output voltage [1 [TPs] - | - | 3 [0 |=] [ 32] 43 [54 [Vv | | «| AFT detector sensitivity 1[TP5|scio| = | 3 [ = | = | ote [48 | 70 | 92 [nv/kte | | View | AFT maximum voltage |i |TP5|séi0| - [73 | - | = | cued] 8 | a7 [Tv] | Vie. | AFT minimum voltage |1[TP5|scio| - | 3 | - | - | coeo| | 038 | 1.0 | V_ | | Vix | RF AGC maximum voltage |1[TPI/sG2[ — | 2 | = | = | 7{ 78s {| vt | Vic___| AF AGC minimum voltage [1 [TPi[sGa[ = | 4 | = | = | [fof oT Vv | CL-U1 | Capture range (U) [1 |TPa|scni[ = | 3 [= | = | (ore 9 {0.45 [0.8 [| Mee | | CL=L1 | Capture range Cy [1 |Tre|scni[ = | 3 [= | = | oowio[ 14 [20 [| Miz | | cL-T | Capture range 7) [1] = | = |= | - [=] | Goon [20 | 28 [|] Miz | | CL-U2 | Capture range (U) [1 |TP9|sci| - | 3 | - |= [swe=2 Goo 9 | 0.45 [08 | 1.2 | MHz | | CL=L2 | Capture range (L) [1 [TPe|scni[ - | 3 | - | - |[swe=2 tote | 1.0 | 1.6 | 22 | Mrz | | Vaor | Lock detector testo volta [1 [TPB] - [= | 3 [5 [Ba [Sw345=2 coeiaf 36 [40 | 44 | V_| | Veo. | Minimum voltage at sin @|1 [TPS] - | - | 3 [5 | wa [Ssw345=2 coea| [005 | os | Vv | EQ frequency TPS) feter to fer Seiems bo| [a] =-[-[0 anal va ae] ae | EQ frequency TPS fer to rea [Swans 2 [fore] ~ | [= | =| cers] 2 | s7| 72] a | EQ frequency TPS fater to reo | Swwaseice 3 | reas = | 9 [= [=| rs] 95 | 0 | us| | [os [oc i fr ej sere = 3 T= T= | a ee Lop or i rPajscief = 3 T= T= | Gore [2 TS des. | te Y sENESAS —

MITSUBISHI ICs (TV) : PLL-SPLIT VIF/SIF VIF SECTION (cont.) ea Test conditions Symbol Parameter [input signal] eee’ | & Switches should Min. | 7; Unit pape!’ VIF [SIF1 usually be set to 1. p || =v Black spot inverter Vari -

5 Black spot inverter Vari ’

| svc _| Syne tip level at pin @1 |TR2|SG2[ - | 3 | — [= | Rin (V)_| VIF input resistance [2[leoul - [3 | - | — | | | oo [| ke | [ Gin CW) | ViF input capacitance [2[~ Javeu| - | 3 | — | — | | | 66 [| oF | Rin (S1)| SIF1 input resistance [2] | — [eowul 3 [ = [= | [ [ar yy ka | Gin (S1) | SIF1_ input capacitance |2[ | = Joweu] 3 | = [= | ee 2 SIF SECTION rest Test conditions Symbol Parameter input signal] 83530 a" Switches should 7 i Unit pipontsir2] | Vi | Ve | V20] usually be set to 1. ue | Ma toc (SIF) Cirouit current (SIF) [i [a2] = [| 0 | = | = [sw2=2 | 61 | 87 | 114 | mA | | Vio__[ AF output DC voltage |1 [TPS] — [| o | = [= | | 41 [49 | 57] v | | Voarwax | Maximum AF outout_|1[TP6|s6I7| | 0 | - | — | [225 | 300 | 375 |mVrms| AF cutout distortion [1 [T9|s621} || =| —| [ fozt 10] % | Vin Cimn)| input limiting sensitiv] 1|7TP6|s618] oT — | — | or a [awa [awa Tr [tPe|scigy Po} = | — | cw | Se] ea] | 8 | AF S/N [ifree|sezoy To T= T= | ow 2) | 58 [73 [8 | ELECTRICAL CHARACTERISTICS TEST METHOD Note4. Maximum allowable input “Vin (max” Note1. Video S/N “P/N” a.Set SG5 to 90dBu and input it in VIF IN. a.Input SG6 in VIF IN. b.Detector output at pin @ at this time is defined as b. The noise appearing at pin @ is determined by measur- V2. ing the r.m.s. voltage at TP10 through low pass filter c. Increase the voltage of SG5 and voltage at which detector (-3dB at 5MHz). output reaches 3dB less than V2 is defined as maximum Vodet_1 (Ver) x 0.7 allowable input. G.PIN = 20 fog { ee | Note5 AGC control range “GR” where Vodet 1 denotes video detector output 1 a.AGC control range is defined as follows: Note2. Video frequency characteristics “Bw” GR = Maximum allowable input - Input sensitivity a.Set SG3 as follows: Note6 AFT detector sensitivity “1” fy = 58.75MHz‘ Vi = 90dBu . a.Input SG10 in VIF IN. j mixed signal i fz = 57.75MHz Vi = 70dBu } b.Measure difference cf frequency between 3.0V and 6.0V of DC voltage at TPS and the difference is defined b.Measure the element of 1MHz at TP9 and the result as Af. is defined as V1. c.AFT detector sensitivity 1 is defined as follows: c. Decrease the frequency until element (fi-f2) at TP9 3000mV (mvikH2) reaches 3dB less than Vi. Then, read the frequency. Be “AF (kHz) d.Bw = 58.75 - f2 (MHz) i Note3. Input sensitivity “Vin (min)” vie a.Input SG4 in VIF IN. ev SEEshs. b. Decrease the SG4 level and the level at which detector output at pin @ reaches 3dB less than Vodet 1 is defined vet as input sensitivity. wv SRR n A ' View fo 58,75MH2 ume) 2-178 2tENESAS

MITSUBISHI ICs (TV) M51362SP - PLL-SPLIT VIF/SIF i Note7. AFT maximum voltage “Vicx” c. Observe TP9 with spectrum analyzer at this time, and a.Maximum DC voltage in the figure on the previous the ratio of the 920kHz level to the 3.58MHz level is page is defined as VieH. defined as intermodulation. Note8. AFT minimum voltage “V:6.” b. Minimum DC voltage in the figure on the previous page is defined as Viet. Note9. Capture range (U) “CL-U-1,” “CL-U-2” a a.Input SG11 in VIF IN and increase the frequency til VCO lock is released. b.Decrease the frequency of SG11 and the frequency Note16.DG, DP “DG, DP” at which VCO locks again is defined as fv (MHz). a. Modulated waves of SG16 is generated by 87.5% video c.Capture range (U) is defined as fv - 58.75 (MHz). modulation of the 10-step waves as shown in the figure Note10. Capture range (L) “CL-L-1,” “CL-2” below. a.Input SG11 in VIF IN and decrease the frequency till b.Measure DG and DP at TP9 with vectorscope VCO lock is released. b.Increase the frequency of SG11 and the frequency at dt which VCO locks again is defined as fi (MHz). 10% c. Capture range (L) is defined as 58.75 - fi (MHz). ia Note11.Capture range (T) “CT-T" 70 a."CL-T" is defined as “CL-U-1" + “CL-L-1" (MHz) vo 10026 Note12.Lock detector threshold voltage “VzoTH” a.Set the voltage at Vz to 3V and observe TP8. b.Increase the voltage at Vz0 and the point at which SUBCARRIER 3.58MHz 40% TP8 voltage changes drastically is defined as Vzom4 (threshold 1V) Note17. Black spot inverter threshold level, clamp level TPs, “Ve tH, Ve cu” VOLTAGE a.Input SG1 in VIF IN. b, By varying Ve, output the waveform as shown in the aa figure below to TP2 and measure each DC voltage. V20 act ----— VetH----- Note13.Minimum voltage at pin @ “Vz0.” TEST POINT a.Minimum voltage in Note12 is defined as V2o. Note14. EQ frequency characteristics “FC1”"FC2”“FC3” —Note1g input limiting sensitivity “Vin amy” a,Inpitt ‘SG12,<SG13 OF SG14"to"VIF IN ; a.Set SG18 to 8OdBK and input it in SIF2 IN. b.Measure the level of element (fr-fz) at TP9 and it is, Decrease the output level of SG18 until detector output defined as Veo w (dBu) ; at TP6 becomes 3dBi smaller than Vo AF MAK. Bay sein Cy liven) ermeet siciset We ane Whe The level of SG18 at this time is input limiting sensitivity. defined as Veo ovr (By). Note19.AMR “AMAR” d.£Q frequency characteristics is defined as follows: a.Input $G19 in SIF2 IN. FO i=3i=iMeaiours= Vea' (dB) b.Measure the output voltage at TP6 and it is defined Note15. Intermodulation “IM” as Vam. a.Input $615 in VIF IN c.AMR is defined as follows: b. Observe TP9 with oscilloscope, and adjust the voltage vere aaa aay of Ve so that the minimum level of detector output AMR = 20 log {eo } (dB) waveform will come to 2V. 2tENESAS oz 178

MITSUBISHI ICs (TV) . PLL-SPLIT VIF/SIF i ree Note20.AF S/N “S/N” INPUT SIGNAL a.Input SG20 in SIF2 IN. Signals (0 Q termination) b.Measure the output voltage at TP6 and it is defined fo-58, 75Mz Vie900B 7. TBKMM (fanensis ™) as Ww. teeta c.AF SIN is defined as follows: eet vn Soe in 1 = 58.75MHz Vi=90d8 HY SIN = 20 log [ Somes tims) ae Max imine) } (aB) f2= 832 BMre Vi= Todd u } Med sional Vw (mVrms) fo=58.75MHz Vi=Vaviable fm= 20kHz 77.78 %Al fo= 58.75MHz Vi= Vaviable fm = 20kHz 169% AM %* Amplitude level of all AM modulated waves are the — [SG6”| fo = 58.75MHz Vi = 8008 p peak level of modulated waves. fo = 58.75MHz Vi= 11008 u * The following is used for the mixer: | SG8_| fo =54.25MHz Vi= 100dB w : ['SG9_| fo = 54.25MHz Vi = 8008 n fo = 58.75MHz + SMHz Vi = 90dB p 25 0-58. 75MHz = SMHz Vi=90dB yu _fa=2Okliz 77. TBKAN fi = 58.75MHz Vi = 90dB y . wi wy fe=58.25MH2 Vi = 60dB yf 2d sional f1 = 58.75MHz Vi = 90dB uy ., . ee fo= BS.75MHz Vi= 6008 u_} Tixed sional 1 = 58.75MHz Viz 90dBu Yo f2= BATEMHe Vi= 6008» } 0d signal * With Vco coil, IF AGC OV and non-input condition, adjust fr = 58.75MHz Vi= 9008 u free run frequency to 58.75MHz. $G15 | f2=55.17MHz Vi = 80dB p rire signal fo = 54,25MHz Vi = 8008 u SGi6 fo = 58.75MHz standard 10— step modulation m = 87.5% video modulation, sync tip level 90d8 u| fo = 4.5MHz +25kHz dev Vi=100dB u_fm =400Hz fo = 4.5MHz +25kHZ dev Vi=Vaviable fm =400Hz fo=4.5MHz Vi= 10008 u 30%AM fn = 400Hz $620 | fo = 4.5MHz Vi= 10008 u fo=4.5MHz Vi=100dBu fm =400H2+7.5kH2 dev SSE EE a RENESAS

MITSUBISHI ICs (TV) PLL-SPLIT VIF/SIF TEST CIRCUIT 1 vee “- TP9 : ° 2k = S560 2 TP10 i! 1 S100 1 bd ‘85-1 85-2 TP6 ¢i0 mi 70.015 » 12u 68u3 v0 O47 ul Hoorn p+] 84 Voc 4.5MHz oTP8” 4] a7 u PN ay (0006 TRAP H 92) 7.5K COIL FOR 300k 0 4.5MHz

9 TPT =D Tr 3k oTPS

Lg V20 0.01 wT (20]_fes]_[28) [27] [26] fes) f24] fea] fee) [21] [20] [rs] fie) [r7] fie) M51362SP UL] Baler Ls] [s] Wel bo Ty] a [5] TP o—{68 yu forw Vee! 5/8 0.01 uw ¢ | TP3 Loaoo) SiS 910 + | 150 [ g [ssl | (ory fist geeut Jaz a] 27 le f 50 50 TP4 ame Se |e azoxy ve O50 777 SIF2IN J Herts Oa 0.01 u} =r 47 82u T= 868 w * a al s2 on 9 6: ° vee ° o2 a? Aa. Units Resistance: @ Capacitance: F TEST CIRCUIT 2 Veo = 9V 0 0.01 n (0.01 a 0.01 if it too 4 fe] (| el fe] Be] sl fee) al 2] Bil fol Gl “@] [7] fie] Ms1362SP wld bya 0.01 Vio = ot al ot w 10k + [Hi rx If [Hi rx Lo Lo Units Resistance: Q Capacitance: F 2tENESAS 2 - 181

MITSUBISHI ICs (TV) M51362SP . * PLL-SPLIT VIF/SIF TYPICAL CHARACTERISTICS THERMAL DERATING (MAXIMUM RATING) ro ee Nee 2 os N got | IN I | gee ER a a 04 zt | i th oe -200 2 50 75 100 125 AMBIENT TEMPERATURE To (‘C) APPLICATION EXAMPLE vec 9Vo H SGP peoxs apt oH 4. pe bee ES i aa Lock AFT PHASE + bertronl conTROL perecror PEIECTOS CH me ae - al las SIE om i f | [1 Titel Total ye ee ea RE AGC z= No abe = I RF AGC ose Le FE 23 a 3 vec SIF veo Tuner Units Resistance: Q Capacitance: F oo RENESAS

MITSUBISHI ICs (TV) M51362SP . PLL-SPLIT VIF/SIF ___ DESCRIPTION OF PIN 8 3 ° ett pa) : : Lavy -— Mn EET bo in f a g¢ #8 a3 ¥ wel é = @s8 rand © = om : SAE) 3 - he 3 By g ie ke fry . Bg roatalat . te s se 8 ; % a oa “ ma Ed 8 Fe ae) ae mo ; ; 8 a : or! pT ae z C18 3 28 a] spat : - mv : sh et | Felt I a ee | 8 z é S5 25 3 fy $ = g 2° BB g* a ztENESAS _—

MITSUBISHI ICs (TV) M51362SP . PLL-SPLIT VIF/SIF _.. PRECAUTIONS FOR APPLICATION The lock detector determines locked/unlocked conditions 1.VIF Amplifier by the average level of detector output. The VIF amplifier is a two-stage amplifier without DC In pin @, the threshold is 3.2V. feedback. The time constant switch is pin @. With a gain of approx. 40dB, the VIF amplifier is connected The VCO circuit diagram is shown to the right, and illustrates to a video detector via an internal capacitor. how sinking current is varied to adjust frequency. Maximum input amplitude is determined by the input The variable range falls between -1.7MHz and +1.3MHz dynamic range of the VIF amplifier, allowing up to 110dBu —at_@ capacity of 27PF (45.75MHz). input. During excessive input, surpassing this limit will cause ‘The variable range widens as the capacity decreases, while the linearity to worsen, while leaving amplitude unchanged. _the temperature drift characteristic and harmonics worsen. Since gain control has the characteristic that AGC speed Vec and GND of the VCO section are independent of those is fastest in the range 50~60dBu, to prevent sag, select of the VIF, while the same DC voltage must be supplied an appropriate filter time constant. as for the VIF. IF input impedance is approx. 1KQ and must be input in balanced type. { 2.Video Detector, PLL Section Vee The PLL system produces a pure carrier wave. The PLL is locked as shown in the diagram below. The VIDEO DET and APC DET employ a double balanced mixer. Detector output (pin @) is 1.5Ve- (Vee = QV, negative sync). Detector output is almost proportional to supply voltage. Pin @ is an emitter follower, containing a 2KQ emitter resistor, and requires an externally attached resistor ({2KQ~1KQ) as it is insufficient alone to drive a 4.5MHz ImA imA trap. Pin28 output waveform wrerencnecenancane> .d76V 3.SIF Det. 4.5MHz issues from pin @, however, for M51362SP, Toetsesdecpaacecaa= 3.20 joa Set inputting 41.25MHz thru pin ® causes 4.5MHz to be output from pin ®, the product of multiplying 45.75MHz by the carrier wave gained at the VCO. Since conversion gain is 18dB, which is constant, note that at a lower level than the delay point, the output level is eee ov, also lowered linearly. Input impedance is approx. 2KQ, output pin ® is an emitter VIDEO DET follower type circuit, current sink is 0.6mA, and a 3002 resistor is connected in series. y The AFT circuit is of the conventional type. Output is also az of the conventional current-drive type. APC Since internal operating current is reduced, use a load resistor ET three times larger than the conventional one. A defeat vco E terminal is not provided here. Therefore, using the middie point in the coil between pins ® and @, lower the voltage of pins @ and @ to less than 1V. The internal resistor of pins @ and @ is 6KQ. Sees — RENESAS

MITSUBISHI ICs (TV) M51362SP PLL-SPLIT VIF/SIF ee a nee 5.IF/RF AGC terminal. ~" “IF AGC input is applied from pin @ Video Out. > 4.5MHz The resistor between pins ® and @ is provided to prevent trap > pin @ to PNP emitter follower. parasitic oscillation. The IF AGC amplifier is a two-stage amplifier, with pin © The FM detector employs a quadrature detection method & pin @ serving as a filter terminal. and requires a tank coil and damping resistor at pins ® Output to pin © is a current-drive type, and a current sink and ®. is 0.5mA, Note that use of a ceramic discriminator would not obtain The RF AGC is a reverse output type; its pin © output a good characteristic. is illustrated in the figure to the right. Pin ® audio output also employs an emitter follower and Output voltage is (7.8V~OV) at Vec = 9V. the output impedance is approx. 7002. Black spot inverter works before EQ amp. Voltage lower than sync chip by 0.45V (pin @) is to be threshold. Principle of M51362SP PLL Section Clamp voltage is nearly at the white level. M51362SP's PLL section is formed as shown in Fig. 1. Vec The locked loop is indiceted by broken lines. The APC and video detector are double balance-type 280 1.9k multipliers, and the LPF \\s a lag-lead filter with external CR. The APC detector is a phase comparator and outputs voltage corresponding to the phase: difference between the IF signal and VCO output (output through +45° phase shift device). 200 10k Video det. output 330 aerial 2 pate ihe c] | device 6.EQ Amplitier B) [yas Basically, the EQ amplifier is as shown in the diagram to _ the right. get]! 1 device Providing the feedback to pin @, it has the frequency H 4 characteristic. —— It can also be used as an amplifier with a fixed gain. Vee HH Fig .1 QQ The phase comparator usually has such a characteristic as 15k the one illustrated in Fig. 2: When the phase angle of B is +90° out-of-phase for the IF signal, the APC output current ® becomes 0, while APC output current becomes positive 500 2) when the phase angle lags. APC output current 500 2.5k 0.75mA 0.25mA —90° o tC) 180° 7-GIr Seeten 80° 8 point relative As Vcc and GND of the SIF section are independent of phase for IF signal those of the VIF, the supply voltage of the SIF section can be changed. The limiter amplifier is a triple amplification device, including an internal differential amplifier. Pin @ is a DC feedback Fig..2 APC Detector ~ 2tENESAS 2 - 185

MITSUBISHI ICs (TV) * PLL-SPLIT VIF/SIF Output current is converted into voltage, and unnecessary When the M51362SPs in the non-locked state and a locked “" "frequency is cut off via LPF. Then, the voltage is applied condition is detected, the LPF time constant is reduced to VCO as controlled voltage. Here, the VCO characteristic to widen the capture range. is shown in Fig. 3, and for the IF signal, the phase at The frequency response characteristic under the locked state B relative to the IF signal is -90°. is shown in Fig. 4; cut-off frequency is approx. 100KHz, The procedure by which the VCO follows the IF signal is and is equivalent to the bandwidth of the carrier wave described below: For example, when the phase of the IF reproduced from the IF signal. signal lags (the phase at B relative to the IF signal leads Here, the AM detector section is now described. If, in Fig. more than -90°), APC output current becomes positive, 5, the phase at point B is locked at -90°, phase lags by controlled current increases, frequency tends to decrease 45° at point A, this means the IF signal carrier wave will and, consequently, the phase lags. be -135°. So at point B, the VCO locked in phase angle is -90°. Consequently, the carrier wave phase at point C, where Meanwhile, when the frequency of the IF signal becomes the signal is input into the video detector, lags by an additional high, APC output is negative, controlled voltage decreases, | 45°, producing -180° (out-of-phase). and the VCO frequency becomes higher, because the A correct phase produces the most complete and effective instantaneous phase is equivalent to leading. demodulation of the video signal. (See Fig. 5). However, with phase error inversely proportional to loop - Phase at Each Point gain, the VCO locks. . Phase of IF Oscillation c > signal carrier frequency —180° wave A Freetun fol -~---~~ 135° : 8 1 —g90° ' Fig.5 H Controlled f voltage Fig. illustrates the basic circuit of the phase shift device. Ratevence Each phase shift device comprises an LPF (45°), an HPF voltage (+45°) having simple C and R and set so that the phase Fig..3 VCO Characteristic will rotate by +45° at 45.75MHz. Free-run frequency is oscillation frequency produced when —_ Consequently, although the phase rotation varies in the other center voltage is applied to the VCO. IF band, the relative phase angle is 90°, independent of When locked, the input frequency lock range depends on _ frequency, as the values of R and C are set equal to one the variable frequency range, and the lower loop gainnarrows —_ another. this range. Description of the capture procedure for the VIDEO IF signal is omitted here due to its complexity. The capture DET range is narrower than that of the lock in relation to loop : pe —45° vco gain, and narrower than the LPF bandwidth. bias = output Detector output c R ace +45 after LPF Noniockes — R Cc << *s. APC ~ DET 100KHz FM modulation te.6 frequency Fig. 4 52 ie 2tENESAS

MITSUBISHI ICs (TV) M51362SP PLL-SPLIT VIF/SIF ——— $e _ SPECIAL PARTS Coil Specification f = 45.75MHz ‘ 1) VCO coil pin @, @ Qu ColpF) Turns Bobbin Wire 92420% 27 (1-6) 6t 10K type 0.120 Stray 2 OUEW Variable range widens as Co is reduced. 2) AFT coil pin @, @ Qu ColpF) Turns Bobbin Wire 84420% 5946% (1-6) 4. 10K type 0.120

4 OUEW

3) SIF coil pin ® Filter passing only 41.25MHz. Can be used in AFT coil. When SAW filter (41.25MHz) is used, compensation for loss is necessary. 4) SIF FM det. coil pin @, ® Qu ColpF) Turns Bobbin Wire 60£20% 68pF (4-6) 36t. ‘10K type 0.120 OUEW —_.]. stENESAS a