M48T35AV_07 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 28
Technical content
Datasheet sections
- 1 Description
- 2 Operation modes
- 2.1 Read mode
- 2.2 Write mode
- 2.3 Data retention mode
- 3 Clock operations
- 3.1 Reading the clock
- 3.2 Setting the clock
- 3.3 Stopping and starting the oscillator
- 3.4 Calibrating the clock
- 3.5 Century bit
- 4 Maximum rating
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Part numbering
- 8 Revision history
Features
■ Integrated, ultra low power SRAM, real-time clock, power-fail control circuit and battery ■ BYTEWIDE™ RAM-like clock access ■ BCD coded year, month, day, date, hours, minutes, and seconds ■ Battery low flag (BOK) ■ Frequency test output for real-time clock ■ Automatic power-fail chip deselect and write protection ■ Write protect voltages PFD = Power-fail deselect voltage): –M 4 8 T 3 5 A Y : VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V –M 4 8 T 3 5 A V : VCC = 3.0 to 3.6V 2.7V ≤ VPFD ≤ 3.0V ■ Self-contained battery and crystal in the CAPHAT™ DIP package ■ SOIC package provides direct connection for a SNAPHAT ® housing containing the battery and crystal ■ SNAPHAT® housing (battery and crystal) is replaceable ■ Pin and function compatible with JEDEC standard 32Kbit x 8 SRAMs ■ RoHS compliant – Lead-free second level interconnect PCDIP28 (PC) battery/crystal CAPHAT SNAPHAT (SH) battery/crystal SOH28 (MH)
1 Description
battery backed-up memory and real-time clock solution. the number of WRITEs that can be performed. a long-life lithium button cell in a single package. Figure 1. Logic diagram
Figure 4. Block diagram
2 Operation modes
BYTEWIDE™ clock information in the bytes with addresses 7FF8h-7FFFh. to the clock information and also stores the clock calibration setting. clock control circuit which updates the clock bytes with current information once per second. maintains data and clock operation until valid power returns. Table 2. Operating modes Note: X = V IH or VIL; VSO = Battery back-up switchover voltage.
2.1 Read mode
that the E and G access times are also satisfied. Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV).
- See Table 11 on page 21 for details.
for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. Figure 5. Read mode AC waveforms Note: WRITE Enable (W ) = High. Table 3. Read mode AC characteristics
- Valid for ambient operating temperature: T A = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted).
2.2 Write mode
and G, a low on W will disable the outputs tWLQZ after W falls. Figure 6. Write enable controlled, write mode AC waveform Figure 7. Chip enable controlled, write mode AC waveforms
Table 4. Write mode AC characteristics
2.3 Data retention mode
of the power supply lines is recommended.
- Valid for ambient operating temperature: T A = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted).
- If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
illustrates how a BOK check routine could be structured. For more information on Battery Storage Life refer to the Application Note AN1012. Figure 8. Checking the BOK flag status
3 Clock operations
3.1 Reading the clock
Updates to the TIMEKEEPER® registers (see Table 5) should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register 7FF8h. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'
3.2 Setting the clock
Bit D7 of the Control Register 7FF8h is the WRITE Bit. Setting the WRITE Bit to a '1,' like the READ Bit, halts updates to the TIMEKEEPER ® registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (seeTable 5). Resetting the WRITE Bit to a '0' then transfers the values of all time registers 7FF9h-7FFFh to the actual TIMEKEEPER counters and allows normal operation to resume. The FT Bit and the bits marked as '0' in Table 5 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. After the WRITE Bit is reset, the next clock update will occur within one second. See the Application Note AN923, “TIMEKEEPER ® Rolling Into the 21st Century” for information on Century Rollover.
3.3 Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T35AV is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T35AV oscillator starts within 1 second.
Table 5. Register map (dependent upon the initial value set).
3.4 Calibrating the clock
The oscillation rate of any crystal changes with temperature (see Figure 9 on page 16). counts speeds the clock up, subtracting counts slows the clock down. D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.
binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration Byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or – 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T35AV may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit in the Day Register is set to a '1,' and D7 of the Seconds Register is a '0' (Oscillator Running), DQ0 will toggle at 512 Hz during a READ of the Seconds Register. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (WR001010) to be loaded into the Calibration Byte for correction. Note: Setting or changing the Calibration Byte does not affect the Frequency Test output frequency. The FT Bit MUST be reset to '0' for normal clock operations to resume. The FT Bit is automatically Reset on power-down. For more information on calibration, see Application Note AN934, “TIMEKEEPER Calibration.”
3.5 Century bit
Bit D5 and D4 of Clock Register 7FFCh contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Note: The WRITE Bit must be set in order to write to the CENTURY Bit.
3.6 V CC noise and negative going transients
Figure 11) is recommended in order to provide the needed filtering. Figure 11. Supply voltage protection
4 Maximum rating
Program and other relevant quality documents. Table 6. Absolute maximum ratings Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
- For DIP package: Soldering temperature not to exc eed 260°C for 10 seconds (total thermal budget not to
exceed 150°C for longer than 30 seconds).
- For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal
budget not to exceed 245°C for greater than 30 seconds).
5 DC and AC parameters
the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 12. AC measurement load circuit Table 8. Capacitance
- Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
Table 9. DC characteristics Figure 13. Power down/up mode AC waveforms
- Valid for ambient operating temperature: T A = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted).
- Negative spikes of –1V allowed for up to 10ns once per cycle.
Table 10. Power down/up AC characteristics Table 11. Power down/up trip points DC characteristics
- V PFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after
- V PFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
- All voltages referenced to V SS.
- CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top t DR = 7 years (typ).
6 Package mechanical data
conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 14. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, package outline Note: Drawing is not to scale. Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT™, pack. mech. data
Figure 15. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline Note: Drawing is not to scale. Table 13. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, pack. mech. data
Figure 16. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline Note: Drawing is not to scale. Table 14. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, pack. mech. data
Figure 17. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, pack. outline Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, pack. mech. data
7 Part numbering
Table 16. Ordering information scheme drain the lithium button-cell battery. ST sales office nearest you. Table 17. SNAPHAT battery table
- The SOIC package (SOH28) requires the SNAPHAT ® battery package which is ordered separately under
the part number “M4TXX-BR12SHx” in plastic tubes (see Table 17).
8 Revision history
Table 18. Document revision history updated Table 16, 17; removed M48T35AY and all references.