M48T201Y_09 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 37
Technical content
Datasheet sections
- 1 Description
- 2 Operation
- 2.1 Address decoding
- 2.2 Read mode
- 2.3 Write mode
- 2.4 Data retention mode
- 3 Clock operation
- 3.1 TIMEKEEPER ® registers
- 3.2 Reading the clock
- 3.3 Setting the clock
- 3.4 Stopping and starting the oscillator
- 3.5 Setting the alarm clock
- 3.6 Watchdog timer
- 3.7 Square wave output
- 3.8 Power-on reset
- 3.9 Reset inputs (RSTIN1
- 3.10 Calibrating the clock
- 3.11 Battery low warning
- 3.12 Initial power-on defaults
- 4 Maximum ratings
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Part numbering
- 8 Environmental information
Features
■ Converts low power SRAM into NVRAMs ■ Year 2000 compliant ■ Battery low flag ■ Integrated real time clock, power-fail control circuit, battery and crystal ■ Watchdog timer ■ Choice of write protect voltages PFD = power-fail deselect voltage): –M 4 8 T 2 0 1 Y : VCC = 4.5 to 5.5 V 4.1V ≤ VPFD ≤ 4.5 V –M 4 8 T 2 0 1 V : VCC = 3.0 to 3.6 V 2.7 V ≤ VPFD ≤ 3.0 V ■ Microprocessor power-on reset (valid even during battery backup mode) ■ Programmable alarm output active in the battery backed-up mode ■ Packaging includes a 44-lead SOIC and SNAPHAT ® top (to be ordered separately) ■ SOIC package provides direct connection for a SNAPHAT ® top which contains the battery and crystal ■ RoHS compliant – Lead-free second level interconnect SOH44 (MH) 44-pin SOIC SNAPHAT® (SH) crystal/battery
M48T201Y, M48T201V Contents
Table 15. SOH44 – 44-lead plastic small outline, SNAPHAT
1 Description
package after the completion of the surface mount process. (e.g., SNAPHAT) part number is “M4Txx-BR12SH” (see Table 19 on page 34). lithium button-cell battery. Figure 1. Logic diagram
Table 1. Signal names
Figure 2. SOIC connections
Figure 3. Hardware hookup
- If the second chip enable pin (E2) is unused, it should be tied to VOUT.
Operation M48T201Y, M48T201V
2 Operation
Automatic backup and write protection for an external SRAM is provided through VOUT, ECON, and GCON pins. (Users are urged to insure that voltage specifications, for both the supervisor chip and external SRAM chosen, are similar.) The SNAPHAT® containing the lithium energy source is used to retain the RTC and RAM data in the absence of VCC power through the VOUT pin. The chip enable output to RAM (ECON) and the output enable output to RAM (GCON) are controlled during power transients to prevent data corruption. The date is automatically adjusted for months with less than 31 days and corrects for leap years (valid until 2100). The internal watchdog timer provides programmable alarm windows. The nine clock bytes (7FFFFh-7FFF9h and 7FFF1h) are not the actual clock counters, they are memory locations consisting of BiPORT™ READ/WRITE memory cells within the static RAM array. Clock circuitry updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. Byte 7FFF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. Byte 7FFF7h contains the watchdog timer setting. The watchdog timer can generate either a reset or an interrupt, depending on the state of the watchdog steering bit (WDS). Bytes 7FFF6h-7FFF2h include bits that, when programmed, provide for clock alarm functionality. Alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. Byte 7FFF1h contains century information. Byte 7FFF0h contains additional flag information pertaining to the watchdog timer, the alarm condition, the battery status and square wave output operation. 4 bits are included within this register (RS0-RS3) that are used to program the square wave output frequency (see Table 7 on page 21). The M48T201Y/V also has its own power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When V CC is out of tolerance, the circuit write protects the TIMEKEEPER® register data and external SRAM, providing data security in the midst of unpredictable system operation. As VCC falls below the battery backup switchover voltage (VSO), the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored.
2.1 Address decoding
The M48T201Y/V accommodates 19 address lines (A0-A18) which allow direct connection of up to 512 K bytes of static RAM. Regardless of SRAM density used, timekeeping, watchdog, alarm, century, flag, and control registers are located in the upper RAM locations. All TIMEKEEPER registers reside in the upper RAM locations without conflict by inhibiting the G CON (output enable RAM) signal during clock access. The RAM's physical locations are transparent to the user and the memory map looks continuous from the first clock address to the upper most attached RAM addresses.
Table 2. Operating modes
2.2 Read mode
® registers or external SRAM locations is to be accessed. signal will be passed to the GCON pin, with the specified delay times of tAOEL or tOERL. Figure 4. G CON timing when switching between RTC and external SRAM
- See Table 14 on page 30 for details.
Figure 5. Read cycle timing: RTC and external RAM control signals
Table 3. Read mode AC characteristics
2.3 Write mode
W will disable the outputs tWLQZ after W falls. the range of TIMEKEEPER registers, an external SRAM location is selected.
Figure 6. Write cycle timing: RTC and external RAM control signals
Table 4. Write mode AC characteristics
2.4 Data retention mode
SNAPHAT® battery and the clock registers are maintained from the attached battery supply.
- If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Operation M48T201Y, M48T201V Note: Most low power SRAMs on the market today can be used with the M48T201Y/V TIMEKEEPER® SUPERVISOR. There are, however some criteria which should be used in making the final choice of an SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M48T201Y/V and SRAMs to be “Don't care” once V CC falls below VPFD (min). The SRAM should also guarantee data retention down to VCC = 2.0 V. The chip enable access time must be sufficient to meet the system needs with the chip enable (and output enable) output propagation delays included.
M48T201Y, M48T201V Clock operation
3 Clock operation
3.1 TIMEKEEPER ® registers
The M48T201Y/V offers 16 internal registers which contain TIMEKEEPER®, alarm, watchdog, flag, and control data (see T a b l e5 o n p a g e1 8). These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT™ TIME KEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. TIMEKEEPER and alarm registers store data in BCD. control, watchdog and flags (bits D0 to D3) registers store data in binary format.
3.2 Reading the clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. The BiPORT TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the control register (7FFF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs approximately 1 second after the READ bit is reset to a '0.'
3.3 Setting the clock
Bit D7 of the control register (7FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 18). Resetting the WRITE bit to a '0' then transfers the values of all time registers (7FFFFh- 7FFF9h, 7FFF1h) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur approximately one second later. Note: Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset to '0.'
3.4 Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is located at bit D7 within the seconds register (7FFF9h). Setting it to a '1' stops the oscillator. When reset to a '0,' the M48T201Y/V oscillator starts within one second.
bit (FT) or the STOP bit (ST). Table 5. TIMEKEEPER ® register map
3.5 Setting the alarm clock
every month, day of month, hour, minute, or second. alert the user of an incorrect alarm setting. Note: User must transition address (or toggle chip enable) to see flag bit change. alarm was generated while the M48T201Y/V was in the deselect mode during power-up. Figure 8 on page 20 illustrates the backup mode alarm timing. Figure 7. Alarm interrupt reset waveforms Table 6. Alarm repeat modes
Figure 8. Backup mode alarm waveforms
3.6 Watchdog timer
00001110 in the watchdog register = 3*1 or 3 seconds). Note: Accuracy of timer is withi n ± the selected resolution. the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the flag register (address 7FFF0h).
- a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI)
- the microprocessor can perform a WRITE of the watchdog register.
watchdog will be reset on each transition (edge) seen by the WDI pin.
written into the watchdog register, effectively restarting the countdown cycle. a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT pin. of the flags register will reset the watchdog flag (bit D7; register 7FFF0h). frequency test function is denied. Note: The user must transition the address (or toggle chip enable) to see the flag bit change.
3.7 Square wave output
the SQW pin. RS3-RS0 bits located in 7FFF0h establish the square wave output frequency. wave enable bit (SQWE) located in register 7FFF6h. Table 7. Square wave output frequency
0000 H i - Z -
11008 H z
11014 H z
11102 H z
11111 H z
3.8 Power-on reset
to VCC should be chosen to control rise time.
3.9 Reset inputs (RSTIN1 & RSTIN2)
duration and function of these resets is identical to a reset generated by a power cycle. pulled up to VCC through a 100 KΩ resistor. Figure 9. RSTIN1 and RSTIN2 timing waveforms Table 8. Reset AC characteristics
3.10 Calibrating the clock
employed, accuracy improves to better than +1/–2 ppm at 25°C.
- C L = 5 pF (see Figure 13 on page 28).
M48T201Y, M48T201V Clock operation The oscillation rate of crystals changes with temperature (see Figure 10 on page 24). The M48T201Y/V design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 24. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the control register 7FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration (see Figure 11 on page 24). Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or – 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T201Y/V may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in the STMicroelectronics application note AN934, “TIMEKEEPER ® calibration.” This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ /FT pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of 7FFF9h) is '0,' the frequency test bit (FT, D6 of 7FFFCh) is '1,' the alarm flag enable bit (AFE, D7 of 7FFF6h) is '0,' and the watchdog steering bit (WDS, D7 of 7FFF7h) is '1' or the watchdog register (7FFF7h=0) is reset. Note: A 4-second settling time must be allowed before reading the 512 Hz output. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (WR001010) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test output frequency. The IRQ /FT pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10 kΩ resistor is recommended in order to control the rise time. The FT bit is cleared on power-down.
Figure 10. Crystal accuracy across temperature Figure 11. Calibration waveform
3.11 Battery low warning
the next scheduled 24-hour interval. should be considered suspect and verified as correct. A fresh battery should be installed.
while VCC is applied to the device. Note: This will cause the clock to lose time durin g the interval the battery/crystal is removed. The M48T201Y/V only monitors the battery when a nominal VCC is applied to the device. power-up via a checksum or other technique.
3.12 Initial power-on defaults
WDS; BMB0-BMB4; RB0-RB1; AFE; ABE; SQWE; W; R; FT (see Table 9). Table 9. Default values
- WDS, BMB0-BMB4, RB0, RB1.
- State of other control bits undefined.
- State of other control bits remains unchanged.
- Assuming these bits set to '1' prior to power-down.
3.13 V CC noise and negative going transients
Figure 12) is recommended in order to provide the needed filtering. CC to VSS (cathode connected to VCC, anode to VSS). recommended for surface mount. Figure 12. Supply voltage protection
4 Maximum ratings
Program and other relevant quality documents. Table 10. Absolute maximum ratings Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
- For SOH44 package, standard (SnPb) lead finish: re flow at peak temperature of 225°C (the time above
220°C must not exceed 20 seconds).
- For SOH44 package, lead-free (Pb-fr ee) lead finish: Reflow at peak temperature of 260°C (the time above
255°C must not exceed 30 seconds).
5 DC and AC parameters
Table 11. DC and AC measurement conditions Note: Output High Z is defined as the point where data is no longer driven. Figure 13. AC testing load circuit Note: Excluding open-drain output pin; 50 pF for M48T201V. Table 12. Capacitance
- Effective capacitance m easured with power supply at 5 V; sampled only, not 100% tested.
Table 13. DC characteristics
- RSTIN1 and RSTIN2 internally pulled-up to VCC through 100 KΩ resistor. WDI internally pulled-down to VSS through
- For IRQ /FT & RST pins (open drain).
- Conditioned outputs (E CON - GCON) can only sustain CMOS leakage currents in the battery backup mode. Higher leakage
currents will reduce battery life.
- External SRAM must match TIMEKEEPER ® supervisor chip VCC specification.
Figure 14. Power down/up mode AC waveforms Table 14. Power down/up mode AC characteristic
- V PFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
- V PFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
6 Package mechanical data
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 15. SOH44 – 44-lead plastic small outline, SNAPHAT ®, package outline Note: Drawing is not to scale. Table 15. SOH44 – 44-lead plastic small outline, SNAPHAT ®, pack. mech. data
Figure 16. SH – 4-pin SNAPHAT ® housing for 48 mAh battery & crystal, package Note: Drawing is not to scale. Table 16. SH – 4-pin SNAPHAT ® housing for 48 mAh battery & crystal, pack. mech.
Figure 17. SH – 4-pin SNAPHAT ® housing for 120 mAh battery & crystal, pack. outline Note: Drawing is not to scale. Table 17. SH – 4-pin SNAPHAT ® housing for 120 mAh battery & crystal, pack. mech.
7 Part numbering
Table 18. Ordering information scheme drain the lithium button-cell battery. of this device, please contact the ST sales office nearest to you. Table 19. SNAPHAT ® battery table
- The SOIC package (SOH44) requires the battery package (SNAPHAT ®) which is ordered separately
under the part number “M4Txx-BR12SH” in plastic tube or “M4Txx-BR12SHTR” in tape & reel form.
8 Environmental information
Figure 18. Recycling symbols button cell battery fully encapsulated in the final product. and local/national disposal and recycling regulations. compliance statements and waste recycling. Go to www.st.com/rtc, then select "Lithium Battery Recycling" from "Related Topics".
9 Revision history
Table 20. Document revision history 22-Apr-2008 6 Updated shipping method in Table 18. added Section 8: Environmental information.