M48T08_10 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 31
Technical content
Datasheet sections
- 1 Description
- 2 Operation modes
- 2.1 READ mode
- 2.2 WRITE mode
- 2.3 Data retention mode
- 2.4 Power-fail interrupt pin
- 3 Clock operations
- 3.1 Reading the clock
- 3.2 Setting the clock
- 3.3 Stopping and starting the oscillator
- 3.4 Calibrating the clock
- 4 Maximum ratings
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Part numbering
- 8 Environmental information
- 9 Revision history
Features
■ Integrated ultra low power SRAM, real-time clock, power-fail control circuit, and battery ■ BYTEWIDE™ RAM-like clock access ■ BCD coded year, month, day, date, hours, minutes, and seconds ■ Typical clock accuracy of ±1 minute a month, at 25 °C ■ Automatic power-fail chip deselect and write protection ■ Write protect VPFD = Power-fail deselect voltage): –M 4 8 T 0 8 : VCC = 4.75 to 5.5 V 4.5 V ≤ VPFD ≤ 4.75 V – M48T18/T08Y: V CC = 4.5 to 5.5 V 4.2 V ≤ VPFD ≤ 4.5 V ■ Software controlled clock calibration for high accuracy applications ■ Self-contained battery and crystal in the CAPHAT ™ DIP package ■ Packaging includes a 28-lead SOIC and SNAPHAT ® top (to be ordered separately) ■ SOIC package provides direct connection for a snaphat top which contains the battery and crystal ■ Pin and function compatible with DS1643 and JEDEC standard 8 K x 8 SRAMs ■ RoHS compliant – Lead-free second level interconnect PCDIP28 (PC) battery/crystal CAPHAT™ SNAPHAT® (SH) battery/crystal SOH28 (MH)
Table 13. SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT
1 Description
on the number of WRITEs that can be performed. and a long-life lithium button cell in a single package. ® housing is keyed to prevent reverse insertion. part number is “M4T28-BR12SH” or “M4T32-BR12SH”. Figure 1. Logic diagram
Figure 4. Block diagram
2 Operation modes
BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. to the clock information and also stores the clock calibration setting. location in the static memory array. maintains data and clock operation until valid power returns. Table 2. Operating modes Note: X = V IH or VIL ; VSO = Battery backup switchover voltage.
- See Table 11 on page 22 for details.
2.1 READ mode
Figure 5. READ mode AC waveforms Note: WRITE enable (W ) = high.
Table 3. READ mode AC characteristics
2.2 WRITE mode
E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2. and a high on E2, a low on W will disable the outputs tWLQZ after W falls.
Table 4. WRITE mode AC characteristics
M48T08, M48T08Y, M48T18 Operation modes Doc ID 2411 Rev 10 13/31
2.3 Data retention mode
With valid VCC applied, the M48T08/18/08Y operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as “Don't care.” Note: A power failure during a WRITE cycle may corr upt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T08/18/08Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T08/18/08Y for an accumulated period of at least 10 years when VCC is less than VSO. Note: Requires use of M4T32-BR12SH SNAPHAT ® top when using the SOH28 package. As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E1 should be kept high or E2 low as VCC rises past VPFD (min) to prevent inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume trec after VCC exceeds VPFD (max). For more information on battery storage life refer to the application note AN1012.
2.4 Power-fail interrupt pin
The M48T08/18/08Y continuously monitors VCC. When VCC falls to the power-fail detect trip point, an interrupt is immediately generated. An internal clock provides a delay of between 10 µs and 40 µs before automatically deselecting the M48T08/18/08Y . The INT pin is an open drain output and requires an external pull-up resistor, even if the interrupt output function is not being used.
Clock operations M48T08, M48T08Y, M48T18 14/31 Doc ID 2411 Rev 10
3 Clock operations
3.1 Reading the clock
Updates to the TIMEKEEPER® registers should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, the seventh bit in the control register. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'
3.2 Setting the clock
The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a '1,' like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (on Table 5). Resetting the WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. The FT bit and the bits marked as '0' in Table 5 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. See the application note AN923, “TIMEKEEPER ® rolling Into the 21st century” for information on century rollover.
3.3 Stopping and starting the oscillator
oscillator starts within one second.
3.4 Calibrating the clock
Table 5. Register map
Clock operations M48T08, M48T08Y, M48T18 16/31 Doc ID 2411 Rev 10 M48T08/18/08Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 9 on page 17. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration byte occupies the five lower order bits in the control register. This byte can be set to represent any value between 0 and 31 in binary form. The sixth bit is the sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T08/18/08Y may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of standard test equipment. When the frequency test (FT) bit, the seventh-most significant bit in the day register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB (DQ0) of the seconds register will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (WR001010) to be loaded into the calibration byte for correction. Note: Setting or changing the calibration byte does not affect the frequency test output frequency. The device must be selected and addresses must be stable at address 1FF9h when reading the 512 Hz on DQ0. The LSB of the seconds register is monitored by holding the M48T08/18/08Y in an extended READ of the seconds register, but without having the READ bit set. The FT bit MUST be reset to '0' for normal clock operations to resume. For more information on calibration, see the application note AN934, “TIMEKEEPER calibration.”
3.5 V CC noise and negative going transients
Figure 10) is recommended in order to provide the needed filtering. Figure 10. Supply voltage protection
4 Maximum ratings
extended periods may affect device reliability. Table 6. Absolute maximum ratings
- For DIP package, soldering temperatur e of the IC leads is to not exceed 260 °C for 10 seconds. In order to
not exceed +85 °C. Furthermore, the devices shall not be exposed to IR reflow.
- For DIP packaged devices, ultrasound vi brations should not be used for post-solder cleaning to avoid
- For SO package, lead-free (Pb-free ) lead finish: reflow at peak temperature of 260 °C (the time above
255 °C must not exceed 30 seconds).
5 DC and AC parameters
the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 11. AC testing load circuit Table 8. Capacitance
- Effective capacitance m easured with power supply at 5 V; sampled only, not 100% tested.
Table 9. DC characteristics Figure 12. Power down/up mode AC waveforms until after the system clock is running.
- Measured with control bits set as follows: R = '1'; W, ST, FT = '0.'
- The INT pin is open drain.
Table 10. Power down/up AC characteristics Table 11. Power down/up trip points DC characteristics
- V PFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200 µs after VCC passes VPFD (min).
- V PFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
- All voltages referenced to V SS.
- At 55 °C, V CC = 0 V; tDR = 8.5 years (typ) at 70 °C. Requires use of M4T32-BR12SH SNAPHAT® top when
6 Package mechanical data
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT ™ , package outline Note: Drawing is not to scale. Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT ™ , package mech. data
Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT®, package Note: Drawing is not to scale. Table 13. SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT®, package mech.
Figure 15. SH – 4-pin SNAPHAT ® housing for 48 mAh battery & crystal, package Note: Drawing is not to scale. Table 14. SH – 4-pin SNAPHAT ® housing for 48 mAh battery & crystal, package mech.
Figure 16. SH – 4-pin SNAPHAT ® housing for 120 mAh battery & crystal, package Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT ® housing for 120 mAh battery & crystal, package
7 Part numbering
Table 16. Ordering information scheme will drain the lithium button-cell battery. ST sales office nearest you.
- The M48T08/18 part is offered with the PCDIP28 (e.g., CAPHAT™) package only.
- The SOIC package (SOH28) requires the SNAPHAT ® battery/crystal package which is ordered separately
Table 17). The M48T08Y part is offered in the SOH28 (SNAPHAT) package only.
Table 17. SNAPHAT ® battery table
8 Environmental information
Figure 17. Recycling symbols button cell battery fully encapsulated in the final product. and local/national disposal and recycling regulations. compliance statements and waste recycling. Go to www.st.com/rtc, then select "Lithium Battery Recycling" from "Related Topics".
9 Revision history
Table 18. Document revision history temp./voltage info. to tables (Table 8, 9, 3, 4, 10, 11). cover page and Section 6: Package mechanical data. Section 8: Environmental information; minor formatting changes. 21-Jun-2010 10 Updated Section 4, Table 12; reformatted document.