M48T128Y_10 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 23
Technical content
Datasheet sections
- 1 Description
- 2 Operation modes
- 2.1 READ mode
- 2.2 WRITE mode
- 2.3 Data retention mode
- 3 Clock operations
- 3.1 Reading the clock
- 3.2 Setting the clock
- 3.3 Stopping and starting the oscillator
- 3.4 Calibrating the clock
- 4 Maximum ratings
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Environmental information
- 8 Part numbering
- 9 Revision history
Features
■ Integrated, ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal ■ BCD coded year, month, day, date, hours, minutes, and seconds ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltages PFD = power-fail deselect voltage): –M 4 8 T 1 2 8 Y : VCC = 4.5 to 5.5 V 4.1 V ≤ VPFD ≤ 4.5 V –M 4 8 T 1 2 8 V : VCC = 3.0 to 3.6 V 2.7 V ≤ VPFD ≤ 3.0 V (contact the ST sales office for availability) ■ Conventional SRAM operation; unlimited WRITE cycles ■ Software-controlled clock calibration for high accuracy applications ■ 10 years of data retention and clock operation in the absence of power ■ Self-contained battery and crystal in the DIP package ■ Pin and function compatible with JEDEC standard 128 K x 8 SRAMs ■ RoHS compliant – Lead-free second level interconnect PMDIP32 module (PM)
1 Description
Figure 1. Logic diagram Table 1. Signal names
2 Operation modes
operation until valid power is restored. Table 2. Operating modes Note: X = V IH or VIL; VSO = battery backup switchover voltage.
- See Table 11 on page 18 for details.
2.1 READ mode
the 131,072 bytes of data is to be accessed. data hold time) but will go indeterminate until the next address access. Figure 4. READ mode AC waveforms Table 3. READ mode AC characteristics
2.2 WRITE mode
are low state after the address inputs are stable. Figure 5. WRITE enable controlled, WRITE AC waveform Figure 6. Chip enable controlled, WRITE AC waveforms
Table 4. WRITE mode AC characteristics
2.3 Data retention mode
decoupling of the power supply lines is recommended. switched to external VCC. Deselect continues for tREC after VCC reaches VPFD (max).
- If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
M48T128Y, M48T128V Clock operations Doc ID 5746 Rev 6 11/23
3 Clock operations
3.1 Reading the clock
Updates to the TIMEKEEPER® registers should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the control register (1FFF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.'
3.2 Setting the clock
Bit D7 of the control register (1FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 12). Resetting the WRITE bit to a '0' then transfers the values of all time registers 1FFFFh- 1FFF9h to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur one second later.
3.3 Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is located at bit D7 within 1FFF9h. Setting it to a '1' stops the oscillator. The M48T128Y/V is shipped from STMicroelectronics with the STOP bit set to a '1.' When reset to a '0,' the M48T128Y/V oscillator starts after one second.
Table 5. Register map
3.4 Calibrating the clock
the oscillator divider circuit at the divide by 128 stage, as shown in Figure 8 on page 13. which corresponds to a total range of +5.5 or –2.75 minutes per month.
3.5 V CC noise and negative going transients
Figure 9) is recommended in order to provide the needed filtering. Figure 9. Supply voltage protection
4 Maximum ratings
extended periods may affect device reliability. Table 6. Absolute maximum ratings
- Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. In order to protect the lithium
battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 °C. Furthermore, the devices shall not be exposed to IR reflow.
- For DIP packaged devices, ul trasonic vibrations should not be used for post-solder cleaning to avoid
5 DC and AC parameters
the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 10. AC testing load circuit Table 8. Capacitance
- Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.
Table 9. DC characteristics
Figure 11. Power down/up mode AC waveforms Table 10. Power down/up AC characteristics Table 11. Power down/up trip points DC characteristics
- V PFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
- V PFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
- All voltages referenced to V SS.
6 Package mechanical data
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 1. PMDIP32 – 32-pin plastic module DIP, package outline Note: Drawing is not to scale. Table 12. PMDIP32 – 32-pin plastic module DIP, package mechanical data
7 Environmental information
Figure 12. Recycling symbols button cell battery fully encapsulated in the final product. and local/national disposal and recycling regulations. compliance statements and waste recycling. Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics".
8 Part numbering
Table 13. Ordering information scheme ST sales office nearest you.
- Contact local ST sales office fo r availability of 3.3 V version.
9 Revision history
Table 14. Document revision history