M45PE40 STMICROELECTRONICS | Alldatasheet
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4 Mbit, Low Voltage, Page-Erasable Serial Flash Memory
Figure 1. Packages
Serial Data Output (Q).This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D).This input signal is used to transfer data serially into the device. It receives in- structions, addresses, and the data to be pro- grammed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C).This input signal provides the timing of the serial interface. Instructions, address- es, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select (S ).When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving Chip Select (S ) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. Reset (Reset).The Reset (Reset) input provides a hardware reset for the memory. In this mode, the outputs are high impedance. When Reset (Reset ) is driven High, the memory is in the normal operating mode. When Reset (Re- set) is driven Low, the memory will enter the Reset mode, provided that no internal operation is cur- rently in progress. Driving Reset (Reset) Low while an internal operation is in progress has no effect on that internal operation (a write cycle, program cycle, or erase cycle). Write Protect (W ).This input signal puts the de- vice in the Hardware Protected mode, when Write Protect (W) is connected to VSS , causing the first 256 pages of memory to become read-only by pro- tecting them from write, program and erase oper- ations. When Write Protect (W ) is connected to VCC , the first 256 pages of memory behave like the other pages of memory.
Sharing the Overhead of Modifying Data To write or program one (or more) data bytes, two instructions are required: Write Enable (WREN), which is one byte, and a Page Write (PW) or Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal cy- cle (of duration t PW or tPP ). To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to 256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at a time, pro- vided that they lie in consecutive addresses on the same page of memory. An Easy Way to Modify Data The Page Write (PW) instruction provides a con- venient way of modifying data (up to 256 contigu- ous bytes at a time), and simply requires the start address, and the new data in the instruction se- quence. The Page Write (PW) instruction is entered by driving Chip Select (S ) Low, and then transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte, and then driving Chip Select (S ) High. While Chip Select (S) is being held Low, the data bytes are written to the data buffer, starting at the address given in the third ad- dress byte (A7-A0). When Chip Select (S) is driven High, the Write cycle starts. The remaining, un- changed, bytes of the data buffer are automatically loaded with the values of the corresponding bytes of the addressed memory page. The addressed memory page then automatically put into an Erase cycle. Finally, the addressed memory page is pro- grammed with the contents of the data buffer. All of this buffer management is handled internally, and is transparent to the user. The user is given the facility of being able to alter the contents of the memory on a byte-by-byte basis. For optimized timings, it is recommended to use the Page Write (PW) instruction to write all con- secutive targeted Bytes in a single sequence ver- sus using several Page Write (PW) sequences with each containing only a few Bytes (see Page Write (PW) and AC Characteristics (33MHz oper- ation)). A Fast Way to Modify Data The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. This might be: – when the designer is programming the device for the first time – when the designer knows that the page has already been erased by an earlier Page Erase (PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available – when the designer knows that the only changes involve resetting bits to 0 that are still set to 1. When this method is possible, it has the additional advantage of minimising the number of unnecessary erase operations, and the extra stress incurred by each page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) se- quences with each containing only a few Bytes (see Page Program (PP) and AC Characteristics (33MHz operation)). Polling During a Write, Program or Erase Cycle A further improvement in the write, program or erase time can be achieved by not waiting for the worst case delay (t PW , tPP , tPE , or tSE ). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can mon- itor its value, polling it to establish when the previ- ous cycle is complete. Reset An internal Power On Reset circuit helps protect against inadvertent data writes. Addition protec- tion is provided by driving Reset (Reset ) Low dur- ing the Power-on process, and only driving it High when V CC has reached the correct voltage level, VCC (min). Active Power, Standby Power and Deep Power-Down Modes When Chip Select (S) is Low, the device is select- ed, and in the Active Power mode. When Chip Select (S) is High, the device is dese- lected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write). The device then goes in to the Standby Power mode. The device consumption drops to I CC1 . The Deep Power-down mode is entered when the specific instruction (the Deep Power-down (DP) in- struction) is executed. The device consumption drops further to I CC2 . The device remains in this
ic Signature (RES) instruction) is executed. cates the status of the internal Write Enable Latch. Table 2. Status Register Format set by the internal logic of the device). the device is not in active use.
■ 2048 pages (256 bytes each). Table 3. Memory Organization
Figure 6. Block Diagram
256 Byte
256 Bytes (Page Size)
and out of the device, most significant bit first. latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 4.. the instruction is rejected, and is not executed. driven Low is an exact multiple of eight. or Erase cycle continues unaffected. Table 4. Instruction Set
device in the second byte (13h). The instruction sequence is shown in Figure 9.. Table 5. Read Identification (RDID) Data-Out Sequence Figure 9. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
Program, Erase or Write cycle is in progress. bit before sending a new instruction to the device. tinuously, as shown in Figure 10.. cates the status of the internal Write Enable Latch. Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
The instruction sequence is shown in Figure 11.. The first byte addressed can be at any location. with a single Read Data Bytes (READ) instruction. sequence to be continued indefinitely. the cycle that is in progress. Figure 11. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence Note: Address bits A23 to A19 are Don’t Care.
The instruction sequence is shown in Figure 12.. The first byte addressed can be at any location. fects on the cycle that is in progress. Figure 12. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence Note: Address bits A23 to A19 are Don’t Care.
sets the Write Enable Latch (WEL). occurs during this write cycle. erase cycle even if only one byte is updated. for the entire duration of the sequence. The instruction sequence is shown in Figure 13.. on the other bytes of the same page. Characteristics (33MHz operation)). Write Enable Latch (WEL) bit is reset. that is Hardware Protected is not executed. Figure 13. Page Write (PW) Instruction Sequence
en Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14.. (see AC Characteristics (33MHz operation)). check the value of the Write In Progress (WIP) bit. that is Hardware Protected is not executed. Figure 14. Page Program (PP) Instruction Sequence
the device sets the Write Enable Latch (WEL). valid address for the Page Erase (PE) instruction. The instruction sequence is shown in Figure 15.. that is Hardware Protected is not executed. Figure 15. Page Erase (PE) Instruction Sequence Note: Address bits A23 to A19 are Don’t Care.
24 Bit Address
ed, the device sets the Write Enable Latch (WEL). Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16.. Figure 16. Sector Erase (SE) Instruction Sequence Note: Address bits A23 to A19 are Don’t Care.
Program and Erase instructions. tion. This releases the device from this mode. The instruction sequence is shown in Figure 17.. Figure 17. Deep Power-down (DP) Instruction Sequence
of the Deep Power-down mode. entire duration of the sequence. The instruction sequence is shown in Figure 18.. decode and execute instructions. fects on the cycle that is in progress. Figure 18. Release from Deep Power-down (RDP) Instruction Sequence
These values are specified in Table 6.. Power-up and Power-down phases. – The Write Enable Latch (WEL) bit is reset. Figure 19. Power-up Timing
Table 6. Power-Up Timing and VWI Threshold Note: 1. These parameters are characterized only, over the temperature range –40°C to +85°C. FFh). All usable Status Register bits are 0. Table 7. may cause permanent damage to the de- Table 7. Absolute Maximum Ratings
Table 8. Operating Conditions Table 9. AC Measurement Conditions Note: Output Hi-Z is defined as the point where data out is no longer driven. Figure 20. AC Measurement I/O Waveform Table 10. Capacitance Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 20 MHz.
Table 11. DC Characteristics
Table 12. AC Characteristics (25MHz operation)
- Value guaranteed by characterization, not 100% tested in production.
- When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all
Test conditions specified in Table 8. and Table 9.
Table 13. AC Characteristics (33MHz operation)
- Value guaranteed by characterization, not 100% tested in production.
- When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all
- Details of how to find the date of marking are given in Application Note, AN1995.
Test conditions specified in Table 8. and Table 9.
Figure 25. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Outline Note: Drawing is not to scale. Table 14. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm,
Figure 26. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, Package Outline Note: Drawing is not to scale. Table 15. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, Mechanical Data
Table 16. Ordering Information Scheme are also marked on the inner box label. 6 = Industrial temperature range, –40 to 85 °C.
REVISION HISTORY
Table 17. Document Revision History Document promoted to Mature Datasheet. Minor wording changes. removed and SO8 wide package added. Scheme . Ecopack® information added.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America