M45PE40 NUMONYX | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 46
Technical content
Datasheet sections
- 1 Description
- 2 Signal description
- 2.1 Serial Data Output (Q)
- 2.2 Serial Data Input (D)
- 2.3 Serial Clock (C)
- 2.4 Chip Select (S)
- 2.5 Reset (Reset)
- 2.6 Write Protect (W)
- 2.8 V SS ground
- 3 SPI modes
- 4 Operating features
- 4.1 Sharing the overhead of modifying data
- 4.2 An easy way to modify data
- 4.3 A fast way to modify data
- 4.4 Polling during a Write, Program or Erase cycle
- 4.5 Reset
- 4.6 Active Power, Standby Power and Deep Power-Down modes
- 4.7 Status Register
- 4.8 Protection modes
- 5 Memory organization
- 6 Instructions
- 6.1 Write Enable (WREN)
- 6.2 Write Disable (WRDI)
- 6.3 Read Identification (RDID)
- 6.4 Read Status Register (RDSR)
- 6.4.1 WIP bit
Features
■ SPI bus compatible serial interface ■ 50 MHz clock rate (maximum) ■ 2.7 V to 3.6 V single supply voltage ■ 4 Mbits of Page-Erasable Flash memory ■ Page size: 256 bytes: – Page Write in 11 ms (typical) – Page Program in 0.8 ms (typical) – Page Erase in 10 ms (typical) ■ Sector Erase (64 Kbytes) ■ Hardware Write protection of the bottom sector (64 Kbytes) ■ Electronic Signature – JEDEC standard two-byte signature (4013h) ■ Deep Power-down Mode 1µA (typical) ■ More than 100 000 Write cycles ■ More than 20 years’ data retention ■ Packages – ECOPACK® (RoHS compliant) VFQFPN8 (MP) 6 × 5 mm (MLP8) SO8W (MW) 208 mils width SO8N (MN) 150 mils width www.numonyx.com
Table 16. VFQFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 6 × 5 mm, Table 17. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package Table 18. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package
1 Description
cycle followed by a Page Program cycle. wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524288 bytes. at a time, using the Sector Erase instruction. packages. ECOPACK® packages are Lead-free and RoHS compliant. Figure 1. Logic diagram Table 1. Signal names
Figure 2. VFQFPN and SO connections
- There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
- See Section 11: Package mechanical for package dimensions, and how to identify pin-1.
Signal description M45PE40
2 Signal description
2.1 Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S )
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5 Reset (Reset )
The Reset (Reset) input provides a hardware reset for the memory. In this mode, the outputs are high impedance. When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset mode, provided that no internal operation is currently in progress. Driving Reset (Reset) Low while an internal operation is in progress has no effect on that internal operation (a write cycle, program cycle, or erase cycle).
2.6 Write Protect (W )
This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is connected to VSS, causing the first 256 pages of memory to become read-only by protecting them from write, program and erase operations. When Write Protect (W) is connected to VCC, the first 256 pages of memory behave like the other pages of memory.
M45PE40 Signal description
2.7 V CC supply voltage
VCC is the supply voltage.
2.8 V SS ground
VSS is the reference for the VCC supply voltage.
3 SPI modes
- CPOL=0, CPHA=0
- CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
- C remains at 0 for (CPOL=0, CPHA=0)
- C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. Bus master and memory devices on the SPI bus
- The Write Protect (W ) signal should be driven, High or Low as appropriate.
Figure 4. SPI modes supported
Operating features M45PE40
4 Operating features
4.1 Sharing the overhead of modifying data
To write or program one (or more) data bytes, two instructions are required: Write Enable (WREN), which is one byte, and a Page Write (PW) or Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal cycle (of duration t PW or tPP). To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to 256 bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at a time, provided that they lie in consecutive addresses on the same page of memory.
4.2 An easy way to modify data
The Page Write (PW) instruction provides a convenient way of modifying data (up to 256 contiguous bytes at a time), and simply requires the start address, and the new data in the instruction sequence. The Page Write (PW) instruction is entered by driving Chip Select (S ) Low, and then transmitting the instruction byte, three address bytes (A23-A0) and at least one data byte, and then driving Chip Select (S ) High. While Chip Select (S) is being held Low, the data bytes are written to the data buffer, starting at the address given in the third address byte (A7-A0). When Chip Select (S ) is driven High, the Write cycle starts. The remaining, unchanged, bytes of the data buffer are automatically loaded with the values of the corresponding bytes of the addressed memory page. The addressed memory page then automatically put into an Erase cycle. Finally, the addressed memory page is programmed with the contents of the data buffer. All of this buffer management is handled internally, and is transparent to the user. The user is given the facility of being able to alter the contents of the memory on a byte-by-byte basis. For optimized timings, it is recommended to use the Page Write (PW) instruction to write all consecutive targeted Bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few Bytes (see Page Write (PW) and AC characteristics (50 MHz operation)).
M45PE40 Operating features
4.3 A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. This might be:
- when the designer is programming the device for the first time
- when the designer knows that the page has already been erased by an earlier Page Erase (PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available
- when the designer knows that the only changes involve resetting bits to 0 that are still set to 1. When this method is possible, it has the additional advantage of minimizing the number of unnecessary erase operations, and the extra stress incurred by each page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Page Program (PP) and AC characteristics (50 MHz operation)).
4.4 Polling during a Write, Program or Erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for the worst case delay (tPW, tPP, tPE, or tSE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous cycle is complete.
4.5 Reset
An internal Power On Reset circuit helps protect against inadvertent data writes. Addition protection is provided by driving Reset (Reset ) Low during the Power-on process, and only driving it High when VCC has reached the correct voltage level, VCC(min).
4.6 Active Power, Standby Powe r and Deep Power-Down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write). The device then goes in to the Standby Power mode. The device consumption drops to I CC1. The Deep Power-down mode is entered when the specific instruction (the Deep Power- down (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down and Read Electronic Signature (RES) instruction) is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions.
Operating features M45PE40
4.7 Status Register
The Status Register contains two status bits that can be read by the Read Status Register (RDSR) instruction. See Section 6.4: Read Status Register (RDSR) for a detailed description of the Status Register bits.
4.8 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M45PE40 features the following data protection mechanisms:
- Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification.
- Program, Erase and Write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
- All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: –P o w e r - u p – Reset (RESET ) driven Low – Write Disable (WRDI) instruction completion – Page Write (PW) instruction completion – Page Program (PP) instruction completion – Page Erase (PE) instruction completion – Sector Erase (SE) instruction completion
- The Hardware Protected mode is entered when Write Protect (W) is driven Low, causing the first 256 pages of memory to become read-only. When Write Protect (W) is driven High, the first 256 pages of memory behave like the other pages of memory
- The Reset (Reset) signal can be driven Low to protect the contents of the memory during any critical time, not just during Power-up and Power-down.
- In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions while the device is not in active use.
5 Memory organization
- 2048 pages (256 bytes each).
- 524288 bytes (8 bits each)
- 8 sectors (64 Kbits, 65536 bytes each) Each page can be individually:
- programmed (bits are programmed from 1 to 0)
- erased (bits are erased from 0 to 1)
- written (bits are changed to either 0 or 1) The device is Page or Sector Erasable (bits are erased from 0 to 1).
Table 2. Memory organization
Figure 5. Block diagram
256 Byte
256 Bytes (Page Size)
6 Instructions
The instruction set is listed in Table 3. instruction, this might be followed by address bytes, or by data bytes, or by both or none. sequence is being shifted out. Table 3. Instruction set
6.1 Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 6) sets the Write Enable Latch (WEL) bit. Program (PP), Page Erase (PE), and Sector Erase (SE) instruction. instruction code, and then driving Chip Select (S) High. Figure 6. Write Enable (WREN) instruction sequence
6.2 Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 7) resets the Write Enable Latch (WEL) bit. instruction code, and then driving Chip Select (S) High.
- Power-up
- Write Disable (WRDI) instruction completion
- Page Write (PW) instruction completion
- Page Program (PP) instruction completion
- Page Erase (PE) instruction completion
- Sector Erase (SE) instruction completion
Figure 7. Write Disable (WRDI) instruction sequence
6.3 Read Identification (RDID)
and the memory capacity of the device in the second byte (13h). not decoded, and has no effect on the cycle that is in progress. the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 8. any time during data output. Figure 8. Read Identification (RDID) instruction sequence and data-out sequence Table 4. Read Identification (RDID) data-out sequence
6.4 Read Status Register (RDSR)
the Status Register continuously, as shown in Figure 9.
6.4.1 WIP bit
6.4.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. Latch is reset and no Write, Program or Erase instruction is accepted. Figure 9. Read Status Register (RDSR) instruction sequence and data-out Table 5. Status Register Format
- WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is
automatically set and reset by the internal logic of the device).
6.5 Read Data Bytes (READ)
R, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. to be continued indefinitely. any effects on the cycle that is in progress. Figure 10. Read Data Bytes (READ) instruction sequence and data-out sequence
- Address bits A23 to A19 are Don’t Care.
6.6 Read Data Bytes at Higher Speed (FAST_READ)
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). C, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 11. 000000h, allowing the read sequence to be continued indefinitely. Figure 11. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
- Address bits A23 to A19 are Don’t Care.
6.7 Page Write (PW)
The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Write (PW) instruction is entered by driving Chip Select (S ) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). The rest of the page remains unchanged if no power failure occurs during this write cycle. The Page Write (PW) instruction performs a page erase cycle even if only one byte is updated. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary wrap round, and are written from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 12. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be written correctly within the same page. If less than
256 Data bytes are sent to device, they are correctly written at the requested addresses
without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Write (PW) instruction to write all consecutive targeted Bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few Bytes (see AC characteristics (50 MHz operation)). Chip Select (S ) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Write (PW) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Write cycle (whose duration is tPW) is initiated. While the Page Write cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Write cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Write (PW) instruction applied to a page that is Hardware Protected is not executed. Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 12. Page Write (PW) instruction sequence
- Address bits A23 to A19 are Don’t Care
6.8 Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S ) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary wrap round, and are programmed from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 13. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see AC characteristics (50 MHz operation)). Chip Select (S ) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page that is Hardware Protected is not executed. Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 13. Page Program (PP) instruction sequence
- Address bits A23 to A19 are Don’t Care
6.9 Page Erase (PE)
Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. ) is driven High, the self-timed Page Erase cycle (whose duration is tPE) is initiated. cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Erase (PE) instruction applied to a page that is Hardware Protected is not executed. rejected without having any effects on the cycle that is in progress. Figure 14. Page Erase (PE) instruction sequence
- Address bits A23 to A19 are Don’t Care.
24 Bit Address
6.10 Sector Erase (SE)
can be accepted, a Write Enable (WREN) instruction must previously have been executed. must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. rejected without having any effects on the cycle that is in progress. Figure 15. Sector Erase (SE) instruction sequence
- Address bits A23 to A19 are Don’t Care.
6.11 Deep Power-down (DP)
device ignores all Write, Program and Erase instructions. Powers-up in the Standby Power mode. entire duration of the sequence. The instruction sequence is shown in Figure 16. to ICC2 and the Deep Power-down mode is entered. progress, is rejected without having any effects on the cycle that is in progress. Figure 16. Deep Power-down (DP) instruction sequence
6.12 Release from Deep Power-down (RDP)
takes the device out of the Deep Power-down mode. driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. Low, cause the instruction to be rejected, and not executed. device waits to be selected, so that it can receive, decode and execute instructions. cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Release from Deep Power-down (RDP) instruction sequence
M45PE40 Power-up and power-down
7 Power-up and power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value:
- VCC(min) at Power-up, and then for a further delay of tVSL
- VSS at Power-down A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program (PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write, Program or Erase instructions should be sent until the later of:
- tPUW after VCC passed the VWI threshold
- tVSL after VCC passed the VCC(min) level These values are specified in Table 6. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. As an extra protection, the Reset (Reset) signal can be driven Low for the whole duration of the Power-up and Power-down phases. At Power-up, the device is in the following state:
- The device is in the Standby Power mode (not the Deep Power-down mode).
- The Write Enable Latch (WEL) bit is reset.
- The Write In Progress (WIP) bit is reset. Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 100 nF). At Power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.)
Figure 18. Power-up timing Table 6. Power-Up timing and V WI threshold
- These parameters are char acterized only, over the temperature range –40°C to +85°C.
8 Initial delivery state
contains FFh). All usable Status Register bits are 0.
9 Maximum rating
Table 7. Absolute maximum ratings
- Compliant with JEDEC Std J-STD-020C (for sm all body, Sn-Pb or Pb assembly), the Numonyx
10 DC and AC parameters
match the measurement conditions when relying on the quoted parameters.
- Output Hi-Z is defined as the point where data out is no longer driven.
Figure 19. AC measurement I/O waveform Table 8. Operating conditions Table 9. AC measurement conditions Table 10. Capacitance (1)
- Sampled only, not 100% tested, at T A=25°C and a frequency of 20 MHz.
Table 11. DC characteristics
Table 12. AC characteristics (25 MHz operation)
- t CH + tCL must be greater than or equal to 1/ fC(max)
- Value guaranteed by characterizati on, not 100% tested in production.
0.03 V/ns
- When using PP and PW instructions to update consec utive Bytes, optimized timings are obtained with one
Table 13. AC characteristics (33 MHz operation)
33 MHz only available for products marked since week 40 of 2005(1)
- Details of how to find the date of marking are given in Application Note, AN1995.
- t CH + tCL must be greater than or equal to 1/ fC
- Value guaranteed by characterizati on, not 100% tested in production.
- When using PP and PW instructions to update consec utive Bytes, optimized timings are obtained with one
Table 14. AC characteristics (50 MHz operation) (1)
50 MHz preliminary data for T9HX technology(2)
- Delivery of parts in T9HX pr ocess to start from July 2007.
- t CH + tCL must be greater than or equal to 1/ fC
- Value guaranteed by characterization, not 100% tested in production.
- n = number of bytes to program. int(A) corresponds to the upper integer part of A. Examples: int(1/8) = 1, int(16/8) = 2,
Figure 23. Reset AC waveforms Table 15. Reset conditions
- Value guaranteed by characterizati on, not 100% tested in production.
Figure 24. VFQFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 6 × 5 mm,
Figure 25. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package
Figure 26. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline
12 Part numbering
“4”), please contact your nearest Numonyx Sales Office. soldering conditions are also marked on the inner box label. Table 19. Ordering information scheme
- Package available only in T9HX technology.
6 = Industrial temperature range, –40 to 85 °C.
Table 20. Document revision history 31-Mar-2004 3.0 Soldering temperature information clarified for RoHS compliant devices. Document promoted to Mature Datasheet. Minor wording changes. Notes 1 and 2 removed from Table 19: Ordering information scheme. SO16 package removed and SO8 wide package added. characteristics. Updated Table 19: Ordering information scheme. explanatory paragraph added. At Power-up The Write In Progress (WIP) bit is reset. IO max modified in Table 7: Absolute maximum ratings. MHz operation) and, Table 15: Reset conditions added. updated (see Section 11: Package mechanical). 10-Dec-2007 8 Applied Numonyx branding.