M4334

M4334 UTC | Alldatasheet

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UNISONIC TECHNOLOGIES CO., LTD M4334 CMOS IC w w w . u n i s o n i c . c o m . t w 1 of 9 Copyright © 2010 Unisonic Technologies Co., Ltd QW-R502-441A STEREO AUDIO D/A CONVERTER 24BITS,96KHZ SAMPLING „ DESCRIPTION The UTC M4334 is a complete low cost stereo audio digital to analog converter(DAC), its contains interpolation, 1-bit D/A conversion and analog output filtering. The M4334 is based on a 4th order Δ-Σ modulation, where the modulator output controls the reference voltage input to an ultra-liner analog low-pa ss filter. This architecture allows for infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The M4334 also contains digital de-em phasis function, operates from a single +5V power supply, for best performance, decoupling capacitors should be located as close to the device package as possible with the smallest capacitor closest, the M4334 requires minimal support circuitry. The M4334 is ideal for DVD players, set-top boxes, SVCD players and A/V receivers. „ FEATURES * Complete stereo DAC: Includes Output Analog Filter and DAC * Dynamic Range: 96dB * THD+N: -88dB * Multiple Sampling Frequencies: 16kHz to 96kHz * Low Clock Jitter Sensitivity * Single Power Supply: 5V * Filtered Line Level Outputs * On-Chip Digital De-emphasis * Normal or I2S Data Input Formats * 24Bits Conversion SOP-8 „ ORDERING INFORMATION Ordering Number Package Packing M4334G-S08-R SOP-8 Tape Reel

UNISONIC TECHNOLOGIES CO., LTD 2 of 9 www.unisonic.com.tw Q W - R 5 0 2 - 4 4 1 A „ PIN CONFIGURATIONS „ PIN DESCRIPTION PIN NO PIN NAME PIN TYPE PIN DESCRIPTION

1 SDATA I

Serial audio data input: two’s complement MSB-first serial data is input on this pin. The data is clocked into the M4334 via internal or external SCLK, and the channel is determined by LRCK.

2 DEM/SCLK I De-emphasis control and clock input for audio data: used for de-emphasis

filter control or external serial clock input.

3 LRCK I Sample rata clock input: determines which channel is currently being input

on the audio serial data input pin.

4 MCLK I System clock input: frequency must be 256x, 384x, or 512x the input

sample rate in BRM and either 128x or 192x the input sample rate in HRM.

5 AOUTR O Right-channel analog output

6 AGND I Ground pin

7 VA I Power supply pin for the internal control circuits

8 AOUTL O Left-channel analog output

UNISONIC TECHNOLOGIES CO., LTD 3 of 9 www.unisonic.com.tw Q W - R 5 0 2 - 4 4 1 A „ BLOCK DIAGRAM

UNISONIC TECHNOLOGIES CO., LTD 4 of 9 www.unisonic.com.tw Q W - R 5 0 2 - 4 4 1 A „ ABSOLUTE MAXIMUM RATING PARAMETER SYMBOL RATINGS UNIT DC Power Supply V A -0.3~6 V Digital Input Voltage V IND -0.3~ VA +0.4 V Input Current, Any Pin Except Supplies I IN ±10 mA Ambient Operating Temperature TA -55 ~ +125 °C Storage Temperature TSTG -65 ~ +150 °C Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. „ RECOMMENDED OPERATING CONDITIONS(Note1) PARAMETER SYMBOL RANGE UNIT DC Power Supply V A 4.75 ~ 5.5 V Note: 1. All voltage values are with respect to the network ground terminal unless otherwise noted. 2 . T h e VOUT tracks the VREF with additional voltage offset and load regulation. „ ELECTRICAL CHARACTERISTICS All specifications at 25°C,VA=+5V, full-scale output sine wave,997Hz; MCLK=12.288MHz; Fs for =48kHz, SCLK=3.072MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified; fS for HRM=96kHz, SCLK=6.144MHz, measurement bandwidth 10Hz to 40kHz, unless otherwise specified. RL=10KΩ, CL=10pF. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT POWER AND THERMAL Normal operation 15 19 mA Power supply current IA Power-down state 40 uA Normal operation 75 104 Power Dissipation PD Power-down state 0.2 mW Package Thermal Resistance θJA 110 °C /W Power Supply Rejection Ratio PSRR f=1kHz 79 dB DC ACCURACY Inter Channel Gain Mismatch 0.1 0.4 dB Gain Error ±5 % Gain Drift 100 ppm/°C ANALOG OUTPUT Full Scale Output Voltage 3.25 3.5 3.75 Vpp Quiescent Voltage V Q 2.2 VDC Max AC-Load Resistance RL 3 K Ω Max Load Capacitance CL 100 pF DIGITAL INPUT/OUTPUT High-Level Input Voltage VIH 2.0 V Low-Level Input Voltage VIL 0.8 V Input Leakage Current II(Leak) ±10 μA Input Capacitance CIN 8 pF

UNISONIC TECHNOLOGIES CO., LTD 5 of 9 www.unisonic.com.tw Q W - R 5 0 2 - 4 4 1 A „ ELECTRICAL CHARACTERISTICS (Cont.) Base-Rate Mode High-Rate Mode PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT Ambient Operating Temperature T OPR -40 85 -40 85 °C 16-bit , un-weighted 83 91 88 16-bit , a-weighted 86 94 86 94 18 to 24-bit, un-weighted 85 93 90 Dynamic Range 18 to 24-bit , a-weighted 88 96 88 96 dB 16-bit, 0dB -86 -70 -86 -80 16-bit, -20dB -71 -63 -68 -60 16-bit, -60dB -31 -23 -28 -20 18 to 24-bit, 0dB -88 -82 -88 -82 18 to 24-bit, -20dB -73 -65 -70 -62 Total Harmonic Distortion +Noise THD+N 18 to 24-bit, -60dB -33 -25 -30 -22 dB „ SWITCHING CHARCTERISTICS (TA=-40 to 85°C;VA=4.75V~5.5V; Input: Logic 0=0V, Logic 1=VA, CL=20pF) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Input Sample Rate f S 2 100 kHz MCLK Pulse Width High MCLK/LRCK=512 10 1000 ns MCLK Pulse Width Low MCLK/LRCK=512 10 1000 ns MCLK Pulse Width High MCLK/LRCK=384 or 192 21 1000 ns MCLK Pulse Width Low MCLK/LRCK=384 or 192 21 1000 ns MCLK Pulse Width High MCLK/LRCK=256 or 128 31 1000 ns MCLK Pulse Width Low MCLK/LRCK=256 or 128 31 1000 ns EXTERNAL SCLK MODE LRCK Duty Cycle 40 50 60 % SCLK Pulse Width High t SCLKH 20 ns SCLK Pulse Width Low t SCLKL 20 ns MCLK/LRCK=512,256 or 384 (128) Fs ns SCLK Period t SCLKW MCLK/LRCK=128 or 192 (64) Fs ns SCLK rising to LRCK edge delay t SLRD 20 ns SCLK rising to LRCK edge setup time t SLRS 20 ns SDATA valid to SCLK rising setup time t SDLRS 20 ns SCLK rising to SDATA hold time t SDH 20 ns INTERNAL SCLK MODE LRCK duty cycle 50 % SCLK Period t SCLKW SCLK ns SCLK rising to LRCK edge t SCLKR tsclkw 2 μs SDATA valid to SCLK rising setup time t SDLRS 1 10(512) Fs+ ns SCLK rising to SDATA hold time t SDH MCLK/LRCK=128 , 256 or 512 1 +15(512) Fs ns SCLK rising to SDATA hold time t SDH MCLK/LRCK=192 or 384 1 15(384) Fs+ ns

Figure 1. I2S Data Input Timing

UNISONIC TECHNOLOGIES CO., LTD 7 of 9 www.unisonic.com.tw Q W - R 5 0 2 - 4 4 1 A „ TYPICAL APPLICATION CIRCUIT

UNISONIC TECHNOLOGIES CO., LTD 8 of 9 www.unisonic.com.tw Q W - R 5 0 2 - 4 4 1 A „ APPLICATION CONSIDERATION The M4334 is a complete low cost stereo digital-to-analog output system contains digital interpolation, fourth-order delta-sigma digital-to-analog conversion, digital de-emphasis and analog low pass filter. The M4334 used the Δ-Σ modulation techniques is to avoid the limitations of resistive laser trimmed DAC architectures by using an inherently linear 1-bit DAC. The M4334 supports two modes of operation. The devices operate in Base Rate Mode (BRM) when MCLK/LRCK is 256, 384 or 512 and in High Rate Mode (HRM) when MCLK/LRCK is 128 or 192. HRM allows input sample rates up to 100 kHz. The M4334 also has the de-emphasis function, the de-emphasis filter is active when the DEM/SCLK pin is low for 5 consecutive falling edges of LRCK, but this function is available only in the internal SCLK mode. When the M4334 is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. After a sh- ort delay of approximately 1000 sample periods, each output begins to ramp towards its quiescent voltage, VQ. App- roximately 10,000 sample cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to VQ, effectively blocking the quiescent DC voltage. To prevent transients at power-down, the device must first enter its power-down state. This is accomplished by rem- oving MCLK or LRCK. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. A soft-start current sink is substituted in place of AOUTL and AOUTR which allows the DC-blo- cking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on. To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance.

audio sample rates and the required MCLK and LRCK frequencies. Table 1. Common Clock Frequencies external SCLK generation modes. also eliminates possible clock interference from an external SCLK. the DEM/SCLK pin for 2 consecutive frames of LRCK. and reliable and may be changed without notice.