Microcontroller

M430G2221IRSA16RG4.B

Texas Instruments

MIXED SIGNAL MICROCONTROLLER REVISED FEBRUARY 2013

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www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 MIXEDSIGNALMICROCONTROLLER 1FEATURES

Low Supply-VoltageRange: 1.8V to3.6V • 16-BitTimer_A With Two Capture/Compare Registers• Ultra-LowPower Consumption
UniversalSerialInterface(USI)SupportingSPI– ActiveMode: 220 µA at1 MHz, 2.2V and I2C (See Table1)– Standby Mode: 0.5µA
Brownout Detector– OffMode (RAM Retention):0.1µA
10-Bit200-kspsA/D ConverterWith Internal• FivePower-Saving Modes Reference,Sample-and-Hold,and Autoscan• Ultra-FastWake-Up From Standby Mode in (See Table1)Less Than 1 µs • SerialOnboard Programming,• 16-BitRISC Architecture,62.5-nsInstruction No ExternalProgramming VoltageNeeded,Cycle Time Programmable Code Protectionby Security
Basic Clock Module Configurations Fuse – InternalFrequenciesup to16 MHz With • On-Chip EmulationLogic With Spy-Bi-Wire One CalibratedFrequency Interface – InternalVery Low Power Low-Frequency • For FamilyMembers Details,See Table1 (LF)Oscillator • Availablein14-PinPlasticSmall-OutlineThin – 32-kHz Crystal Package (TSSOP) (PW),14-PinPlasticDual – ExternalDigitalClock Source InlinePackage (PDIP)(N),and 16-PinQFN Package (RSA)
For Complete Module Descriptions,See the MSP430x2xx FamilyUser’s Guide (SLAU144 )

DESCRIPTION

The Texas InstrumentsMSP430 familyofultra-low-powermicrocontrollersconsistsofseveraldevicesfeaturing differentsetsof peripheralstargetedforvariousapplications.The architecture,combined withfivelow-power modes, isoptimizedtoachieveextendedbatterylifeinportablemeasurement applications.The devicefeaturesa powerful16-bitRISC CPU, 16-bitregisters,and constantgeneratorsthatcontributetomaximum code efficiency. The digitallycontrolledoscillator(DCO) allowswake-up fromlow-powermodes toactivemode inlessthan1 µs. The MSP430G2x21/G2x31 seriesisan ultra-low-powermixed signalmicrocontrollerwitha built-in16-bittimer and tenI/Opins.The MSP430G2x31 familymembers have a 10-bitA/D converterand built-incommunication capabilityusingsynchronousprotocols(SPIorI2C).Forconfigurationdetails,see Table1. Typicalapplicationsincludelow-costsensorsystemsthatcaptureanalogsignals,convertthem todigitalvalues, and thenprocessthedatafordisplayorfortransmissiontoa hostsystem. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2010–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com Table1.AvailableOptions(1) Flash RAM ADC10 PackageDevice BSL EEM Timer_A USI Clock I/O(KB) (B) Channel Type (2) MSP430G2231IRSA16 16-QFN MSP430G2231IPW14 - 1 2 128 1x TA2 1 8 LF,DCO, VLO 10 14-TSSOP MSP430G2231IN14 14-PDIP MSP430G2221IRSA16 16-QFN MSP430G2221IPW14 - 1 2 128 1x TA2 1 - LF,DCO, VLO 10 14-TSSOP MSP430G2221IN14 14-PDIP MSP430G2131IRSA16 16-QFN MSP430G2131IPW14 - 1 1 128 1x TA2 1 8 LF,DCO, VLO 10 14-TSSOP MSP430G2131IN14 14-PDIP MSP430G2121IRSA16 16-QFN MSP430G2121IPW14 - 1 1 128 1x TA2 1 - LF,DCO, VLO 10 14-TSSOP MSP430G2121IN14 14-PDIP (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. (2) Package drawings,thermaldata,and symbolizationareavailableatwww.ti.com/packaging.

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P1.4/SMCLK/TCK P1.5/T A0.0/SCLK/TMS P1.6/T A0.1/SDO/SCL/TDI/TCLK P1.7/SDI/SDA/TDO/TDI 1 1 DVSS DVSS DVCC DVCC P1.0/T A0CLK/A CLK P1.1/TA0.0 P1.2/TA0.1 P1.3 XIN/P2.6/T A0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO 1DVCC 7 8 P1.6/TA0.1/SDO/SCL/TDI/TCLK 9 P1.7/SDI/SDA/TDO/TDI

10 RST/NMI/SBWTDIO

12 XOUT/P2.7 13 XIN/P2.6/T A0.1

14 DVSS

P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3 P1.4/SMCLK/T CK P1.5/TA0.0/SCLK/TMS MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 Device Pinout,MSP430G2x21 N OR PW PACKAGE (TOP VIEW) NOTE: See portschematicsinApplicationInformationfordetailedI/Oinformation. RSA PACKAGE (TOP VIEW) NOTE: See portschematicsinApplicationInformationfordetailedI/Oinformation. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3

P1.4/SMCLK/A4/VREF+/VEREF+/TCK P1.5/TA0.0/SCLK/A5/TMS P1.6/T A0.1/SDO/SCL/TDI/TCLK P1.7/SDI/SDA/T DO/TDI

9 RST/NMI/SBWTDIO

10 TEST/SBWTCK

1 1 XOUT/P2.7 12 XIN/P2.6/T A0.1 DVSS DVSS DVCC DVCC P1.0/TA0CLK/ACLK/A0 P1.1/TA0.0/A1 P1.2/TA0.1/A2 P1.3/ADC10CLK/A3/VREF-/VER EF- 1DVCC 7 8 P1.6/TA0.1/A6/SD O/SCL/TDI/TCLK 9 P1.7/A7/SDI/SDA/TDO/TDI 12 XOUT/P2.7 13 XIN/P2.6/T A0.1 P1.0/TA0CLK/ACLK/A0 P1.1/TA0.0/A1 P1.2/TA0.1/A2 P1.3/ADC10CLK/A3/VREF-/VEREF- P1.4/ SMCLK/A4/VREF+/VEREF +/TCK P1.5/TA0.0/A5/SCLK/TMS MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com Device Pinout,MSP430G2x31 N OR PW PACKAGE (TOP VIEW) NOTE: See portschematicsinApplicationInformationfordetailedI/Oinformation. RSA PACKAGE (TOP VIEW) NOTE: See portschematicsinApplicationInformationfordetailedI/Oinformation.

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Timer0_A2 2 CC Registers 16MHz CPU incl. 16 Registers Emulation 2BP JT AG Interface SMCLK ACLK MDB MAB Port P1

8 I/O

P1.x Spy-Bi Wire XIN XOUT RAM 128B Flash 2kB 1kB ADC 10-Bit 8 Ch. Autoscan 1 ch DMA P2.x Port P2

2 I/O

SPI, I2C Clock System Brownout Protection RST/NMI DVCC DVSS MCLK Watchdog WDT+ 15-Bit Timer0_A2 2 CC Registers 16MHz CPU incl. 16 Registers Emulation 2BP JT AG Interface SMCLK ACLK MDB MAB Port P1 P1.x Spy-Bi Wire XIN XOUT RAM 128B Flash 2KB 1KB P2.x Port P2 SPI, I2C MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 FunctionalBlock Diagram,MSP430G2x21 FunctionalBlock Diagram,MSP430G2x31 Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5

SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com Table2.TerminalFunctions TERMINAL NO. I/O DESCRIPTION NAME N, PW RSA P1.0/ General-purposedigitalI/Opin TA0CLK/ Timer0_A,clocksignalTACLK input2 1 I/OACLK/ ACLK signaloutput A0 ADC10 analoginputA0 (1) P1.1/ General-purposedigitalI/Opin TA0.0/ 3 2 I/O Timer0_A,capture:CCI0A input,compare:Out0 output A1 ADC10 analoginputA1 (1) P1.2/ General-purposedigitalI/Opin TA0.1/ 4 3 I/O Timer0_A,capture:CCI1A input,compare:Out1 output A2 ADC10 analoginputA2 (1) P1.3/ General-purposedigitalI/Opin ADC10CLK/ ADC10, conversionclockoutput(1) 5 4 I/OA3/ ADC10 analoginputA3 (1) VREF-/VEREF ADC10 negativereferencevoltage(1) P1.4/ General-purposedigitalI/Opin SMCLK/ SMCLK signaloutput A4/ 6 5 I/O ADC10 analoginputA4 (1) VREF+/VEREF+/ ADC10 positivereferencevoltage(1) TCK JTAG testclock,inputterminalfordeviceprogrammingand test P1.5/ General-purposedigitalI/Opin TA0.0/ Timer0_A,compare:Out0 output A5/ 7 6 I/O ADC10 analoginputA5 (1) SCLK/ USI:clockinputinI2C mode; clockinput/outputinSPI mode TMS JTAG testmode select,inputterminalfordeviceprogrammingand test P1.6/ General-purposedigitalI/Opin TA0.1/ Timer0_A,capture:CCI1A input,compare:Out1 output A6/ ADC10 analoginputA6 (1) 8 7 I/OSDO/ USI:Data outputinSPI mode SCL/ USI:I2C clockinI2C mode TDI/TCLK JTAG testdatainputortestclockinputduringprogrammingand test P1.7/ General-purposedigitalI/Opin A7/ ADC10 analoginputA7 (1) SDI/ 9 8 I/O USI:Data inputinSPI mode SDA/ USI:I2C datainI2C mode TDO/TDI (2) JTAG testdataoutputterminalortestdatainputduringprogrammingand test XIN/ Inputterminalofcrystaloscillator P2.6/ 13 12 I/O General-purposedigitalI/Opin TA0.1 Timer0_A,compare:Out1 output XOUT/ Outputterminalofcrystaloscillator(3) 12 11 I/OP2.7 General-purposedigitalI/Opin RST/ Reset NMI/ 10 9 I Nonmaskable interruptinput SBWTDIO Spy-Bi-Wiretestdatainput/outputduringprogrammingand test TEST/ Selectstestmode forJTAG pinson Port1.The deviceprotectionfuseisconnectedtoTEST.11 10 ISBWTCK Spy-Bi-Wiretestclockinputduringprogrammingand test DVCC 1 15,16 NA Supplyvoltage DVSS 14 13,14 NA Ground reference QFN Pad - Pad NA QFN package pad connectiontoVSS recommended. (1) MSP430G2x31 only (2) TDO orTDI isselectedviaJTAG instruction. (3) IfXOUT/P2.7 isused as an input,excesscurrentwillflowuntilP2SEL.7 iscleared.Thisisdue totheoscillatoroutputdriverconnection tothispad afterreset.

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General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R15 General-Purpose Register R14 MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bitRISC architecture that is highlytransparentto the application.All operations,otherthan program-flowinstructions,are performedas registeroperationsinconjunctionwith seven addressingmodes forsourceoperandand four addressingmodes fordestinationoperand. The CPU isintegratedwith16 registersthatprovide reduced instructionexecutiontime.The register-to- registeroperationexecutiontimeisone cycleof the CPU clock. Four of the registers,R0 to R3, are dedicatedas program counter,stackpointer,statusregister,and constant generator,respectively.The remaining registersaregeneral-purposeregisters. Peripheralsare connected to the CPU using data, address,and controlbuses,and can be handledwith allinstructions. The instructionset consistsof the original51 instructionswith threeformatsand seven address modes and additionalinstructionsforthe expanded addressrange.Each instructioncan operateon word and bytedata. InstructionSet The instructionset consistsof 51 instructionswith three formats and seven address modes. Each instructioncan operate on word and byte data. Table 3 shows examples of the three types of instructionformats;Table 4 shows the address modes. Table3.InstructionWord Formats INSTRUCTION FORMAT SYNTAX OPERATION Dualoperands,source-destination ADD R4,R5 R4 + R5 ---> R5 Singleoperands,destinationonly CALL R8 PC -->(TOS),R8--> PC Relativejump,un/conditional JNE Jump-on-equalbit= 0 Table4.Address Mode Descriptions(1) ADDRESS MODE S D SYNTAX EXAMPLE OPERATION Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 ----> R11 Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) ----> M(6+R6) Symbolic(PC relative) ✓ ✓ MOV EDE,TONI M(EDE) ----> M(TONI) Absolute ✓ ✓ MOV &MEM, &TCDAT M(MEM) ----> M(TCDAT) Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) ----> M(Tab+R6) M(R10) ----> R11Indirectautoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 R10 + 2----> R10 Immediate ✓ MOV #X,TONI MOV #45,TONI #45 ----> M(TONI) (1) S = source,D = destination Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7

SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com OperatingModes The MSP430 has one activemode and fivesoftwareselectablelow-powermodes of operation.An interrupt eventcan wake up thedevicefrom any ofthelow-powermodes, servicetherequest,and restoreback tothe low-powermode on returnfromtheinterruptprogram. The followingsixoperatingmodes can be configuredby software:

Activemode (AM) – Allclocksareactive
Low-power mode 0 (LPM0) – CPU isdisabled – ACLK and SMCLK remainactive,MCLK isdisabled
Low-power mode 1 (LPM1) – CPU isdisabled – ACLK and SMCLK remainactive,MCLK isdisabled – DCO's dc generatorisdisabledifDCO notused inactivemode
Low-power mode 2 (LPM2) – CPU isdisabled – MCLK and SMCLK aredisabled – DCO's dc generatorremainsenabled – ACLK remainsactive
Low-power mode 3 (LPM3) – CPU isdisabled – MCLK and SMCLK aredisabled – DCO's dc generatorisdisabled – ACLK remainsactive
Low-power mode 4 (LPM4) – CPU isdisabled – ACLK isdisabled – MCLK and SMCLK aredisabled – DCO's dc generatorisdisabled – Crystaloscillatorisstopped

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www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 InterruptVectorAddresses The interruptvectorsand thepower-upstartingaddressare locatedintheaddressrange 0FFFFh to0FFC0h. The vectorcontainsthe16-bitaddressoftheappropriateinterrupthandlerinstructionsequence. Ifthe resetvector(locatedat address0FFFEh) contains0FFFFh (forexample,flashisnot programmed) the CPU goes intoLPM4 immediatelyafterpower-up. Table5.InterruptSources,Flags,and Vectors SYSTEM WORDINTERRUPT SOURCE INTERRUPT FLAG PRIORITYINTERRUPT ADDRESS Power-Up PORIFG ExternalReset RSTIFG Watchdog Timer+ WDTIFG Reset 0FFFEh 31,highest Flashkey violation KEYV (2) PC out-of-range(1) NMI NMIIFG (non)-maskable Oscillatorfault OFIFG (non)-maskable 0FFFCh 30 Flashmemory accessviolation ACCVIFG (2)(3) (non)-maskable 0FFFAh 29 0FFF8h 28 0FFF6h 27 Watchdog Timer+ WDTIFG maskable 0FFF4h 26 Timer_A2 TACCR0 CCIFG (4) maskable 0FFF2h 25 Timer_A2 TACCR1 CCIFG, TAIFG (2)(4) maskable 0FFF0h 24 0FFEEh 23 0FFECh 22 ADC10 (5) ADC10IFG (4)(5) maskable 0FFEAh 21 USI USIIFG,USISTTIFG (2)(4) maskable 0FFE8h 20 I/OPortP2 (twoflags) P2IFG.6toP2IFG.7(2)(4) maskable 0FFE6h 19 I/OPortP1 (eightflags) P1IFG.0toP1IFG.7(2)(4) maskable 0FFE4h 18 0FFE2h 17 0FFE0h 16 See (6) 0FFDEh to 15 to0,lowest0FFC0h (1) A resetisgeneratediftheCPU triestofetchinstructionsfromwithinthemodule registermemory addressrange(0hto01FFh) orfrom withinunused addressranges. (2) Multiplesourceflags (3) (non)-maskable:theindividualinterrupt-enablebitcan disablean interruptevent,butthegeneralinterruptenablecannot. (4) Interruptflagsarelocatedinthemodule. (5) MSP430G2x31 only (6) The interruptvectorsataddresses0FFDEh to0FFC0h arenotused inthisdeviceand can be used forregularprogramcode if necessary. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9

SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com SpecialFunctionRegisters(SFRs) Most interruptand module enablebitsarecollectedintothelowestaddressspace.Specialfunctionregisterbits notallocatedtoa functionalpurposearenotphysicallypresentinthedevice.Simplesoftwareaccessisprovided withthisarrangement. Legend rw: Bitcan be readand written. rw-0,1: Bitcan be readand written.Itisresetorsetby PUC. rw-(0,1): Bitcan be readand written.Itisresetorsetby POR. SFR bitisnotpresentindevice. Table6.InterruptEnable Register1 and 2 Address 7 6 5 4 3 2 1 0 00h ACCVIE NMIIE OFIE WDTIE rw-0 rw-0 rw-0 rw-0 WDTIE Watchdog Timerinterruptenable.Inactiveifwatchdogmode isselected.ActiveifWatchdog Timerisconfiguredin intervaltimermode. OFIE Oscillatorfaultinterruptenable NMIIE (Non)maskableinterruptenable ACCVIE Flashaccessviolationinterruptenable Address 7 6 5 4 3 2 1 0 01h Table7.InterruptFlagRegister1 and 2 Address 7 6 5 4 3 2 1 0 02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) WDTIFG Seton watchdogtimeroverflow(inwatchdogmode) orsecuritykey violation. Reseton VCC power-onora resetconditionattheRST/NMI pininresetmode. OFIFG Flagseton oscillatorfault. PORIFG Power-On Resetinterruptflag.Seton VCC power-up. RSTIFG Externalresetinterruptflag.Seton a resetconditionatRST/NMI pininresetmode. Reseton VCC power-up. NMIIFG SetviaRST/NMI pin Address 7 6 5 4 3 2 1 0 03h

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www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 Memory Organization Table8.Memory Organization MSP430G2021 MSP430G2121 MSP430G2221 MSP430G2031 MSP430G2131 MSP430G2231 Memory Size 512B 1kB 2kB Main:interruptvector Flash 0xFFFF to0xFFC0 0xFFFF to0xFFC0 0xFFFF to0xFFC0 Main:code memory Flash 0xFFFF to0xFE00 0xFFFF to0xFC00 0xFFFF to0xF800 Informationmemory Size 256 Byte 256 Byte 256 Byte Flash 010FFh to01000h 010FFh to01000h 010FFh to01000h RAM Size 128B 128B 128B 027Fh to0200h 027Fh to0200h 027Fh to0200h Peripherals 16-bit 01FFh to0100h 01FFh to0100h 01FFh to0100h 8-bit 0FFh to010h 0FFh to010h 0FFh to010h 8-bitSFR 0Fh to00h 0Fh to00h 0Fh to00h FlashMemory The flashmemory can be programmed viatheSpy-Bi-Wire/JTAGportor in-systemby theCPU. The CPU can performsingle-byteand single-wordwritestotheflashmemory. Featuresoftheflashmemory include:

Flash memory has n segments of main memory and foursegments of informationmemory (A to D) of 64 byteseach.Each segment inmain memory is512 bytesinsize.
Segments 0 ton may be erasedinone step,oreach segment may be individuallyerased.
Segments A toD can be erasedindividuallyoras a groupwithsegments 0 ton.Segments A toD arealso calledinformationmemory .
Segment A containscalibrationdata.Afterresetsegment A isprotectedagainstprogrammingand erasing.It can be unlockedbutcareshouldbe takennottoerasethissegment ifthedevice-specificcalibrationdatais required. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11

SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com Peripherals Peripheralsare connectedtotheCPU throughdata,address,and controlbuses and can be handledusingall instructions.Forcompletemodule descriptions,see theMSP430x2xx FamilyUser'sGuide (SLAU144 ). Oscillatorand System Clock The clocksystem issupportedby the basicclockmodule thatincludessupportfora 32768-Hz watch crystal oscillator,an internalvery-low-powerlow-frequencyoscillatorand an internaldigitallycontrolledoscillator(DCO). The basic clockmodule is designed to meet the requirementsof both low system cost and low power consumption.The internalDCO providesa fastturn-onclocksourceand stabilizesinlessthan1µs.The basic clockmodule providesthefollowingclocksignals:

Auxiliaryclock(ACLK),sourcedeitherfroma 32768-Hz watchcrystalortheinternalLF oscillator.
Main clock(MCLK),thesystemclockused by theCPU.
Sub-Mainclock(SMCLK), thesub-systemclockused by theperipheralmodules. Table9.DCO CalibrationData (ProvidedFrom FactoryInFlashInformationMemory Segment A) CALIBRATIONDCO FREQUENCY SIZE ADDRESSREGISTER CALBC1_1MHZ byte 010FFh

1 MHz

CALDCO_1MHZ byte 010FEh Brownout The brownoutcircuitisimplementedtoprovidetheproperinternalresetsignaltothedeviceduringpower on and power off. DigitalI/O Thereisone 8-bitI/Oportimplemented— portP1— and two bitsofI/OportP2:

AllindividualI/Obitsareindependentlyprogrammable.
Any combinationofinput,output,and interruptconditionispossible.
Edge-selectableinterruptinputcapabilityforalltheeightbitsofportP1 and thetwo bitsofportP2.
Read/writeaccesstoport-controlregistersissupportedby allinstructions.
Each I/Ohas an individuallyprogrammablepull-up/pull-downresistor. WDT+ Watchdog Timer The primaryfunctionof the watchdog timer(WDT+) module isto performa controlledsystem restartaftera softwareproblem occurs.Ifthe selectedtime intervalexpires,a system resetisgenerated.Ifthe watchdog functionisnotneeded inan application,themodule can be disabledorconfiguredas an intervaltimerand can generateinterruptsatselectedtimeintervals.

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www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 Timer_A2 Timer_A2 is a 16-bittimer/counterwith two capture/compareregisters.Timer_A2 can support multiple capture/compares,PWM outputs,and intervaltiming.Timer_A2 also has extensiveinterruptcapabilities. Interruptsmay be generatedfrom the counteron overflowconditionsand from each of the capture/compare registers. Table10.Timer_A2 SignalConnections – Device With ADC10 INPUT PIN NUMBER MODULE OUTPUT PIN NUMBERDEVICE INPUT MODULE MODULE OUTPUTSIGNAL INPUT NAME BLOCKPW ,N RSA PW ,N RSASIGNAL 2 -P1.0 1 -P1.0 TACLK TACLK ACLK ACLK Timer NA SMCLK SMCLK 2 -P1.0 1 -P1.0 TACLK INCLK 3 -P1.1 2 -P1.1 TA0 CCI0A 3 -P1.1 2 -P1.1 ACLK (internal) CCI0B 7 -P1.5 6 -P1.5 CCR0 TA0 VSS GND VCC VCC 4 -P1.2 3 -P1.2 TA1 CCI1A 4 -P1.2 3 -P1.2 8 -P1.6 7 -P1.6 TA1 CCI1B 8 -P1.6 7 -P1.6 CCR1 TA1 VSS GND 13 -P2.6 12 -P2.6 VCC VCC USI The universalserialinterface(USI)module is used forserialdata communicationand providesthe basic hardwareforsynchronouscommunicationprotocolslikeSPI and I2C. ADC10 (MSP430G2x31 only) The ADC10 module supportsfast,10-bitanalog-to-digitalconversions.The module implementsa 10-bitSAR core,sample selectcontrol,referencegeneratorand datatransfercontroller,or DTC, forautomaticconversion resulthandling,allowingADC samplestobe convertedand storedwithoutany CPU intervention. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13

SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com PeripheralFileMap Table11.PeripheralsWith Word Access REGISTERMODULE REGISTER DESCRIPTION OFFSETNAME ADC10 (MSP430G2x31 only) ADC datatransferstartaddress ADC10SA 1BCh ADC control0 ADC10CTL0 01B0h ADC control1 ADC10CTL0 01B2h ADC memory ADC10MEM 01B4h Timer_A Capture/compareregister TACCR1 0174h Capture/compareregister TACCR0 0172h Timer_A register TAR 0170h Capture/comparecontrol TACCTL1 0164h Capture/comparecontrol TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interruptvector TAIV 012Eh FlashMemory Flashcontrol3 FCTL3 012Ch Flashcontrol2 FCTL2 012Ah Flashcontrol1 FCTL1 0128h Watchdog Timer+ Watchdog/timercontrol WDTCTL 0120h Table12.PeripheralsWith Byte Access REGISTERMODULE REGISTER DESCRIPTION OFFSETNAME ADC10 (MSP430G2x31 only) ADC analogenable ADC10AE0 04Ah ADC datatransfercontrol1 ADC10DTC1 049h ADC datatransfercontrol0 ADC10DTC0 048h USI USI control0 USICTL0 078h USI control1 USICTL1 079h USI clockcontrol USICKCTL 07Ah USI bitcounter USICNT 07Bh USI shiftregister USISR 07Ch Basic Clock System+ Basicclocksystemcontrol3 BCSCTL3 053h Basicclocksystemcontrol2 BCSCTL2 058h Basicclocksystemcontrol1 BCSCTL1 057h DCO clockfrequencycontrol DCOCTL 056h PortP2 PortP2 resistorenable P2REN 02Fh PortP2 selection P2SEL 02Eh PortP2 interruptenable P2IE 02Dh PortP2 interruptedge select P2IES 02Ch PortP2 interruptflag P2IFG 02Bh PortP2 direction P2DIR 02Ah PortP2 output P2OUT 029h PortP2 input P2IN 028h

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www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 Table12.PeripheralsWith Byte Access (continued) REGISTERMODULE REGISTER DESCRIPTION OFFSETNAME PortP1 PortP1 resistorenable P1REN 027h PortP1 selection P1SEL 026h PortP1 interruptenable P1IE 025h PortP1 interruptedge select P1IES 024h PortP1 interruptflag P1IFG 023h PortP1 direction P1DIR 022h PortP1 output P1OUT 021h PortP1 input P1IN 020h SpecialFunction SFR interruptflag2 IFG2 003h SFR interruptflag1 IFG1 002h SFR interruptenable2 IE2 001h SFR interruptenable1 IE1 000h Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15

Supply voltage range , during flash memory programming Supply voltage range , during program execution Legend:

16 MHz

12 MHz

6 MHz

1.8 V Supply Voltage - V 3.3 V2.7 V2.2 V 3.6 V MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com AbsoluteMaximum Ratings(1) VoltageappliedatVCC toVSS –0.3V to4.1V Voltageappliedtoany pin(2) –0.3V toVCC + 0.3V Diodecurrentatany devicepin ±2 mA Unprogrammed device –55°C to150°C Storagetemperaturerange,Tstg (3) Programmed device –55°C to150°C (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagesreferencedtoVSS .The JTAG fuse-blowvoltage,VFB ,isallowedtoexceed theabsolutemaximum rating.The voltageis appliedtotheTEST pinwhen blowingtheJTAG fuse. (3) Highertemperaturemay be appliedduringboardsolderingaccordingtothecurrentJEDEC J-STD-020specificationwithpeak reflow temperaturesnothigherthanclassifiedon thedevicelabelon theshippingboxes orreels. Recommended OperatingConditions TypicalvaluesarespecifiedatVCC = 3.3V and TA = 25°C (unlessotherwisenoted) MIN NOM MAX UNIT Duringprogramexecution 1.8 3.6 VCC Supplyvoltage V Duringflashprogramming 2.2 3.6 VSS Supplyvoltage 0 V TA Operatingfree-airtemperature Iversion –40 85 °C VCC = 1.8V, dc 6Dutycycle= 50% ± 10% VCC = 2.7V,fSYSTEM Processorfrequency(maximum MCLK frequency)(1)(2) dc 12 MHzDutycycle= 50% ± 10% VCC = 3.3V, dc 16Dutycycle= 50% ± 10% (1) The MSP430 CPU isclockeddirectlywithMCLK. Boththehighand lowphase ofMCLK must notexceed thepulsewidthofthe specifiedmaximum frequency. (2) Modules mighthave a differentmaximum inputclockspecification.See thespecificationoftherespectivemodule inthisdatasheet. Note: Minimum processorfrequencyisdefinedby system clock.Flashprogram oreraseoperationsrequirea minimum VCC of2.2V. Figure1. Safe OperatingArea

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0.0 1.0 2.0 3.0 4.0 5.0 VCC − Supply Voltage − V Active Mode Current − mA fDCO = 1 MHz fDCO = 8 MHz fDCO = 12 MHz fDCO = 16 MHz 0.0 1.0 2.0 3.0 4.0 fDCO − DCO Frequency − MHz Active Mode Current − mA TA = 25 °C TA = 85 °C VCC = 2.2 V VCC = 3 V TA = 25 °C TA = 85 °C MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 ElectricalCharacteristics ActiveMode Supply CurrentIntoVCC ExcludingExternalCurrent overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted)(1)(2) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT fDCO = fMCLK = fSMCLK = 1 MHz, 2.2V 220 fACLK = 32768 Hz, Program executesinflash,Activemode (AM)IAM,1MHz BCSCTL1 = CALBC1_1MHZ, µAcurrent(1MHz) 3 V 300 370DCOCTL = CALDCO_1MHZ, CPUOFF = 0,SCG0 = 0,SCG1 = 0, OSCOFF = 0 (1) Allinputsaretiedto0 V ortoVCC .Outputsdo notsourceorsinkany current. (2) The currentsarecharacterizedwitha MicroCrystalCC4V-T1A SMD crystalwitha loadcapacitanceof9 pF.The internaland external loadcapacitanceischosen tocloselymatch therequired9 pF. TypicalCharacteristics– ActiveMode Supply Current(IntoVCC ) Figure2.ActiveMode Currentvs VCC ,TA = 25°C Figure3.ActiveMode Currentvs DCO Frequency Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 -40 I – Low-Power Mode Current – µALPM3 Vcc = 3.6 V T – Temperature – °CA Vcc = 1.8 V Vcc = 3 V Vcc = 2.2 V -20 0 20 40 60 80 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 -40 I – Low-Power Mode Current – µALPM4 Vcc = 3.6 V T – Temperature – °CA Vcc = 1.8 V Vcc = 3 V Vcc = 2.2 V -20 0 20 40 60 80 MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com Low-Power Mode Supply Currents(IntoVCC )ExcludingExternalCurrent overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted)(1)(2) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32768 Hz,Low-power mode 0ILPM0,1MHz BCSCTL1 = CALBC1_1MHZ, 25°C 2.2V 65 µA(LPM0) current(3) DCOCTL = CALDCO_1MHZ, CPUOFF = 1,SCG0 = 0,SCG1 = 0, OSCOFF = 0 fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz, fACLK = 32768 Hz,Low-power mode 2ILPM2 BCSCTL1 = CALBC1_1MHZ, 25°C 2.2V 22 µA(LPM2) current(4) DCOCTL = CALDCO_1MHZ, CPUOFF = 1,SCG0 = 0,SCG1 = 1, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz, Low-power mode 3 fACLK = 32768 Hz,ILPM3,LFXT1 25°C 2.2V 0.7 1.5 µA(LPM3) current(4) CPUOFF = 1,SCG0 = 1,SCG1 = 1, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz, Low-power mode 3 fACLK frominternalLF oscillator(VLO),ILPM3,VLO 25°C 2.2V 0.5 0.7 µAcurrent,(LPM3)(4) CPUOFF = 1,SCG0 = 1,SCG1 = 1, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz, 25°C 2.2V 0.1 0.5 µA Low-power mode 4 fACLK = 0 Hz,ILPM4 (LPM4) current(5) CPUOFF = 1,SCG0 = 1,SCG1 = 1, 85°C 2.2V 0.8 1.5 µA OSCOFF = 1 (1) Allinputsaretiedto0 V ortoVCC .Outputsdo notsourceorsinkany current. (2) The currentsarecharacterizedwitha MicroCrystalCC4V-T1A SMD crystalwitha loadcapacitanceof9 pF. (3) Currentforbrownoutand WDT clockedby SMCLK included. (4) Currentforbrownoutand WDT clockedby ACLK included. (5) Currentforbrownoutincluded. TypicalCharacteristicsLow-Power Mode Supply Currents overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) Figure4.LPM3 Currentvs Temperature Figure5.LPM4 Currentvs Temperature

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www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 Schmitt-TriggerInputs– PortsPx overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 0.45VCC 0.75VCC VIT+ Positive-goinginputthresholdvoltage V 3 V 1.35 2.25 0.25VCC 0.55VCC VIT– Negative-goinginputthresholdvoltage V 3 V 0.75 1.65 Vhys Inputvoltagehysteresis(VIT+ – VIT–) 3 V 0.3 1 V Forpullup:VIN = VSSR Pull Pullup/pulldownresistor 3 V 20 35 50 kΩForpulldown:VIN = VCC C I Inputcapacitance VIN = VSS orVCC 5 pF Leakage Current– PortsPx overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Ilkg(Px.y) High-impedanceleakagecurrent (1)(2) 3 V ±50 nA (1) The leakagecurrentismeasured withVSS orVCC appliedtothecorrespondingpin(s),unlessotherwisenoted. (2) The leakageofthedigitalportpinsismeasured individually.The portpinisselectedforinputand thepullup/pulldownresistoris disabled. Outputs – PortsPx overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VOH High-leveloutputvoltage I(OHmax) = –6 mA (1) 3 V VCC – 0.3 V VOL Low-leveloutputvoltage I(OLmax) = 6 mA (1) 3 V VSS + 0.3 V (1) The maximum totalcurrent,I(OHmax) and I(OLmax),foralloutputscombined shouldnotexceed ±48 mA toholdthemaximum voltagedrop specified. Output Frequency – PortsPx overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT PortoutputfrequencyfPx.y Px.y,C L = 20 pF,R L = 1 kΩ(1)(2) 3 V 12 MHz(withload) fPort_CLK Clockoutputfrequency Px.y,C L = 20 pF (2) 3 V 16 MHz (1) A resistivedividerwith2 × 0.5kΩ between VCC and VSS isused as load.The outputisconnectedtothecentertapofthedivider. (2) The outputvoltagereachesatleast10% and 90% VCC atthespecifiedtogglefrequency. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19

VOH − High-Level Output Voltage − V −25 −20 −15 −10 0 0.5 1 1.5 2 2.5 VCC = 2.2 V P1.7 TA = 25°C TA = 85°C OHI − Typical High-Level Output Current − mA VOH − High-Level Output Voltage − V −50 −40 −30 −20 −10 0 0.5 1 1.5 2 2.5 3 3.5 VCC = 3 V P1.7 TA = 25°C TA = 85°C OHI − Typical High-Level Output Current − mA VOL − Low-Level Output Voltage − V 0 0.5 1 1.5 2 2.5 VCC = 2.2 V P1.7 TA = 25°C TA = 85°C OLI − Typical Low-Level Output Current − mA VOL − Low-Level Output Voltage − V 0 0.5 1 1.5 2 2.5 3 3.5 VCC = 3 V P1.7 TA = 25°C TA = 85°C OLI − Typical Low-Level Output Current − mA MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com TypicalCharacteristics– Outputs overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT vs vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE Figure6. Figure7. TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT vs vs HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE Figure8. Figure9.

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t d(BOR) VCC V(B_IT−) Vhys(B_IT−) VCC(star t) MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 POR, BOR (1)(2) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) See Figure10 dVCC /dt≤ 3 V/s 0.7× V(B_IT–) V V(B_IT–) See Figure10 throughFigure12 dVCC /dt≤ 3 V/s 1.35 V Vhys(B_IT–) See Figure10 dVCC /dt≤ 3 V/s 140 mV td(BOR) See Figure10 2000 µs Pulsedurationneeded atRST/NMI pintot(reset) 2.2V,3 V 2 µsacceptedresetinternally (1) The currentconsumptionofthebrownoutmodule isalreadyincludedintheICC currentconsumptiondata.The voltagelevelV(B_IT–) + Vhys(B_IT–)is≤ 1.8V. (2) Duringpower up,theCPU beginscode executionfollowinga periodoftd(BOR) afterVCC = V(B_IT–) + Vhys(B_IT–).The defaultDCO settings must notbe changed untilVCC ≥ VCC(min),where VCC(min) istheminimum supplyvoltageforthedesiredoperatingfrequency. Figure10. POR and BOR vs Supply Voltage Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21

0.5 1.5 VCC(drop) t pw tpw − Pulse Width − µs VCC(drop) − V 3 V 0.001 1 1000 tf tr tpw − Pulse Width − µs tf = tr Typical Conditions VCC = 3 V VCC(drop) VCC 3 V t pw 0.5 1.5 0.001 1 1000 Typical Conditions 1 ns 1 ns tpw − Pulse Width − µs VCC(drop) − V tpw − Pulse Width − µs VCC = 3 V MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com TypicalCharacteristics– POR and BOR Figure11.VCC(drop) LevelWith a Square VoltageDrop toGenerate a POR or BOR Signal Figure12.VCC(drop) LevelWith a TriangleVoltageDrop toGenerate a POR or BOR Signal

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DCO(RSEL,DCO+1)DCO(RSEL,DCO) average DCO(RSEL,DCO) DCO(RSEL,DCO+1) 32 × f × f f = MOD × f + (32 – MOD) × f MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 Main DCO Characteristics

Allranges selectedby RSELx overlapwithRSELx + 1: RSELx = 0 overlapsRSELx = 1, ...RSELx = 14 overlapsRSELx = 15.
DCO controlbitsDCOx have a stepsizeas definedby parameterSDCO .
ModulationcontrolbitsMODx selecthow oftenfDCO(RSEL,DCO+1) isused withinthe periodof 32 DCOCLK cycles.The frequencyfDCO(RSEL,DCO) isused fortheremainingcycles.The frequencyisan averageequalto: DCO Frequency overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT RSELx < 14 1.8 3.6 V VCC Supplyvoltage RSELx = 14 2.2 3.6 V RSELx = 15 3 3.6 V fDCO(0,0) DCO frequency(0,0) RSELx = 0,DCOx = 0,MODx = 0 3 V 0.06 0.14 MHz fDCO(0,3) DCO frequency(0,3) RSELx = 0,DCOx = 3,MODx = 0 3 V 0.12 MHz fDCO(1,3) DCO frequency(1,3) RSELx = 1,DCOx = 3,MODx = 0 3 V 0.15 MHz fDCO(2,3) DCO frequency(2,3) RSELx = 2,DCOx = 3,MODx = 0 3 V 0.21 MHz fDCO(3,3) DCO frequency(3,3) RSELx = 3,DCOx = 3,MODx = 0 3 V 0.30 MHz fDCO(4,3) DCO frequency(4,3) RSELx = 4,DCOx = 3,MODx = 0 3 V 0.41 MHz fDCO(5,3) DCO frequency(5,3) RSELx = 5,DCOx = 3,MODx = 0 3 V 0.58 MHz fDCO(6,3) DCO frequency(6,3) RSELx = 6,DCOx = 3,MODx = 0 3 V 0.80 MHz fDCO(7,3) DCO frequency(7,3) RSELx = 7,DCOx = 3,MODx = 0 3 V 0.8 1.5 MHz fDCO(8,3) DCO frequency(8,3) RSELx = 8,DCOx = 3,MODx = 0 3 V 1.6 MHz fDCO(9,3) DCO frequency(9,3) RSELx = 9,DCOx = 3,MODx = 0 3 V 2.3 MHz fDCO(10,3) DCO frequency(10,3) RSELx = 10,DCOx = 3,MODx = 0 3 V 3.4 MHz fDCO(11,3) DCO frequency(11,3) RSELx = 11,DCOx = 3,MODx = 0 3 V 4.25 MHz fDCO(12,3) DCO frequency(12,3) RSELx = 12,DCOx = 3,MODx = 0 3 V 4.3 7.3 MHz fDCO(13,3) DCO frequency(13,3) RSELx = 13,DCOx = 3,MODx = 0 3 V 7.8 MHz fDCO(14,3) DCO frequency(14,3) RSELx = 14,DCOx = 3,MODx = 0 3 V 8.6 13.9 MHz fDCO(15,3) DCO frequency(15,3) RSELx = 15,DCOx = 3,MODx = 0 3 V 15.25 MHz fDCO(15,7) DCO frequency(15,7) RSELx = 15,DCOx = 7,MODx = 0 3 V 21 MHz FrequencystepbetweenSRSEL SRSEL = fDCO(RSEL+1,DCO) /fDCO(RSEL,DCO) 3 V 1.35 ratiorangeRSEL and RSEL+1 FrequencystepbetweenSDCO SDCO = fDCO(RSEL,DCO+1) /fDCO(RSEL,DCO) 3 V 1.08 ratiotapDCO and DCO+1 Dutycycle Measured atSMCLK output 3 V 50 % Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23

DCO Frequency − MHz 0.10 1.00 10.00 0.10 1.00 10.00 DCO Wake Time − µs RSELx = 0...1 1 RSELx = 12...15 MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com CalibratedDCO Frequencies– Tolerance overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT BCSCTL1= CALBC1_1MHz,1-MHz toleranceover DCOCTL = CALDCO_1MHz, 0°C to85°C 3 V -3 ±0.5 +3 %temperature(1) calibratedat30°C and 3 V BCSCTL1= CALBC1_1MHz, 1-MHz toleranceoverVCC DCOCTL = CALDCO_1MHz, 30°C 1.8V to3.6V -3 ±2 +3 % calibratedat30°C and 3 V BCSCTL1= CALBC1_1MHz, 1-MHz toleranceoverall DCOCTL = CALDCO_1MHz, -40°C to85°C 1.8V to3.6V -6 ±3 +6 % calibratedat30°C and 3 V (1) Thisisthefrequencychange fromthemeasured frequencyat30°C overtemperature. Wake-Up From Lower-Power Modes (LPM3/4)– ElectricalCharacteristics overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT DCO clockwake-up timefrom BCSCTL1= CALBC1_1MHz,tDCO,LPM3/4 3 V 1.5 µsLPM3/4 (1) DCOCTL = CALDCO_1MHz 1/fMCLK +tCPU,LPM3/4 CPU wake-up timefromLPM3/4 (2) tClock,LPM3/4 (1) The DCO clockwake-up timeismeasured fromtheedge ofan externalwake-up signal(forexample,portinterrupt)tothefirstclock edge observableexternallyon a clockpin(MCLK orSMCLK). (2) ParameterapplicableonlyifDCOCLK isused forMCLK. TypicalCharacteristics– DCO Clock Wake-Up Time From LPM3/4 Figure13.DCO Wake-Up Time From LPM3 vs DCO Frequency

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www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 CrystalOscillator,XT1, Low-Frequency Mode (1) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT LFXT1 oscillatorcrystalfLFXT1,LF XTS = 0,LFXT1Sx = 0 or1 1.8V to3.6V 32768 Hzfrequency,LF mode 0,1 LFXT1 oscillatorlogiclevel fLFXT1,LF,logic squarewave inputfrequency,XTS = 0,XCAPx = 0,LFXT1Sx = 3 1.8V to3.6V 10000 32768 50000 Hz LF mode XTS = 0,LFXT1Sx = 0, 500fLFXT1,LF = 32768 Hz,C L,eff= 6 pFOscillationallowanceforOA LF kΩLF crystals XTS = 0,LFXT1Sx = 0, 200fLFXT1,LF = 32768 Hz,C L,eff= 12 pF XTS = 0,XCAPx = 0 1 XTS = 0,XCAPx = 1 5.5IntegratedeffectiveloadC L,eff pFcapacitance,LF mode (2) XTS = 0,XCAPx = 2 8.5 XTS = 0,XCAPx = 3 11 XTS = 0,Measured atP2.0/ACLK,Dutycycle,LF mode 2.2V 30 50 70 %fLFXT1,LF = 32768 Hz Oscillatorfaultfrequency,fFault,LF XTS = 0,XCAPx = 0,LFXT1Sx = 3(4) 2.2V 10 10000 HzLF mode (3) (1) To improveEMI on theXT1 oscillator,thefollowingguidelinesshouldbe observed. (a) Keep thetracebetween thedeviceand thecrystalas shortas possible. (b) Designa good groundplanearoundtheoscillatorpins. (c)PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXIN and XOUT. (d) AvoidrunningPCB tracesunderneathoradjacenttotheXIN and XOUT pins. (e) Use assemblymaterialsand praxistoavoidany parasiticloadon theoscillatorXIN and XOUT pins. (f)Ifconformalcoatingisused,ensurethatitdoes notinducecapacitive/resistiveleakagebetween theoscillatorpins. (g) Do notroutetheXOUT linetotheJTAG headertosupporttheserialprogrammingadapteras shown inotherdocumentation.This signalisno longerrequiredfortheserialprogrammingadapter. (2) Includesparasiticbond and package capacitance(approximately2 pF perpin). SincethePCB adds additionalcapacitance,itisrecommended toverifythecorrectloadby measuringtheACLK frequency.Fora correctsetup,theeffectiveloadcapacitanceshouldalwaysmatch thespecificationoftheused crystal. (3) FrequenciesbelowtheMIN specificationsetthefaultflag.Frequenciesabove theMAX specificationdo notsetthefaultflag. Frequenciesinbetween mightsettheflag. (4) Measured withlogic-levelinputfrequencybutalsoappliestooperationwithcrystals. InternalVery-Low-Power Low-Frequency Oscillator(VLO) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TA VCC MIN TYP MAX UNIT fVLO VLO frequency -40°C to85°C 3 V 4 12 20 kHz dfVLO /dT VLO frequencytemperaturedrift -40°C to85°C 3 V 0.5 %/°C dfVLO /dVCC VLO frequencysupplyvoltagedrift 25°C 1.8V to3.6V 4 %/V Timer_A overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal:SMCLK, ACLK fTA Timer_A inputclockfrequency External:TACLK, INCLK fSYSTEM MHz Dutycycle= 50% ± 10% tTA,cap Timer_A capturetiming TA0, TA1 3 V 20 ns Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25

VOL − Low-Level Output Voltage − V 0.0 1.0 2.0 3.0 4.0 5.0 VCC = 2.2 V TA = 25°C OLI − Low-Level Output Current − mA TA = 85°C VOL − Low-Level Output Voltage − V 0.0 1.0 2.0 3.0 4.0 5.0 VCC = 3 V TA = 25°C OLI − Low-Level Output Current − mA TA = 85°C MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com USI,UniversalSerialInterface overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT External:SCLK, fUSI USI clockfrequency Dutycycle= 50% ±10%, fSYSTEM MHz SPI slavemode USI module inI2C mode, VSSVOL,I2C Low-leveloutputvoltageon SDA and SCL 3 V VSS VI(OLmax) = 1.5mA + 0.4 TypicalCharacteristics– USI Low-Level Output Voltageon SDA and SCL Figure14.USI Low-Level Output Voltagevs Output Current Figure15.USI Low-Level Output Voltagevs Output Current

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www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 10-BitADC, Power Supply and InputRange Conditions(MSP430G2x31 Only) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT VCC Analogsupplyvoltage VSS = 0 V 2.2 3.6 V AllAx terminals,AnaloginputsVAx Analoginputvoltage(2) 3 V 0 VCC VselectedinADC10AE register fADC10CLK = 5.0MHz, ADC10ON = 1,REFON = 0,IADC10 ADC10 supplycurrent(3) 25°C 3 V 0.6 mAADC10SHT0 = 1,ADC10SHT1 = 0, ADC10DIV = 0 fADC10CLK = 5.0MHz, ADC10ON = 0,REF2_5V = 0, 0.25 REFON = 1,REFOUT = 0Referencesupplycurrent,IREF+ 25°C 3 V mAreferencebufferdisabled(4) fADC10CLK = 5.0MHz, ADC10ON = 0,REF2_5V = 1, 0.25 REFON = 1,REFOUT = 0 fADC10CLK = 5.0MHz, Referencebuffersupply ADC10ON = 0,REFON = 1,IREFB,0 25°C 3 V 1.1 mAcurrentwithADC10SR = 0(4) REF2_5V = 0,REFOUT = 1, ADC10SR = 0 fADC10CLK = 5.0MHz, Referencebuffersupply ADC10ON = 0,REFON = 1,IREFB,1 25°C 3 V 0.5 mAcurrentwithADC10SR = 1(4) REF2_5V = 0,REFOUT = 1, ADC10SR = 1 Onlyone terminalAx can be selectedC I Inputcapacitance 25°C 3 V 27 pFatone time R I InputMUX ON resistance 0 V ≤ VAx ≤ VCC 25°C 3 V 1000 Ω (1) The leakagecurrentisdefinedintheleakagecurrenttablewithPx.y/Axparameter. (2) The analoginputvoltagerangemust be withintheselectedreferencevoltagerangeVR+ toVR – forvalidconversionresults. (3) The internalreferencesupplycurrentisnotincludedincurrentconsumptionparameterIADC10 . (4) The internalreferencecurrentissuppliedviaterminalVCC .ConsumptionisindependentoftheADC10ON controlbit,unlessa conversionisactive.The REFON bitenablesthebuilt-inreferencetosettlebeforestartingan A/D conversion. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27

SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com 10-BitADC, Built-InVoltageReference(MSP430G2x31 Only) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT IVREF+ ≤ 1 mA, REF2_5V = 0 2.2Positivebuilt-inreferenceVCC,REF+ Vanalogsupplyvoltagerange IVREF+ ≤ 1 mA, REF2_5V = 1 2.9 Maximum VREF+ loadILD,VREF+ 3 V ±1 mAcurrent IVREF+ = 500 µA ± 100 µA, AnaloginputvoltageVAx ≉ 0.75V, ±2 REF2_5V = 0 VREF+ loadregulation 3 V LSB IVREF+ = 500 µA ± 100 µA, AnaloginputvoltageVAx ≉ 1.25V, ±2 REF2_5V = 1 IVREF+ = 100 µA→900 µA, VREF+ loadregulation VAx ≉ 0.5× VREF+, 3 V 400 nsresponsetime Errorofconversionresult≤ 1 LSB, ADC10SR = 0 Maximum capacitanceatC VREF+ IVREF+ ≤ ±1 mA, REFON = 1,REFOUT = 1 3 V 100 pFpinVREF+ ppm/TC REF+ Temperaturecoefficient IVREF+ = constwith0 mA ≤ IVREF+ ≤ 1 mA 3 V ±100 °C Settlingtimeofinternal IVREF+ = 0.5mA, REF2_5V = 0,tREFON referencevoltageto99.9% 3.6V 30 µsREFON = 0 → 1VREF IVREF+ = 0.5mA,SettlingtimeofreferencetREFBURST REF2_5V = 1,REFON = 1, 3 V 2 µsbufferto99.9% VREF REFBURST = 1,ADC10SR = 0

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www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 10-BitADC, ExternalReference(1)(MSP430G2x31 Only) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VEREF+ > VEREF –, 1.4 VCCSREF1 = 1,SREF0 = 0PositiveexternalreferenceinputVEREF+ Vvoltagerange (2) VEREF – ≤ VEREF+ ≤ VCC – 0.15V, 1.4 3SREF1 = 1,SREF0 = 1 (3) NegativeexternalreferenceinputVEREF – VEREF+ > VEREF – 0 1.2 Vvoltagerange (4) Differentialexternalreference ΔVEREF inputvoltagerange, VEREF+ > VEREF – (5) 1.4 VCC V ΔVEREF = VEREF+ – VEREF –

0 V ≤ VEREF+ ≤ VCC , 3 V ±1SREF1 = 1,SREF0 = 0

IVEREF+ StaticinputcurrentintoVEREF+ µA 0 V ≤ VEREF+ ≤ VCC – 0.15V ≤ 3 V, 3 V 0SREF1 = 1,SREF0 = 1(3) IVEREF – StaticinputcurrentintoVEREF – 0 V ≤ VEREF – ≤ VCC 3 V ±1 µA (1) The externalreferenceisused duringconversiontochargeand dischargethecapacitancearray.The inputcapacitance,C I,isalsothe dynamicloadforan externalreferenceduringconversion.The dynamicimpedance ofthereferencesupplyshouldfollowthe recommendationson analog-sourceimpedance toallowthechargetosettlefor10-bitaccuracy. (2) The accuracylimitstheminimum positiveexternalreferencevoltage.Lower referencevoltagelevelsmay be appliedwithreduced accuracyrequirements. (3) Under thisconditiontheexternalreferenceisinternallybuffered.The referencebufferisactiveand requiresthereferencebuffersupply currentIREFB .The currentconsumptioncan be limitedtothesample and conversionperiodwithREBURST = 1. (4) The accuracylimitsthemaximum negativeexternalreferencevoltage.Higherreferencevoltagelevelsmay be appliedwithreduced accuracyrequirements. (5) The accuracylimitstheminimum externaldifferentialreferencevoltage.Lower differentialreferencevoltagelevelsmay be appliedwith reducedaccuracyrequirements. 10-BitADC, Timing Parameters (MSP430G2x31 Only) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT ADC10SR = 0 0.45 6.3ADC10 inputclock ForspecifiedperformanceoffADC10CLK 3 V MHzfrequency ADC10 linearityparameters ADC10SR = 1 0.45 1.5 ADC10 built-in ADC10DIVx = 0,ADC10SSELx = 0,fADC10OSC 3 V 3.7 6.3 MHzoscillatorfrequency fADC10CLK = fADC10OSC ADC10 built-inoscillator,ADC10SSELx = 0, 3 V 2.06 3.51fADC10CLK = fADC10OSC tCONVERT Conversiontime µs13 ×fADC10CLK fromACLK, MCLK, orSMCLK, ADC10DIV ×ADC10SSELx ≠ 0 1/fADC10CLK Turn-onsettlingtimetADC10ON (1) 100 nsoftheADC (1) The conditionisthattheerrorina conversionstartedaftertADC10ON islessthan±0.5LSB. The referenceand inputsignalarealready settled. 10-BitADC, LinearityParameters (MSP430G2x31 Only) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT EI Integrallinearityerror 3 V ±1 LSB ED Differentiallinearityerror 3 V ±1 LSB EO Offseterror Sourceimpedance R S < 100 Ω 3 V ±1 LSB EG Gain error 3 V ±1.1 ±2 LSB ET Totalunadjustederror 3 V ±2 ±5 LSB Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29

SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com 10-BitADC, Temperature Sensor and Built-InVMID (MSP430G2x31 Only) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Temperaturesensorsupply REFON = 0,INCHx = 0Ah,ISENSOR 3 V 60 µAcurrent(1) TA = 25°C TC SENSOR ADC10ON = 1,INCHx = 0Ah (2) 3 V 3.55 mV/°C Sample timerequiredifchannel ADC10ON = 1,INCHx = 0Ah,tSensor(sample) 3 V 30 µs10 isselected(3) Errorofconversionresult≤ 1 LSB IVMID Currentintodivideratchannel11 ADC10ON = 1,INCHx = 0Bh 3 V (4) µA ADC10ON = 1,INCHx = 0Bh,VMID VCC divideratchannel11 3 V 1.5 VVMID ≉ 0.5× VCC Sample timerequiredifchannel ADC10ON = 1,INCHx = 0Bh,tVMID(sample) 3 V 1220 ns11 isselected(5) Errorofconversionresult≤ 1 LSB (1) The sensorcurrentISENSOR isconsumed if(ADC10ON = 1 and REFON = 1)or(ADC10ON = 1 and INCH = 0Ah and sample signalis high).When REFON = 1,ISENSOR isincludedinIREF+ .When REFON = 0,ISENSOR appliesduringconversionofthetemperaturesensor input(INCH = 0Ah). (2) The followingformulacan be used tocalculatethetemperaturesensoroutputvoltage: VSensor,typ= TC Sensor (273+ T [°C] )+ VOffset,sensor[mV]or VSensor,typ= TC Sensor T [°C] + VSensor(TA = 0°C) [mV] (3) The typicalequivalentimpedance ofthesensoris51 kΩ.The sample timerequiredincludesthesensor-ontimetSENSOR(on) . (4) No additionalcurrentisneeded.The VMID isused duringsampling. (5) The on-timetVMID(on) isincludedinthesamplingtimetVMID(sample);no additionalon timeisneeded. FlashMemory overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST VCC MIN TYP MAX UNITCONDITIONS VCC(PGM/ERASE) Program and erasesupplyvoltage 2.2 3.6 V fFTG Flashtiminggeneratorfrequency 257 476 kHz IPGM SupplycurrentfromVCC duringprogram 2.2V,3.6V 1 5 mA IERASE SupplycurrentfromVCC duringerase 2.2V,3.6V 1 7 mA tCPT Cumulativeprogramtime(1) 2.2V,3.6V 10 ms tCMErase Cumulativemass erasetime 2.2V,3.6V 20 ms Program/eraseendurance 104 105 cycles tRetention Data retentionduration TJ = 25°C 100 years tWord Word orbyteprogramtime (2) 30 tFTG tBlock,0 Blockprogramtimeforfirstbyteorword (2) 25 tFTG Blockprogramtimeforeach additionalbyteortBlock,1-63 (2) 18 tFTGword tBlock,End Blockprogramend-sequencewaittime (2) 6 tFTG tMass Erase Mass erasetime (2) 10593 tFTG tSeg Erase Segment erasetime (2) 4819 tFTG (1) The cumulativeprogramtimemust notbe exceeded when writingtoa 64-byteflashblock.Thisparameterappliestoallprogramming methods:individualword/bytewriteand blockwritemodes. (2) These valuesarehardwiredintotheFlashController's statemachine (tFTG = 1/fFTG ).

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www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 RAM overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN MAX UNIT V(RAMh) RAM retentionsupplyvoltage(1) CPU halted 1.6 V (1) Thisparameterdefinestheminimum supplyvoltageVCC when thedatainRAM remainsunchanged.No programexecutionshould happen duringthissupplyvoltagecondition. JTAG and Spy-Bi-WireInterface overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wireinputfrequency 2.2V,3 V 0 20 MHz tSBW,Low Spy-Bi-Wirelowclockpulselength 2.2V,3 V 0.025 15 µs Spy-Bi-WireenabletimetSBW,En 2.2V,3 V 1 µs(TEST hightoacceptanceoffirstclockedge(1)) tSBW,Ret Spy-Bi-Wirereturntonormaloperationtime 2.2V,3 V 15 100 µs 2.2V 0 5 MHz fTCK TCK inputfrequency(2)

3 V 0 10 MHz

R Internal Internalpulldownresistanceon TEST 2.2V,3 V 25 60 90 kΩ (1) ToolsaccessingtheSpy-Bi-Wireinterfaceneed towaitforthemaximum tSBW,En timeafterpullingtheTEST/SBWCLK pinhighbefore applyingthefirstSBWCLK clockedge. (2) fTCK may be restrictedtomeet thetimingrequirementsofthemodule selected. JTAG Fuse (1) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN MAX UNIT VCC(FB) Supplyvoltageduringfuse-blowcondition TA = 25°C 2.5 V VFB Voltagelevelon TEST forfuseblow 6 7 V IFB SupplycurrentintoTEST duringfuseblow 100 mA tFB Time toblowfuse 1 ms (1) Once thefuseisblown,no furtheraccesstotheJTAG/Test,Spy-Bi-Wire,and emulationfeatureispossible,and JTAG isswitchedto bypassmode. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31

P1.0/T A0CLK/ACLK P1.1/T A0.0 P1.2/T A0.1 P1.3 T o Module From Timer PxOUT . y DVSS DVCC 1 PxIN.y PxSEL.y PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Input 1: Output PxDIR.y PxSEL.y MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com

APPLICATION INFORMATION

PortP1 Pin Schematic:P1.0toP1.3,Input/OutputWith SchmittTrigger– MSP430G2x21 Table13.PortP1 (P1.0toP1.3)Pin Functions– MSP430G2x21 CONTROL BITS/SIGNALS PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x TA0CLK/ 0 TA0CLK 0 1 ACLK ACLK 1 1 TA0.0 1 TA0.CCI0A 0 1 TA0.0 1 1 TA0.1 2 TA0.CCI1A 0 1 TA0.1 1 1

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PxOUT . y DVSS DVCC 1 PxIN.y PxSEL.y PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Input 1: Output PxDIR.y PxSEL.y From JTAG T o J T A G P1.4/SMCLK/TCK MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 PortP1 Pin Schematic:P1.4,Input/OutputWith SchmittTrigger– MSP430G2x21 Table14.PortP1 (P1.4)Pin Functions– MSP430G2x21 CONTROL BITS /SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x JTAG Mode P1.4/ P1.x(I/O) I:0;O: 1 0 0 SMCLK/ 4 SMCLK 1 1 0 TCK TCK X X 1 (1) X = don'tcare Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33

PxOUT.y DVSS DVCC 1 PxIN.y PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Input 1: Output PxDIR.y PxSEL.y From JTAG T o J T AG P1.5/T A0.0/SCLK/TMS PxSEL.y or USI P E5 PxSEL.y From US I MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com PortP1 Pin Schematic:P1.5,Input/OutputWith SchmittTrigger– MSP430G2x21 Table15.PortP1 (P1.5)Pin Functions– MSP430G2x21 CONTROL BITS /SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x USIP.x JTAG Mode TA0.0/ TA0.0 1 1 0 0 SCLK/ SCLK X X 1 0 TMS TMS X X 0 1 (1) X = don'tcare

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PxOUT . y DVSS DVCC 1 PxIN.y PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Input 1: Output PxDIR.y PxSEL.y From JT AG T o J T A G P1.6/T A0.1/SDO/SCL/TDI PxSEL.y or USI P E6 PxSEL.y MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 PortP1 Pin Schematic:P1.6,Input/OutputWith SchmittTrigger– MSP430G2x21 Table16.PortP1 (P1.6)Pin Functions– MSP430G2x21 CONTROL BITS /SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x USIP.x JTAG Mode TA0.1/ TA0.1 1 1 0 0 6 TA0.CCI1B 0 1 0 0 SDO/SCL/ SDO/SCL X X 1 0 TDI/TCLK TDI/TCLK X X 0 1 (1) X = don'tcare Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35

PxOUT . y DVSS DVCC 1 PxIN.y PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Input 1: Output PxDIR.y USIPE7 From JT AG T o J T A G P1.7/SDI/SDA/TDO/TDI PxSEL.y or USI P E7 PxSEL.y From JT AG T o J T A G From US I MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com PortP1 Pin Schematic:P1.7,Input/OutputWith SchmittTrigger– MSP430G2x21 Table17.PortP1 (P1.7)Pin Functions– MSP430G2x21 CONTROL BITS /SIGNALS (1) PIN NAME (P(1.x) x FUNCTION P1DIR.x P1SEL.x USIP.x JTAG Mode SDI/SDA/ 7 SDI/SDA X X 1 0 TDO/TDI TDO/TDI X X 0 1 (1) X = don'tcare

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P1.0/T A0CLK/ACLK/A0 P1.1/T A0.0/A1 P1.2/T A0.1/A2 T o Mo d u l e ACLK PxOUT .y DVSS DVCC 1 Bus Keeper EN PxIN.y PxSEL.y PxREN.y INC Hx T o ADC1 0 PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Input 1: Output PxDIR.y PxSEL.y ADC10AE0.y MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 PortP1 Pin Schematic:P1.0toP1.2,Input/OutputWith SchmittTrigger– MSP430G2x31 Table18.PortP1 (P1.0toP1.2)Pin Functions– MSP430G2x31 CONTROL BITS /SIGNALS (1) P1.0/ P1.x(I/O) I:0;O: 1 0 0 TA0CLK/ TA0.TACLK 0 1 0 ACLK/ ACLK 1 1 0 A0 A0 X X 1 (y= 0) P1.1/ P1.x(I/O) I:0;O: 1 0 0 TA0.0/ TA0.0 1 1 0 TA0.CCI0A 0 1 0 A1 A1 X X 1 (y= 1) P1.2/ P1.x(I/O) I:0;O: 1 0 0 TA0.1/ TA0.1 1 1 0 TA0.CCI1A 0 1 0 A2/ A2 X X 1 (y= 2) (1) X = don'tcare Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37

PxOUT.y DVSS DVCC 1 Bus Keeper EN PxIN.y EN D PxSEL.y PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Input 1: Output PxDIR.y PxSEL.y P1.3/ADC10CLK/A3/VREF-/VEREF- INCHx = y To ADC10 To ADC10 VREF- 1

0 VSS

ADC10AE0.y MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com PortP1 Pin Schematic:P1.3,Input/OutputWith SchmittTrigger– MSP430G2x31 Table19.PortP1 (P1.3)Pin Functions– MSP430G2x31 CONTROL BITS /SIGNALS (1) P1.3/ P1.x(I/O) I:0;O: 1 0 0 ADC10CLK/ ADC10CLK 1 1 0 A3/ 3 A3 X X 1 (y= 3) VREF-/ VREF- X X 1 VEREF- VEREF- X X 1 (1) X = don'tcare

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PxOUT .y DVSS DVCC 1 Bus Keeper EN PxIN.y PxSEL.y PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Input 1: Output PxDIR.y PxSEL.y P1.4/SMCLK /A4/V REF+/VE REF+/TCK INCHx = y T o A D C1 0 T o AD C10 V REF+ ADC10AE0.y From JT AG T o J T A G MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 PortP1 Pin Schematic:P1.4,Input/OutputWith SchmittTrigger– MSP430G2x31 Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39

P1.5/T A0.0/A5/TMS T o Module From Module PxOUT .y DVSS DVCC 1 PxIN.y PxSEL.y PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Input 1: Output PxDIR.y PxSEL.y From JTAG T o J T A G INCHx T o ADC1 0 ADC10AE0.y MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com Table20.PortP1 (P1.4)Pin Functions– MSP430G2x31 CONTROL BITS /SIGNALS (1) SMCLK/ SMCLK 1 1 0 0 A4/ A4 X X 1 (y= 4) 0 VREF+/ VREF+ X X 1 0 VEREF+/ VEREF+ X X 1 0 TCK TCK X X 0 1 (1) X = don'tcare PortP1 Pin Schematic:P1.5,Input/OutputWith SchmittTrigger– MSP430G2x31

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P1.6/T A0.1/SDO/SCL/A6/TDI T o Module From US I PxOUT . y DVSS DVCC 1 PxIN.y PxSEL.y or USI P E6 PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Inpu t 1: Output PxDIR.y USIPE6 From JT AG T o J T AG INCHx T o ADC1 0 ADC10AE0.y from USI PxSEL.y USI in I2C mode: Output driver drives low level only . Driver i s disa bled in JT AG mode. MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 Table21.PortP1 (P1.5)Pin Functions-MSP430G2x31 CONTROL BITS /SIGNALS (1) TA0.0/ TA0.0 1 1 0 0 0 A5/ 5 A5 X X X 1 (y= 5) 0 SCLK/ SCLK X X 1 0 0 TMS TMS X X 0 0 1 (1) X = don'tcare PortP1 Pin Schematic:P1.6,Input/OutputWith SchmittTrigger– MSP430G2x31 Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41

SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com Table22.PortP1 (P1.6)Pin Functions-MSP430G2x31 CONTROL BITS /SIGNALS (1) TA0.1/ TA0.1 1 1 0 0 0 TA0.CCR1B 0 1 0 0 0 A6/ A6 X X 0 1 (y= 6) 0 SDO/ SDO X X 1 0 0 TDI/TCLK TDI/TCLK X X 0 0 1 (1) X = don'tcare

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P1.7/ S DI/SDA/A7/TDO/TDI T o Module From US I PxOUT .y DVSS DVCC 1 PxIN.y PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Input 1: Output PxDIR.y USIPE7 From JTAG T o J T A G INC Hx T o ADC1 0 ADC10AE0.y from USI PxSEL.y PxSEL.y or USI P E7 PxSEL.y From JTAG T o J T A G US I in I2C mode: Output driver drives low level only . Driver i s disa bled in JTAG mode. MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 PortP1 Pin Schematic:P1.7,Input/OutputWith SchmittTrigger– MSP430G2x31 Table23.PortP1 (P1.7)Pin Functions– MSP430G2x31 CONTROL BITS /SIGNALS (1) A7/ A7 X X 0 1 (y= 7) 0 SDI/SDO SDI/SDO X X 1 0 0 TDO/TDI TDO/TDI X X 0 0 1 (1) X = don'tcare Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43

XI N/P2.6/T A0 .1 XOUT/P2.7 LF off LFXT1CLK PxSEL.6 PxSEL.7 BC SCTL3.L FX T1Sx = 1 1 T o Module from Module PxOUT . y DVSS DVCC 1 Bus Keeper EN PxIN.y PxSEL.6 PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Input 1: Output PxDIR.y PxSEL.6 MSP430G2x31 MSP430G2x21 SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com PortP2 Pin Schematic:P2.6,Input/OutputWith SchmittTrigger– MSP430G2x21 and MSP430G2x31 Table24.PortP2 (P2.6)Pin Functions– MSP430G2x21 and MSP430G2x31 CONTROL BITS /SIGNALS (1) PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL.6 P2SEL.7 XIN XIN 0 1 1 P2.6 6 P2.x(I/O) I:0;O: 1 0 X TA0.1 TA0.1(2) 1 1 X (1) X = don'tcare (2) BCSCTL3.LFXT1Sx = 11 isrequired.

XIN/P2 .6/TA0.1 XOUT/P2.7 LF off LFXT1CLK PxSEL.6 PxSEL.7 BC SCTL3 .LFX T1 Sx = 1 1 T o Module from Module PxOUT.y DVSS DVCC 1 Bus Keeper EN PxIN.y PxSEL.7 PxREN.y PxIRQ.y PxIE.y EN Set Q Interrupt Edge Select PxSEL.y PxIES.y PxIFG.y Direction 0: Inpu t 1: Output PxDIR.y PxSEL.7 from P2.6/XIN MSP430G2x31 MSP430G2x21 www.ti.com SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 PortP2 Pin Schematic:P2.7,Input/OutputWith SchmittTrigger– MSP430G2x21 and MSP430G2x31 Table25.PortP2 (P2.7)Pin Functions– MSP430G2x21 and MSP430G2x31 CONTROL BITS /SIGNALS (1) PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL.6 P2SEL.7 XOUT XOUT 1 1 1 P2.7 P2.x(I/O) I:0;O: 1 X 0 (1) X = don'tcare Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45

SLAS694J –FEBRUARY 2010–REVISED FEBRUARY 2013 www.ti.com

REVISION HISTORY

SLAS694 LimitedProductPreviewrelease Updated ProductPreviewrelease.SLAS694A Changes throughoutforsampling. SLAS694B Updated ProductPreviewrelease SLAS694C ProductionData release Updated Table12,Table15,Table16,Table17,Table19,Table20,Table21,Table24,Table25.SLAS694D Updated Table20,Table21,Table24.SLAS694E Updated MSP430G2x31 portschematics:P1.3,P1.4. CorrectedTA0.1 signaldescriptioninTable2. Added ADC10SA registertoTable11. SLAS694F Added ADC10DTC1 and ADC10DTC0 registerstoTable12. CorrectedcontrolbitsinTable13. CorrectedcontrolbitsinTable25. SLAS694G Changed Tstg,Programmed device,to-40°C to150°C inAbsoluteMaximum Ratings. Changed Tstg,Programmed device,to-55°C to150°C inAbsoluteMaximum Ratings.SLAS694H Changed fSYSTEM MAX atVCC = 1.8V from4.15to6 MHz inRecommended OperatingConditions. SLAS694I Correctedallportschematics(addedbufferafterPxOUT.y mux) inAPPLICATION INFORMATION Recommended OperatingConditions,Added testconditionsfortypicalvalues.SLAS694J POR, BOR ,Added note(2).

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) M430G2221IRSA16RG4 Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2221 M430G2221IRSA16RG4.A Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2221 M430G2221IRSA16RG4.B Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2221 MSP430G2121IN14 Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2121 MSP430G2121IN14.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2121 MSP430G2121IN14.B Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2121 MSP430G2121IPW14 Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2121 MSP430G2121IPW14.A Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2121 MSP430G2121IPW14.B Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2121 MSP430G2121IPW14R Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2121 MSP430G2121IPW14R.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2121 MSP430G2121IPW14R.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2121 MSP430G2121IRSA16R Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 M430G 2121 MSP430G2121IRSA16R.A Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2121 MSP430G2121IRSA16R.B Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2121 MSP430G2121IRSA16T Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 M430G 2121 MSP430G2121IRSA16T.A Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2121 MSP430G2121IRSA16T.B Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2121 MSP430G2131IN14 Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2131 MSP430G2131IN14.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2131 MSP430G2131IN14.B Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2131 MSP430G2131IPW14 Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2131 Addendum-Page 1

www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) MSP430G2131IPW14.A Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2131 MSP430G2131IPW14.B Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2131 MSP430G2131IPW14R Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2131 MSP430G2131IPW14R.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2131 MSP430G2131IPW14R.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2131 MSP430G2131IRSA16R Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 M430G 2131 MSP430G2131IRSA16R.A Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2131 MSP430G2131IRSA16R.B Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2131 MSP430G2131IRSA16T Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 M430G 2131 MSP430G2131IRSA16T.A Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2131 MSP430G2131IRSA16T.B Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2131 MSP430G2221IN14 Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2221 MSP430G2221IN14.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2221 MSP430G2221IN14.B Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2221 MSP430G2221IPW14 Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2221 MSP430G2221IPW14.A Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2221 MSP430G2221IPW14.B Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2221 MSP430G2221IPW14R Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2221 MSP430G2221IPW14R.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2221 MSP430G2221IPW14R.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2221 MSP430G2221IRSA16R Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 M430G 2221 MSP430G2221IRSA16R.A Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2221 MSP430G2221IRSA16R.B Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2221 Addendum-Page 2

www.ti.com 7-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) MSP430G2221IRSA16T Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 M430G 2221 MSP430G2221IRSA16T.A Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2221 MSP430G2221IRSA16T.B Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2221 MSP430G2231IN14 Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2231 MSP430G2231IN14.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2231 MSP430G2231IN14.B Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 MSP430G2231 MSP430G2231IPW14 Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2231 MSP430G2231IPW14.A Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2231 MSP430G2231IPW14.B Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2231 MSP430G2231IPW14R Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2231 MSP430G2231IPW14R.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2231 MSP430G2231IPW14R.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 G2231 MSP430G2231IRSA16R Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 M430G 2231 MSP430G2231IRSA16R.A Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 M430G 2231 MSP430G2231IRSA16R.B Active Production QFN (RSA) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 M430G 2231 MSP430G2231IRSA16T Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 M430G 2231 MSP430G2231IRSA16T.A Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2231 MSP430G2231IRSA16T.B Active Production QFN (RSA) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 M430G 2231 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. Addendum-Page 3

www.ti.com 7-Oct-2025 (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF MSP430G2231 :

Automotive : MSP430G2231-Q1
Enhanced Product : MSP430G2231-EP NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) M430G2221IRSA16RG4 QFN RSA 16 3000 346.0 346.0 33.0 MSP430G2121IPW14R TSSOP PW 14 2000 353.0 353.0 32.0 MSP430G2121IRSA16R QFN RSA 16 3000 367.0 367.0 35.0 MSP430G2121IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2131IPW14R TSSOP PW 14 2000 353.0 353.0 32.0 MSP430G2131IRSA16R QFN RSA 16 3000 346.0 346.0 33.0 MSP430G2131IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2221IPW14R TSSOP PW 14 2000 353.0 353.0 32.0 MSP430G2221IRSA16R QFN RSA 16 3000 346.0 346.0 33.0 MSP430G2221IRSA16T QFN RSA 16 250 210.0 185.0 35.0 MSP430G2231IPW14R TSSOP PW 14 2000 353.0 353.0 32.0 MSP430G2231IRSA16R QFN RSA 16 3000 346.0 346.0 33.0 MSP430G2231IRSA16T QFN RSA 16 250 210.0 185.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) MSP430G2121IN14 N PDIP 14 25 506 13.97 11230 4.32 MSP430G2121IN14.A N PDIP 14 25 506 13.97 11230 4.32 MSP430G2121IN14.B N PDIP 14 25 506 13.97 11230 4.32 MSP430G2121IPW14 PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2121IPW14 PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2121IPW14.A PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2121IPW14.A PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2121IPW14.B PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2121IPW14.B PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2131IN14 N PDIP 14 25 506 13.97 11230 4.32 MSP430G2131IN14.A N PDIP 14 25 506 13.97 11230 4.32 MSP430G2131IN14.B N PDIP 14 25 506 13.97 11230 4.32 MSP430G2131IPW14 PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2131IPW14 PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2131IPW14.A PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2131IPW14.A PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2131IPW14.B PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2131IPW14.B PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2221IN14 N PDIP 14 25 506 13.97 11230 4.32 MSP430G2221IN14.A N PDIP 14 25 506 13.97 11230 4.32 MSP430G2221IN14.B N PDIP 14 25 506 13.97 11230 4.32 MSP430G2221IPW14 PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2221IPW14 PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2221IPW14.A PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2221IPW14.A PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2221IPW14.B PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2221IPW14.B PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2231IN14 N PDIP 14 25 506 13.97 11230 4.32 MSP430G2231IN14.A N PDIP 14 25 506 13.97 11230 4.32 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2025 Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) MSP430G2231IN14.B N PDIP 14 25 506 13.97 11230 4.32 MSP430G2231IPW14 PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2231IPW14 PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2231IPW14.A PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2231IPW14.A PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2231IPW14.B PW TSSOP 14 90 530 10.2 3600 3.5 MSP430G2231IPW14.B PW TSSOP 14 90 530 10.2 3600 3.5 Pack Materials-Page 4

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRSA 16 PLASTIC QUAD FLATPACK - NO LEAD4 x 4, 0.65 mm pitch 4230969/A

www.ti.com PACKAGE OUTLINE C 16X 0.38 0.23 2.7 0.1 16X 0.5 0.3 1.0 0.8 (0.2) TYP 0.05 0.00 12X 0.65 1.95 A 4.1 3.9 B 4.1 3.9 VQFN - 1 mm max heightRSA0016B PLASTIC QUAD FLATPACK - NO LEAD 4219093/A 08/2021 PIN 1 INDEX AREA 0.08 SEATING PLANE 5 8 16 13 X 0.3)(45 PIN 1 ID 0.1 C A B 0.05 C EXPOSED THERMAL PAD SYMM

17 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. Reference JEDEC registration MO-220. SCALE 3.300

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

16X (0.31) 16X (0.6) ( 0.2) TYP VIA 12X (0.65) (3.8) (3.8) (1.1) ( 2.7) (R0.05) TYP (1.1) VQFN - 1 mm max heightRSA0016B PLASTIC QUAD FLATPACK - NO LEAD 4219093/A 08/2021 SYMM 5 8 1316 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 16X (0.6) 16X (0.31) 12X (0.65) (3.8) (3.8) 4X ( 1.19) (0.695) TYP (0.695) TYP (R0.05) TYP VQFN - 1 mm max heightRSA0016B PLASTIC QUAD FLATPACK - NO LEAD 4219093/A 08/2021 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP EXPOSED SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 77% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 5 8 1316

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