MSP430C11X1_16 TI1 | Alldatasheet
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MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low Supply Voltage Range 1.8 V to 3.6 V /C0068Ultralow Power Consumption − Active Mode: 160 μA at 1 MHz, 2.2 V − Standby Mode: 0.7 μA − Off Mode (RAM Retention): 0.1 μA /C0068Wake-Up From Standby Mode in Less Than 6 μs /C006816-Bit RISC Architecture, 125 ns Instruction Cycle Time /C0068Basic Clock Module Configurations: − Various Internal Resistors − Single External Resistor − 32-kHz Crystal − High-Frequency Crystal − Resonator − External Clock Source /C006816-Bit Timer_A With Three Capture/Compare Registers /C0068On-Chip Comparator for Analog Signal Compare Function or Slope Analog-to-Digital (A/D) Conversion /C0068Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse /C0068Family Members Include MSP430C1101: 1KB ROM, 128B RAM MSP430C1111: 2KB ROM, 128B RAM MSP430C1121: 4KB ROM, 256B RAM MSP430F1101A: 1KB + 128B Flash Memory 128B RAM MSP430F1111A: 2KB + 256B Flash Memory 128B RAM MSP430F1121A: 4KB + 256B Flash Memory 256B RAM /C0068Available in a 20-Pin Plastic Small-Outline Wide Body (SOWB) Package, 20-Pin Plastic Small-Outline Thin Package, 20-Pin TVSOP (F11x1A only), and 24-Pin QFN /C0068For Complete Module Descriptions, Refer to the MSP430x1xx Family User’s Guide, Literature Number SLAU049
description
The T exas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 μs. The MSP430x11x1(A) series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, versatile analog comparator and fourteen I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Stand alone radio frequency (RF) sensor front end is another area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection. Please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2008 Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(DW) PLASTIC 20-PIN TSSOP (PW) PLASTIC 20-PIN TVSOP (DGV) PLASTIC 24-PIN QFN (RGE) 40°Ct o8 5°C MSP430C1101IDW MSP430C1111IDW MSP430C1121IDW MSP430C1101IPW MSP430C1111IPW MSP430C1121IPW MSP430F1101AIDGV MSP430F1111AIDGV MSP430C1101IRGE MSP430C1111IRGE MSP430C1121IRGE−40°C to 85°C MSP430C1121IDW MSP430F1101AIDW MSP430F1111AIDW MSP430F1121AIDW MSP430C1121IPW MSP430F1101AIPW MSP430F1111AIPW MSP430F1121AIPW MSP430F1111AIDGV MSP430F1121AIDGV MSP430C1121IRGE MSP430F1101AIRGE MSP430F1111AIRGE MSP430F1121AIRGE
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RGE PACKAGE (TOP VIEW) TEST VCC P2.5/Rosc VSS XOUT XIN RST/NMI P2.0/ACLK P2.1/INCLK P2.2/CAOUT/TA0 P1.7/TA2/TDO/TDI P1.6/TA1/TDI/TCLK P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/CA1/TA2 P2.3/CA0/TA1 DW, PW, or DGV PACKAGE (TOP VIEW) VSS P2.5/ROSC XOUT VCC XIN TEST RST/NMI P1.7/TA2/TDO/TDI P2.0/ACLK P1.6/TA1/TDI/TCLK NC NC P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P1.5/TA0/TMS Note: NC pins not internally connected P2.1/INCLK P2.2/CAOUT/TA0 NC P2.3/CA0/TA1 P2.4/CA1/TA2 NC 1389 1 0 1 1 20 21 22 23 Power Pad connection to V SS recommended functional block diagram Oscillator ACLK SMCLK CPU Incl. 16 Reg. Bus Conv MCB XIN XOUT P2 MDB, 16 Bit MAB, 16 Bit MCLK MAB,
4 Bit
Timer_A3
3 CC Reg
8 I/Os, with
6 I/Os, with
MDB, 16-Bit MAB, 16-Bit TEST Test JTAG 8 6 Comparator A MDB, 8 Bit Emulation Module (F versions only)
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
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NO. DESCRIPTIONNAME DW, PW, OR DGV RGE I/O DESCRIPTION P1.0/TACLK 13 13 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 14 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit P1.2/TA1 15 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 16 16 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK/TCK 17 17 I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming and test P1.5/TA0/TMS 18 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for device programming and test P1.6/TA1/TDI/TCLK 19 20 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input or test clock input P1.7/TA2/TDO/TDI† 20 21 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input during programming P2.0/ACLK 8 6 I/O General-purpose digital I/O pin/ACLK output P2.1/INCLK 9 7 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK P2.2/CAOUT/TA0 10 8 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/ comparator_A, output/BSL receive P2.3/CA0/TA1 11 10 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/ comparator_A, input P2.4/CA1/TA2 12 11 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/ comparator_A, input P2.5/ROSC 3 24 I/O General-purpose digital I/O pin/input for external resistor that defines the DCO nominal frequency RST/NMI 7 5 I Reset or nonmaskable interrupt input TEST 1 22 I Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. VCC 2 23 Supply voltage VSS 4 2 Ground reference XIN 6 4 I Input terminal of crystal oscillator XOUT 5 3 O Output terminal of crystal oscillator QFN Pad NA Package Pad NA QFN package pad connection to VSS recommended. † TDO or TDI is selected via JTAG instruction.
instruction can operate on word and byte data. Table 1. Instruction Word Formats Table 2. Address Mode Descriptions
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
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The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: /C0068Active mode (AM) − All clocks are active. /C0068Low-power mode 0 (LPM0) − CPU is disabled. − ACLK and SMCLK remain active. MCLK is disabled. /C0068Low-power mode 1 (LPM1) − CPU is disabled. − ACLK and SMCLK remain active. MCLK is disabled. − DCO’s dc generator is disabled if DCO not used in active mode. /C0068Low-power mode 2 (LPM2) − CPU is disabled. − MCLK and SMCLK are disabled. − DCO’s dc generator remains enabled. − ACLK remains active. /C0068Low-power mode 3 (LPM3) − CPU is disabled. − MCLK and SMCLK are disabled. − DCO’s dc generator is disabled. − ACLK remains active. /C0068Low-power mode 4 (LPM4) − CPU is disabled. − ACLK is disabled. − MCLK and SMCLK are disabled. − DCO’s dc generator is disabled. − Crystal oscillator is stopped.
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset Watchdog Flash Memory WDTIFG KEYV (see Note 1) Reset 0FFFEh 15, highest NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG (see Notes 1 and 4) (non)-maskable, (non)-maskable, (non)-maskable 0FFFCh 14 0FFFAh 13 0FFF8h 12 Comparator_A CAIFG maskable 0FFF6h 11 Watchdog Timer WDTIFG maskable 0FFF4h 10 Timer_A3 TACCR0 CCIFG (see Note 2) maskable 0FFF2h 9 Timer_A3 TACCR1 CCIFG. TACCR2 CCIFG TAIFG (see Notes 1 and 2) maskable 0FFF0h 8 0FFEEh 7 0FFECh 6 0FFEAh 5 0FFE8h 4 I/O Port P2 (eight flags; see Note 3) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) maskable 0FFE6h 3 I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) maskable 0FFE4h 2 0FFE2h 1 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module 3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) implemented on the ’C11x1 and ’F11x1A devices. 4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
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special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 76 54 0 OFIE WDTIE 32 1 rw-0 rw-0 rw-0 Address 0h NMIIEACCVIE rw-0 WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. OFIE: Oscillator fault enable NMIIE: (Non)maskable interrupt enable ACCVIE: Flash access violation interrupt enable 76 54 032 1Address 01h interrupt flag register 1 and 2 76 54 0 OFIFG WDTIFG 32 1 rw-0 rw-1 rw-(0) Address 02h NMIIFG WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power up or a reset condition at RST/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST /NMI pin 76 54 032 1Address 03h Legend rw: rw-0,1: Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR.rw-(0,1): SFR bit is not present in device
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 memory organization MSP430C1101 MSP430C1111 MSP430C1121 Memory Main: interrupt vector Main: code memory Size ROM ROM 1KB ROM 0FFFFh−0FFE0h 0FFFFh−0FC00h 2KB ROM 0FFFFh−0FFE0h 0FFFFh−0F800h 4KB ROM 0FFFFh−0FFE0h 0FFFFh−0F000h Information memory Size Flash Not applicable Not applicable Not applicable Boot memory Size ROM Not applicable Not applicable Not applicable RAM Size 128 Byte 027Fh − 0200h
128 Byte
027Fh − 0200h
256 Byte
02FFh − 0200h Peripherals 16-bit 8-bit 8-bit SFR 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h MSP430F1101A MSP430F1111A MSP430F1121A Memory Main: interrupt vector Main: code memory Size Flash Flash 1KB Flash 0FFFFh−0FFE0h 0FFFFh−0FC00h 2KB Flash 0FFFFh−0FFE0h 0FFFFh−0F800h 4KB Flash 0FFFFh−0FFE0h 0FFFFh−0F000h Information memory Size Flash 010FFh − 01080h 010FFh − 01000h 010FFh − 01000h Boot memory Size ROM 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h 1KB 0FFFh − 0C00h RAM Size 128 Byte 027Fh − 0200h 027Fh − 0200h 02FFh − 0200h Peripherals 16-bit 8-bit 8-bit SFR 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h 01FFh − 0100h 0FFh − 010h 0Fh − 00h bootstrap loader (BSL) The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089. BSL FUNCTION DW, PW, AND DGV PACKAGE PINS RGE PACKAGE PINS Data Transmit 14 - P1.1 14 - P1.1 Data Receive 10 - P2.2 8 - P2.2
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
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The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: /C0068Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. /C0068Segments 0 to n may be erased in one step, or each segment may be individually erased. /C0068Segments A and B can be erased individually, or as a group with segments 0 to n. Segments A and B are also called information memory. /C0068New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. Segment0 w/ Interrupt Vectors 0FFFFh 0FE00h Information Memory Flash Main Memory Segment1 Segment2 Segment3 Segment4 Segment5 Segment6 Segment7 SegmentA SegmentB 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 0F800h 0F7FFh 0F600h 0F5FFh 0F400h 0F3FFh 0F200h 0F1FFh 0F000h 010FFh 01080h 0107Fh 01000h NOTE: All segments not implemented on all devices.
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number SLAU049. oscillator and system clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The basic clock module provides the following clock signals: /C0068Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal /C0068Main clock (MCLK), the system clock used by the CPU /C0068Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules digital I/O There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external pins): /C0068All individual I/O bits are independently programmable. /C0068Any combination of input, output, and interrupt conditions is possible. /C0068Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of port P2. /C0068Read/write access to port-control registers is supported by all instructions. NOTE: Only six bits of port P2 (P2.0 to P2.5) are available on external pins, but all control and data bits for port P2 are implemented. watchdog timer (WDT) The primary function of the WDT module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. Comparator_A The primary function of the Comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_A3 SIGNAL CONNECTIONS INPUT PIN NUMBER DEVICE INPUT MODULE MODULE MODULE OUTPUT OUTPUT PIN NUMBER DW, PW, DGV RGE DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK OUTPUT SIGNAL DW, PW, DGV RGE 13 - P1.0 13 - P1.0 TACLK TACLK ACLK ACLK Timer NASMCLK SMCLK Timer NA 9 - P2.1 7 - P2.1 INCLK INCLK 14 - P1.1 14 - P1.1 TA0 CCI0A 14 - P1.1 14 - P1.1 10 - P2.2 8 - P2.2 TA0 CCI0B CCR0 TA0 18 - P1.5 18 - P1.5 VSS GND CCR0 TA0 VCC VCC 15 - P1.2 15 - P1.2 TA1 CCI1A 11 - P2.3 10 - P2.3 CAOUT (internal) CCI1B CCR1 TA1 15 - P1.2 15 - P1.2 VSS GND CCR1 TA1 19 - P1.6 20 - P1.6 VCC VCC 16 - P1.3 16 - P1.3 TA2 CCI2A 12 - P2.4 11 - P2.4 ACLK (internal) CCI2B CCR2 TA2 16 - P1.3 16 - P1.3 VSS GND CCR2 TA2 20 - P1.7 21 - P1.7 VCC VCC
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 peripheral file map PERIPHERALS WITH WORD ACCESS Timer_A Reserved Reserved Reserved Reserved Capture/compare register Capture/compare register Capture/compare register Timer_A register Reserved Reserved Reserved Reserved Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector TACCR2 TACCR1 TACCR0 TAR TACCTL2 TACCTL1 TACCTL0 TACTL TAIV 017Eh 017Ch 017Ah 0178h 0176h 0174h 0172h 0170h 016Eh 016Ch 016Ah 0168h 0166h 0164h 0162h 0160h 012Eh Flash Memory Flash control 3 Flash control 2 Flash control 1 FCTL3 FCTL2 FCTL1 012Ch 012Ah 0128h Watchdog Watchdog/timer control WDTCTL 0120h PERIPHERALS WITH BYTE ACCESS Comparator_A Comparator_A port disable Comparator_A control 2 Comparator_A control 1 CAPD CACTL2 CACTL1 05Bh 05Ah 059h Basic Clock Basic clock system control 2 Basic clock system control 1 DCO clock frequency control BCSCTL2 BCSCTL1 DCOCTL 058h 057h 056h Port P2 Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h Port P1 Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 026h 025h 024h 023h 022h 021h 020h Special Function SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 IFG2 IFG1 IE2 IE1 003h 002h 001h 000h
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implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. to the TEST pin when blowing the JTAG fuse. XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8 MHz at VCC ≥ 2.8 V.
- In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
4.15 MHz
8.0 MHz
Figure 1. Frequency vs Supply Voltage
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current (into VCC) excluding external current PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT TA = −40°C to 85°C, f f 1 MHz
2.2 V 160 200
f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz 3 V 240 300C11x1 TA = −40°C to 85°C, 2.2 V 1.3 2TA = 40 C to 85 C, f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz 3 V 2.5 3.2 I(AM) Active mode TA = −40°C to 85°C, fMCLK = f(SMCLK) = 1 MHz, 2.2 V 200 250 μA F11x1A fMCLK = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz, Program executes in flash 3 V 300 350F11x1A TA = −40°C to 85°C, Program executes in flash
2.2 V 3 5
f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz 3 V 11 18 C11x1 TA = −40°C to 85°C, f 0f 1 MHz
2.2 V 30 40
C11x1 f(MCLK) = 0, f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz 3 V 51 60 μAI(CPUOff) Low power mode (LPM0) F11x1A TA = −40°C to 85°C, f 0f 1 MHz
2.2 V 32 45
μA F11x1A f(MCLK) = 0, f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz 3 V 55 70 I Low power mode (LPM2) TA = −40°C to 85°C, f f 0 MHz
2.2 V 11 14
μAI(LPM2) Low-power mode (LPM2) f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 0 3 V 17 22 μA C11x1 TA = −40°C to 85°C, f f 0 MHz 2.2 V 1.2 1.7 C11x1 f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 3 V 2 2.7 Low power mode TA = −40°C 0.8 1.2 I(LPM3) Low-power mode (LPM3) TA = 25°C f(MCLK) = 0 MHz 2.2 V 0.7 1 μAI(LPM3) (LPM3) F11x1A TA = 85°C f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, 1.6 2.3 μA F11x1A TA = −40°C f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 1 1.8 2.2 TA = 25°C (ACLK) SCG0 = 1 3 V 1.6 1.9 TA = 85°C 2.3 3.4 TA = −40°C 0.1 0.5 C11x1 TA = 25°C 2.2 V/3 V 0.1 0.5 I Low-power mode TA = 85°C f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz 0.4 0.8 μAI(LPM4) Low power mode (LPM4) TA = −40°C f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 0.1 0.5 μA F11x1A TA = 25°C f(ACLK) = 0 Hz, SCG0 = 1 2.2 V/3 V 0.1 0.5 TA = 85°C 0.8 1.9 NOTE: All inputs are tied to 0 V or V CC. Outputs do not source or sink any current. current consumption of active mode versus system frequency, C version, F version IAM = IAM[1 MHz] × fsystem [MHz] current consumption of active mode versus supply voltage, C version IAM = IAM[3 V] + 105 μA/V × (VCC−3 V) current consumption of active mode versus supply voltage, F version IAM = IAM[3 V] + 120 μA/V × (VCC−3 V)
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs − Ports P1 (P1.0 to P1.7) and P2 (P2.0 to P2.5) PARAMETER VCC MIN TYP MAX UNIT V Positive going input threshold voltage 2.2 V 1.1 1.5 VVIT+ Positive-going input threshold voltage 3 V 1.5 1.9 V V Negative going input threshold voltage 2.2 V 0.4 0.9 VVIT− Negative-going input threshold voltage 3 V 0.9 1.3 V V Input voltage hysteresis (V V ) 2.2 V 0.3 1.1 VVhys Input voltage hysteresis (VIT+ − VIT−) 3 V 0.5 1 V standard inputs − RST/NMI, JTAG (TCK, TMS, TDI/TCLK) PARAMETER VCC MIN TYP MAX UNIT VIL Low-level input voltage 22V/3V VSS VSS+0.6 V VIH High-level input voltage
2.2 V / 3 V
0.8×VCC VCC V inputs Px.x, TAx PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT P t P1 P2 P1 t P2 E t l t i i l 2.2 V/3 V 1.5 cycle t(int) External interrupt timing Port P1, P2: P1.x to P2.x, External trigger signal for the interrupt flag (see Note 1) 2.2 V 62 ns(int) pg for the interrupt flag (see Note 1)
3 V 50
t() Timer A capture timing TA0 TA1 TA2
2.2 V 62
nst(cap) Timer_A, capture timing TA0, TA1, TA2 f Timer_A clock frequency TACLK INCLK t =t
2.2 V 8
MHzf(TAext) Timer_A clock frequency externally applied to pin TACLK, INCLK t(H) = t(L) 3 V 10 MHz f Timer A clock frequency SMCLK or ACLK signal selected MHzf(TAint) Timer_A clock frequency SMCLK or ACLK signal selected
3 V 10
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles. leakage current PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT I High impedance leakage current Port P1: P1.x, 0 ≤ ×≤ 7 (see Notes 1 and 2) 2.2 V/3 V ±50 nAIlkg(Px.x) High-impedance leakage current Port P2: P2.x, 0 ≤ ×≤ 5 (see Notes 1 and 2) 2.2 V/3 V ±50 nA NOTES: 1. The leakage current is measured with V SS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1 (P1.0 to P1.7) and P2 (P2.0 to P2.5) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(OHmax) = −1.5 mA V 22V See Note 1 VCC−0.25 VCC V High-level output voltage Port 1 and Port 2 (C11x1) I(OHmax) = −6 mA VCC = 2.2 V See Note 2 VCC−0.6 VCC VVOH Port 1 and Port 2 (C11x1) Port 1 (F11x1A) I(OHmax) = −1.5 mA V 3V See Note 1 VCC−0.25 VCC V Port 1 (F11x1A) I(OHmax) = −6 mA VCC = 3 V See Note 2 VCC−0.6 VCC I(OHmax) = −1 mA V 22V See Note 3 VCC−0.25 VCC V High-level output voltage I(OHmax) = −3.4 mA VCC = 2.2 V See Note 3 VCC−0.6 VCC VVOH High level output voltage Port 2 (F11x1A) I(OHmax) = −1 mA V 3V See Note 3 VCC−0.25 VCC V I(OHmax) = −3.4 mA VCC = 3 V See Note 3 VCC−0.6 VCC I(OLmax) = 1.5 mA V 22V See Note 1 VSS VSS+0.25 V Low-level output voltage Port 1 and Port 2 (C11x1 I(OLmax) = 6 mA VCC = 2.2 V See Note 2 VSS VSS+0.6 VVOL Port 1 and Port 2 (C11x1, F11x1A ) I(OLmax) = 1.5 mA V =3V See Note 1 VSS VSS+0.25 V F11x1A) I(OLmax) = 6 mA VCC = 3 V See Note 2 VSS VSS+0.6 NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop specified. 2. The maximum total current, I OHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. 3. One output loaded at a time. output frequency PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fP20 P2.0/ACLK, CL = 20 pF 2.2 V/3 V fSystem fTAx Output frequency TA0, TA1, TA2, CL = 20 pF Internal clock source, SMCLK signal applied (see Note 1) 2.2 V/3 V dc fSystem MHz fSMCLK = fLFXT1 = fXT1 40% 60% P1 4/SMCLK fSMCLK = fLFXT1 = fLF 2 2 V/3 V 35% 65% P1.4/SMCLK, CL = 20 pF fSMCLK = fLFXT1/n
2.2 V/3 V
50%− 15 ns 50% 50%+ 15 ns tXdc Duty cycle of O/P frequency fSMCLK = fDCOCLK 2.2 V/3 V 50%− 15 ns 50% 50%+ 15 nsfrequency P2 0/ACLK fP20 = fLFXT1 = fXT1 40% 60% P2.0/ACLK, CL =2 0p F fP20 = fLFXT1 = fLF 2.2 V/3 V 30% 70%CL = 20 pF fP20 = fLFXT1/n 50% tTAdc TA0, TA1, TA2, CL = 20 pF, duty cycle = 50% 2.2 V/3 V 0 ±50 ns NOTE 1: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1 and P2 (continued) Figure 2 VOL − Low-Level Output Voltage − V VCC = 2.2 V P1.0 TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TA = 25°C TA = 85°C OLI − Typical Low-Level Output Current − mA Figure 3 VOL − Low-Level Output Voltage − V VCC = 3 V P1.0 TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TA = 25°C TA = 85°C OLI − Typical Low-Level Output Current − mA Figure 4 VOH − High-Level Output Voltage − V −14 −12 −10 VCC = 2.2 V P1.0 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TA = 25°C TA = 85°C OHI − Typical High-Level Output Current − mA Figure 5 VOH − High-Level Output Voltage − V −30 −25 −20 −15 −10 VCC = 3 V P1.0 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TA = 25°C TA = 85°C OHI − Typical High-Level Output Current − mA NOTE: One output loaded at a time.
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) optional resistors, individually programmable with ROM code (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R(opt1) 2.5 5 10 kΩ R(opt2) 3.8 7.7 15 kΩ R(opt3) 7.6 15 31 kΩ R(opt4) 11.5 23 46 kΩ R(opt5) Resistors, individually programmable with ROM code, all port pins, V 2 2 V/3 V 23 45 90 kΩ R(opt6) Resistors, individually programmable with ROM code, all port pins, values applicable for pulldown and pullup VCC = 2.2 V/3 V 46 90 180 kΩ R(opt7) 70 140 280 kΩ R(opt8) 115 230 460 kΩ R(opt9) 160 320 640 kΩ R(opt10) 205 420 830 kΩ NOTE 1: Optional resistors R optx for pulldown or pullup are not available in standard flash memory device MSP430F11x1A. wake-up from low-power modes (LPMx) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(LPM0) VCC = 2.2 V/3 V 100 nst(LPM2) VCC = 2.2 V/3 V 100 ns f(MCLK) = 1 MHz, VCC = 2.2 V/3 V 6 t(LPM3) Delay time (see Note 1) f(MCLK) = 2 MHz, VCC = 2.2 V/3 V 6 μs(LPM3) Delay time (see Note 1) f(MCLK) = 3 MHz, VCC = 2.2 V/3 V 6 μ f(MCLK) = 1 MHz, VCC = 2.2 V/3 V 6 t(LPM4) f(MCLK) = 2 MHz, VCC = 2.2 V/3 V 6 μs(LPM4) f(MCLK) = 3 MHz, VCC = 2.2 V/3 V 6 μ NOTE 1: Parameter applicable only if DCOCLK is used for MCLK. RAM PARAMETER MIN TYP MAX UNIT V(RAMh) CPU halted (see Note 1) 1.6 V NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program execution should happen during this supply voltage condition.
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Comparator_A (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I CAON=1 CARSEL=0 CAREF=0 VCC = 2.2 V 25 40 μAI(DD) CAON=1, CARSEL=0, CAREF=0 VCC = 3 V 45 60 μA I CAON=1, CARSEL=0, CAREF 1/2/3 no load at VCC = 2.2 V 30 50 μAI(Refladder/RefDiode) CAREF=1/2/3, no load at P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC = 3 V 45 71 μA V(IC) Common-mode input voltage CAON =1 VCC = 2.2 V/3 V 0 VCC−1 V V(Ref025) Voltage @ 0.25 VCC node VCC PCA0=1, CARSEL=1, CAREF=1, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC = 2.2 V/3 V 0.23 0.24 0.25 V(Ref050) Voltage @ 0.5VCC node VCC PCA0=1, CARSEL=1, CAREF=2, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC = 2.2 V/3 V 0.47 0.48 0.5 V (see Figure 6 and Figure 7) PCA0=1, CARSEL=1, CAREF=3, No load at P2 3/CA0/TA1 and VCC = 2.2 V 390 480 540 mVV(RefVT) (see Figure 6 and Figure 7) No load at P2.3/CA0/TA1 and P2.4/CA1/TA2, T A = 85°C VCC = 3 V 400 490 550 mV V(offset) Offset voltage See Note 2 VCC = 2.2 V/3 V −30 30 mV Vhys Input hysteresis CAON=1 VCC = 2.2 V/3 V 0 0.7 1.4 mV TA = 25°C, Overdrive 10 mV, VCC = 2.2 V 160 210 300 ns t TA = 25 C, Overdrive 10 mV, Without filter: CAF=0 VCC = 3 V 90 150 240 ns t(response LH) TA = 25°C, Overdrive 10 mV, VCC = 2.2 V 1.4 1.9 3.4 μsTA = 25 C, Overdrive 10 mV, With filter: CAF=1 VCC = 3 V 0.9 1.5 2.6 μs TA = 25°C, Overdrive 10 mV, VCC = 2.2 V 130 210 300 ns t TA = 25 C, Overdrive 10 mV, Without filter: CAF=0 VCC = 3 V 80 150 240 ns t(response HL) TA = 25°C, Overdrive 10 mV, VCC = 2.2 V 1.4 1.9 3.4 μsTA = 25 C, Overdrive 10 mV, With filter: CAF=1 VCC = 3 V 0.9 1.5 2.6 μs NOTES: 1. The leakage current for the Comparator_A terminals is identical to I lkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NOTES: 1. V CC rise time dV/dt ≥ 1V/ms.
- When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less
than −1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms. Figure 10. Power-On Reset (POR) vs Supply Voltage Figure 11. VPOR vs Temperature
NOTE 1: These parameters are not production tested.
2.2 V 3 V
Figure 12. DCO Characteristics
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics /C0068Individual devices have a minimum and maximum operation frequency. The specified parameters for f(DCOx0) to f(DCOx7) are valid for all devices. /C0068All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7. /C0068DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO. /C0068Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to: faverage /C0043 32 /C0032f(DCO) /C0032f(DCO/C00411) MOD /C0032f(DCO)/C0041(32/C0042MOD) /C0032f(DCO/C00411) DCO when using ROSC (see Note 1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f CO DCO output frequency R =4 D C O=3 M O D=0 D C O R=1 T =2 5°C 2.2 V 1.8±15% MHz fDCO, DCO output frequency Rsel = 4, DCO = 3, MOD = 0, DCOR = 1, TA = 25°C 3 V 1.95±15% MHz Dt, Temperature drift Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V ±0.1 %/°C Dv, Drift with VCC variation Rsel = 4, DCO = 3, MOD = 0, DCOR = 1 2.2 V/3 V 10 %/V crystal oscillator, LFXT1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT C Input capacitance XTS=0, LF mode selected, VCC = 2.2 V / 3 V 12 pFCXIN Input capacitance XTS=1, XT1 mode selected, V CC = 2.2 V / 3 V (see Note 1) 2 pF C Output capacitance XTS=0, LF mode selected, V CC = 2.2 V / 3 V 12 pFCXOUT Output capacitance XTS=1, XT1 mode selected, V CC = 2.2 V / 3 V (see Note 1) 2 pF VIL Input levels at XIN V = 2 2 V/3 V (see Note 2) VSS 0.2×VCC V VIH Input levels at XIN VCC = 2.2 V/3 V (see Note 2) 0.8×VCC VCC V NOTES: 1. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) flash memory PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(PGM/ ERASE) Program and erase supply voltage 2.7 3.6 V fFTG Flash Timing Generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.7 V/ 3.6 V 3 5 mA IERASE Supply current from VCC during erase 2.7 V/ 3.6 V 3 7 mA tCPT Cumulative program time See Note 1 2.7 V/ 3.6 V 4 ms tCMErase Cumulative mass erase time See Note 2 2.7 V/ 3.6 V 200 ms Program/erase endurance 104 105 cycles tRetention Data retention duration TJ = 25°C 100 years tWord Word or byte program time 35 tBlock, 0 Block program time for first byte or word 30 tBlock, 1-63 Block program time for each additional byte or word See Note 3 ttBlock, End Block program end-sequence wait time See Note 3 6 tFTG tMass Erase Mass erase time 5297 tSeg Erase Segment erase time 4819 NOTES: 1. The cum ulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f FTG,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG). JTAG interface PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT f TCK input frequency see Note 1
2.2 V 0 5 MHz
fTCK TCK input frequency see Note 1 3 V 0 10 MHz RInternal Internal pulldown resistance on TEST see Note 2 2.2 V/ 3 V 25 60 90 kΩ NOTES: 1. f TCK may be restricted to meet the timing requirements of the module selected. 2. TEST pull-down resistor implemented in all versions. JTAG fuse (see Note 1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V V Voltage level on TEST for fuse blow (’C11x1) 3.5 3.9 V VFB Voltage level on TEST for fuse blow (’F11x1A) 6 7 V IFB Supply current into TEST during fuse blow 100 mA tFB Time to blow fuse 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation (F versions only) features is possible. The JTAG block is switched to bypass mode.
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
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APPLICATION INFORMATION
Port P1, P1.0 to P1.3, input/output with Schmitt trigger EN D (See Note 1) (See Note 2) (See Note 2) (See Note 1) GND VCC P1.0 − P1.3 Interrupt Edge Select EN Set Q P1IE.x P1IFG.x P1IRQ.x Interrupt Flag P1IES.x P1SEL.x Module X IN P1IN.x P1OUT.x Module X OUT Direction Control From Module P1DIR.x P1SEL.x Pad Logic NOTE: x = Bit/identifier, 0 to 3 for port P1 PnSel.x PnDIR.x Direction control from module † Signal from or to Timer_A NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Port P1, P1.4 to P1.7, input/output with Schmitt trigger and in-system access features EN D See Note 1 See Note 2 See Note 2 See Note 1 GND VCC P1.4−P1.7 Interrupt Edge Select EN Set Q P1IE.x P1IFG.x P1IRQ.x Interrupt Flag P1IES.x P1SEL.x Module X IN P1IN.x P1OUT.x Module X OUT Direction Control From Module P1DIR.x P1SEL.x Pad Logic Bus Keeper TST Fuse 60 kΩ Fuse Blow Control Control By JTAG TDO Controlled By JTAG P1.x TDI P1.x TST TST TMS TST TCK TST Controlled by JTAG TST P1.x P1.x NOTE: The test pin should be protected from potential EMI and ESD voltage spikes. This may require a smaller external pulldown resistor in some applications. x = Bit identifier, 4 to 7 for port P1 During programming activity and during blowing of the fuse, the pin TDO/TDI is used to apply the test input for JTAG circuitry. P1.7/TDI/TDO P1.6/TDI/TCLK P1.5/TMS P1.4/TCK Typical TEST GND PnSel.x PnDIR.x Direction control from module † Signal from or to Timer_A NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P2, P2.0 to P2.2, input/output with Schmitt trigger EN D See Note 1 See Note 2 See Note 2 See Note 1 GND VCC P2.0 − P2.2 Interrupt Edge Select EN Set Q P2IE.x P2IFG.x P2IRQ.x Interrupt Flag P2IES.x P2SEL.x Module X IN P2IN.x P2OUT.x Module X OUT Direction Control From Module P2DIR.x P2SEL.x Pad Logic NOTE: x = Bit Identifier, 0 to 2 for port P2 0: Input 1: Output Bus Keeper CAPD.X PnSel.x PnDIR.x Direction control from module † Signal from or to Timer_A NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Port P2, P2.3 to P2.4, input/output with Schmitt trigger EN D See Note 1 See Note 2 See Note 2 See Note 1 GND VCC P2.3 Interrupt Edge Select EN Set Q P2IE.3 P2IFG.3 P2IRQ.3 Interrupt Flag P2IES.3 P2SEL.3 Module X IN P2IN.3 P2OUT.3 Module X OUT Direction Control From Module P2DIR.3 P2SEL.3 Pad Logic 0: Input 1: Output Bus Keeper CAPD.3 EN D See Note 1 See Note 2 See Note 2 See Note 1 P2.4 Interrupt Edge SelectEN Set Q P2IE.4 P2IFG.4 P2IRQ.4 Interrupt Flag P2IES.4 P2SEL.4 Module X IN P2IN.4 P2OUT.4 Module X OUT Direction Control From Module P2DIR.4 P2SEL.4 Pad Logic 0: Input 1: Output Bus Keeper CAPD.4 Comparator_A Reference BlockCAREF CAREF CAEXP2CA CAF CCI1B 0 V VCC GND PnSel.x PnDIR.x Direction control from module † Signal from Timer_A NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P2, P2.5, input/output with Schmitt trigger and ROSC function for the Basic Clock module EN D See Note 1 See Note 2 See Note 2 See Note 1 GND VCC P2.5 Interrupt Edge Select EN Set Q P2IE.5 P2IFG.5 P2IRQ.5 Interrupt Flag P2IES.5 P2SEL.5 Module X IN P2IN.5 P2OUT.5 Module X OUT Direction Control From Module P2DIR.5 P2SEL.5 Pad Logic NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad Bus Keeper 0 1VCC Internal to Basic Clock Module DCOR DC Generator 0: Input 1: Output CAPD.5 PnSel.x PnDIR.x Direction control from module NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions 2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
MSP430C11x1, MSP430F11x1A MIXED SIGNAL MICROCONTROLLER SLAS241I − SEPTEMBER 1999 − REVISED DECEMBER 2008 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Port P2, unbonded bits P2.6 and P2.7 EN D Interrupt Edge Select EN Set Q P2IE.x P2IFG.x P2IRQ.x Interrupt Flag P2IES.x P2SEL.x Module X IN P2IN.x P2OUT.x Module X OUT Direction Control From Module P2DIR.x P2SEL.x Bus Keeper 0: Input 1: Output Node Is Reset With PUC PUC NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins P2Sel.x P2DIR.x Direction control from module NOTE 1: Unbonded bits 6 and 7 of port P2 can be used as software interrupt flags. The interrupt flags can only be influenced by software. They work then as a software interrupt.
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is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. check mode has the potential to be activated. Figure 13. Fuse Check Mode Current, MSP430F11x1A and MSP430C11x1 access key is used. Also, see the bootstrap loader section for more information.
www.ti.com 28-Oct-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples MSP430C1101 ACTIVE TBD Call TI Call TI -40 to 85 MSP430F1101AIDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 4F1101A MSP430F1101AIDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 4F1101A MSP430F1101AIDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 M430F1101A MSP430F1101AIDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 M430F1101A MSP430F1101AIPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 430F1101A MSP430F1101AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 430F1101A MSP430F1101AIRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F 1101A MSP430F1101AIRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F 1101A MSP430F1101IDW OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 M430F1101 MSP430F1101IDWR NRND SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 M430F1101 MSP430F1101IPW OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85 430F1101 MSP430F1101IPWR OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85 430F1101 MSP430F1111AIDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 4F1111A MSP430F1111AIDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 4F1111A MSP430F1111AIDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 M430F1111A MSP430F1111AIDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 M430F1111A MSP430F1111AIPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 430F1111A
www.ti.com 28-Oct-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples MSP430F1111AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 430F1111A MSP430F1111AIRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F 1111A MSP430F1111AIRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F 1111A MSP430F1121AIDGV ACTIVE TVSOP DGV 20 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 4F1121A MSP430F1121AIDGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 4F1121A MSP430F1121AIDW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 M430F1121A MSP430F1121AIDWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 M430F1121A MSP430F1121AIPW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 430F1121A MSP430F1121AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 430F1121A MSP430F1121AIRGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F 1121A MSP430F1121AIRGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 M430F 1121A MSP430F1121CY NRND DIESALE Y 0 TBD Call TI Call TI -40 to 85 MSP430F1121IDW NRND SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 M430F1121 MSP430F1121IDWR NRND SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 M430F1121 MSP430F1121IPW NRND TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 430F1121 MSP430F1121IPWR NRND TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 430F1121 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
www.ti.com 28-Oct-2014 Addendum-Page 3 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 18-Mar-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F1101AIDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F1101AIRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F1101AIRGET VQFN RGE 24 250 210.0 185.0 35.0 MSP430F1101IDWR SOIC DW 20 2000 367.0 367.0 45.0 MSP430F1111AIDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F1111AIDWR SOIC DW 20 2000 367.0 367.0 45.0 MSP430F1111AIRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F1111AIRGET VQFN RGE 24 250 210.0 185.0 35.0 MSP430F1121AIDGVR TVSOP DGV 20 2000 367.0 367.0 35.0 MSP430F1121AIDWR SOIC DW 20 2000 367.0 367.0 45.0 MSP430F1121AIRGER VQFN RGE 24 3000 367.0 367.0 35.0 MSP430F1121AIRGET VQFN RGE 24 250 210.0 185.0 35.0 MSP430F1121IDWR SOIC DW 20 2000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 18-Mar-2015 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C TYP10.63 9.97
2.65 MAX
18X 1.27 20X 0.51 0.31 11.43 TYP0.33 0.10 0 - 8 0.3 0.1 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 13.0 12.6 B 7.6 7.4 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. 1 20
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.200
www.ti.com EXAMPLE BOARD LAYOUT (9.3)
0.07 MAX
0.07 MIN
20X (2) 20X (0.6) 18X (1.27) (R ) TYP 0.05 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC SYMM SYMM LAND PATTERN EXAMPLE SCALE:6X 10 11 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (9.3) 18X (1.27) 20X (0.6) 20X (2) 4220724/A 05/2016 SOIC - 2.65 mm max heightDW0020A SOIC NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 10 11 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X
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