M41T56_V01 STM | Alldatasheet
Document overview
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- PDF pages: 27
Technical content
Datasheet sections
- 1 Description
- 2 Operation
- 2.1.1 Bus not busy
- 2.1.2 Start data transfer
- 2.1.3 Stop data transfer
- 2.1.4 Data valid
- 2.1.5 Acknowledge
- 2.2 Read mode
- 2.3 Write mode
- 2.4 Data retention mode
- 3 Clock operation
- 3.1 Clock calibration
- 3.2 Output driver pin
- 3.3 Initial power-on defaults
- 4 Maximum ratings
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Part numbering
- 8 References
- 9 Revision history
Features
■ Counters for seconds, minutes, hours, day, date, month, years, and century ■ 32 KHz crystal oscillator integrating load capacitance (12.5 pF) providing exceptional oscillator stability and high crystal series resistance operation ■ Serial interface supports I2C bus (100 kHz protocol) ■ Ultra-low battery supply current of 450 nA (typ at 3 V) ■ 5 V ±10% supply voltage ■ Timekeeping down to 2.5 V ■ Automatic power-fail detect and switch circuitry ■ 56 bytes of general purpose RAM ■ Software clock calibration to compensate crystal deviation due to temperature ■ Automatic leap year compensation ■ Operating temperature of –40 °C to 85 °C ■ Available in an 8-lead, 150-mil, plastic SOIC (SO8) ■ RoHS compliant – Lead-free second level interconnect SO8 150-mil width
1 Description
for the clock/calendar function and are configured in binary coded decimal (BCD) format. address register is incremented automatically after each WRITE or READ data byte. sustain the RAM and clock operations can be supplied from a small lithium coin cell. M41T56 is supplied in an 8-lead plastic SOIC package. Figure 1. Logic diagram
2 Operation
The M41T56 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order: 1. Seconds register 2. Minutes register 3. Century/hours register 4. Day register 5. Date register 6. Month register 7. Y ears register 8. Control register 9. RAM The clock continually monitors V CC for an out of tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. When VCC falls below VBAT, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. Upon power-up, the device switches from battery to V CC at VBAT and recognizes inputs when VCC goes above VPFD volts. 2.1 2-wire bus characteristics This bus is intended for communication between different ICs. It consists of two lines: one bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is high.
- Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
2.1.3 Stop data transfer
2.1.4 Data valid
changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
2.1.5 Acknowledge
reception of each byte that has been clocked out of the slave transmitter. Figure 4. Serial bus data transfer sequence
2.2 Read mode
last one stored in the pointer, see Figure 9 on page 11. Table 2. AC characteristics
- Valid for ambient operating temperature: T A = –40 to 85 °C; VCC = 4.5 to 5.5 V (except where noted).
- Transmitter must internally provi de a hold time to bridge the undefined region (300 ns max.) of the falling
Figure 7. Slave address location Figure 8. Read mode sequence Figure 9. Alternative read mode sequence
0100011 MSB
2.3 Write mode
2.4 Data retention mode
write protection continues for tREC. Figure 10. Write mode sequence
3 Clock operation
prevent a transition of data during the READ. Table 3. Register map (1)
0 ST 10 Seconds Seconds Seconds 00-59
1 X 10 Minutes Minutes Minutes 00-59
- When CEB is set to '1,' CB toggles from '0' to '1' or from '1' to '0' every 100 years (dependent upon the
initial value set). When CEB is set to '0,' CB does not toggle.
4 X X 10 date Date Date 01-31
7 OUT FT S Calibration Control
3.1 Clock calibration
The M41T56 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25 °C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M41T56 improves to better than ±2 ppm at 25 °C. The oscillation rate of any crystal changes with temperature (see Figure 11 on page 15). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The M41T56 design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 15. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration byte occupies the five lower order bits (D4-D0) in the control register (addr 7). This byte can be set to represent any value between 0 and 31 in binary form. Bit D5 is the sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minutes cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or – 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T56 may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accessed the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the frequency test (FT) bit, the seventh-most significant bit in the control register, is set to a '1,' and the oscillator is running at 32,768 Hz, the FT/OUT pin of the device will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10(XX001010) to be loaded into the calibration byte for correction. Note: Setting or changing the calibration byte does not affect the frequency test output frequency.
Figure 11. Crystal accuracy across temperature Figure 12. Clock calibration
3.2 Output driver pin
location 7 is a '0' and then the FT/OUT pin will be driven low. Note: The FT/OUT pin is open drain which requires an external pull-up resistor.
3.3 Initial power-on defaults
will be set to a '1.' All other register bits will initially power-on in a random state.
4 Maximum ratings
extended periods may affect device reliability. Table 4. Absolute maximum ratings
- For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260 °C. The time above
255 °C must not exceed 30 seconds.
5 DC and AC parameters
Figure 13. AC measurement I/O waveform Table 5. Operating and AC measurement conditions (1)
- Output Hi-Z is defined as the point where data is no longer driven.
Table 6. Capacitance
- Effective capacitance measur ed with power supply at 5V; sampled, not 100% tested.
Figure 14. Power down/up mode AC waveforms Table 7. DC characteristics
- Valid for ambient operating temperature: T A = –40 to 85 °C; VCC = 4.5 to 5.5 V (except where noted).
- STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
Table 8. Crystal electrical characteristics
- These values are externally supplied for the SO 8 package. STMicroelectronics recommends the KDS DT-
- Load capacitors are integrated within the M41T56. Circ uit board layout considerations for the 32.768 kHz
crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
Table 9. Power down/up mode AC characteristics
- Valid for ambient operating temperature: T A = –40 to 85 °C; VCC = 4.5 to 5.5 V (except where noted).
Table 10. Power down/up trip points DC characteristics
- All voltages referenced to V SS.
- Valid for ambient operating temperature: T A = –40 to 85 °C; VCC = 4.5 to 5.5 V (except where noted).
Package mechanical data M41T56 20/27 Doc ID 6104 Rev 9
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
Figure 15. SO8 – 8-pin plastic small package outline Table 11. SO8 – 8-pin plastic small outline, package mechanical data
Figure 16. Carrier tape for SO8 package (150-mil body width) Table 12. Carrier tape dimensions for SO8 package (150-mil body width)
Figure 17. Reel schematic Table 13. Reel dimensions for 12 mm carrier tape - SO8 package (150-mil body width)
7 Part numbering
Table 14. Ordering information scheme
- Not recommended for new design. Contact local ST sales office for availability.
8 References
- The crystal component supplier KDS as cited in Table 8: Crystal electrical characteristics on page 18 can be contacted at http://www.kds.info/index_en.htm
9 Revision history
Table 15. Document revision history 16-Feb-2001 2.0 Reformatted, table added ( Table 16). Section 4, Table 4, Table 8, and Table 14). 13-Dec-2007 8 Updated cover page and Section 8: References. scheme; added Figure 16, 17, Table 12, 13; updated title; minor textual updates.