M41T315Y_07 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 30
Technical content
Datasheet sections
- 1 Description
- 2 Operation
- 2.1 Non-volatile supervisor operation
- 2.2 Data retention
- 3 Clock operation
- 3.1 Clock register information
- 3.2 AM-PM/12/24 mode
- 3.3 Oscillator and reset bits
- 3.4 Zero bits
- 4 Maximum rating
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Part numbering
- 8 Revision history
Features
■ 3.0V, 3.3V, or 5V operating voltage ■ Real-time clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years ■ Automatic leap year correction valid up to 2100 ■ Automatic switch-over and deselect circuitry ■ Choice of power-fail deselect voltages: (VPFD = power-fail deselect voltage) –M 4 1 T 3 1 5 Y(a): VCC = 4.5 to 5.5V 4.25V ≤ VPFD ≤ 4.50V –M 4 1 T 3 1 5 V : VCC = 3.0 to 3.6V 2.80V ≤ VPFD ≤ 2.97V –M 4 1 T 3 1 5 W : VCC = 2.7 to 3.3V 2.60V ≤ VPFD ≤ 2.70V ■ No address space required to communicate with RTC ■ Provides nonvolatile supervisor functions for battery backup of SRAM ■ Full ±10% VCC operating range ■ Industrial operating temperature range (–40 to +85°C) ■ Ultra-low battery supply current of 500nA (max) ■ Optional packaging includes A 28-lead SOIC and SNAPHAT ® top (to be ordered separately) ■ SNAPHAT package provides direct connection for a snaphat top, which contains the battery and crystal ■ RoHS compliant – Lead-free second level interconnect a. Contact local ST sales office for availability. SO16 (MQ) SNAPHAT (SH) battery & crystal SOH28 (MH)
Table 12. SO16 - 16-lead plastic small outline (150 mils body width), package mechanical data . . . 23 Table 14. SH - 4-pin SNAPHAT housing for 48mAh battery and crystal, package mechanical data . 25 Table 15. SH - 4-pin SNAPHAT housing for 120mAh ba ttery and crystal, package mechanical data 26
M41T315Y, M41T315V, M41T315W Description
1 Description
The M41T315Y/V/W RTC Supervisor is a combination of a CMOS TIMEKEEPER® and a nonvolatile memory supervisor. Power is constantly monitored by the memory supervisor. In the event of power instability or absence, an external battery maintains the timekeeping operation and provides power for a CMOS static RAM by switching on and invoking write protection to prevent data corruption in the memory and RTC. The clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The last day of the month is automatically adjusted for months with less than 31 days, including leap year correction. The clock operates in one of two formats:
- a 12-hour mode with an AM/PM indicator; or
- a 24-hour mode The nonvolatile supervisor supplies all the necessary support circuitry to convert a CMOS RAM to a nonvolatile memory. The M41T315Y/V/W can be interfaced with RAM without leaving gaps in memory. The M41T315Y/V/W is supplied in a 28-lead SOIC SNAPHAT® package (which integrates both crystal and battery in a single SNAPHAT top) or a-16 pin SOIC. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion. The 28-pin SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4TXX-BR12SH” (see Table 17 on page 28). Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
Figure 1. Logic diagram Table 1. Signal names
Figure 4. Block diagram
Figure 5. M41T315Y/V/W to RAM/clock interface
Operation M41T315Y, M41T315V, M41T315W
2 Operation
Figure 6 on page 11 illustrates the main elements of the device. The following paragraphs describe the signals and functions. Communication with the clock is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive WRITE cycles containing the proper data on data in (D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the chip enable output pin (CEO After recognition is established, the next 64 READ or WRITE Cycles either extract or update data in the clock and CEO remains high during this time, disabling the connected memory (see Table 2 on page 11). Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable input (CEI), output enable (OE), and WRITE enable (WE). Initially, a READ cycle using the CEI and OE control of the clock starts the pattern recognition sequence by moving the pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive WRITE cycles are executed using the CEI and WE control of the clock. These 64 WRITE cycles are used only to gain access to the clock. When the first WRITE cycle is executed, it is compared to the first bit of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next WRITE cycle. If a match is not found, the pointer does not advance and all subsequent WRITE cycles are ignored. If a READ cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 WRITE cycles as described above until all the bits in the comparison register have been matched (see Figure 8 on page 14). With a correct match for 64 bits, access to the registers is enabled and data transfer to or from the timekeeping registers may proceed. The next 64 cycles will cause the device to either receive data on D, or transmit data on Q, depending on the level of OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CEI cycles without interrupting the pattern recognition sequence or data transfer sequence to the device. For a SO16 pin package, a standard 32.768 kHz quartz crystal can be directly connected to the M41T315Y/V/W via pins 1 and 2 (XI, XO). The crystal selected for use should have a specified load capacitance (C L) of 12.5 pF (see Table 10 on page 21).
2.1 Non-volatile supervisor operation
detection and write protection. VPFD. Figure 5 on page 9 illustrates a typical RAM/clock interface. Figure 6. Read mode waveforms Table 2. Operating modes
- See Table 11 on page 21 for details.
Figure 7. Write mode waveforms Table 3. AC electrical characteristics (M41T315Y)
- Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where noted).
- t WR is a function of the latter occurring edge of WE or CEI.
- t DH and tDS are functions of the first occurring edge of WE or CEI in RAM mode.
Table 4. AC electrical characteristics (M41T315V/W)
- Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V (except where noted).
- t WR is a function of the latter occurring edge of WE or CEI.
- t DH and tDS are functions of the first occurring edge of WE or CEI in RAM mode.
Figure 8. Comparison register definition being accidentally duplicated and sending aberrant entries to the RTC is less than 1 in 1019. This pattern is sent to the clock LSB to MSB.
2.2 Data retention
M41T315Y, M41T315V, M41T315W Operation use. The data retention current value of the SRAMs can then be added to the IBAT value of the M41T315Y/V/W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT ® of your choice can then be divided by this current to determine the amount of data retention available (see Table 17 on page 28). For a further more detailed review of lifetime calculations, please see Application Note AN1012.
Clock operation M41T315Y, M41T315V, M41T315W
3 Clock operation
3.1 Clock register information
Clock information is contained in eight registers of 8 bits, each of which is sequentially accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the clock registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These READ/WRITE registers are defined in Table 5 on page 17. Data contained in the clock registers is in binary coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping though all eight registers, starting with Bit 0 of Register 0 and ending with Bit 7 of Register 7.
3.2 AM-PM/12/24 mode
Bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, Bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, Bit 5 is the second 10-hour bit (20-23 hours).
3.3 Oscillator and reset bits
Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the reset pin input. When the Reset Bit is set to logic '1,' the reset input pin is ignored. When the Reset Bit is set to logic '0,' a low input on the reset pin will cause the device to abort data transfer without changing data in the timekeeping registers. Reset operates independently of all other inputs. Bit 5 controls the oscillator. When set to logic '0,' the oscillator turns on and the real-time clock/calendar begins to increment.
3.4 Zero bits
Registers 1, 2, 3, 4, 5, and 6 contain one (1) or more bits that will always read logic '0.' When writing to these locations, either a logic '1' or '0' is acceptable.
Figure 9. Reset pulse waveform Table 5. RTC register map
4 Maximum rating
Program and other relevant quality documents. Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. Table 6. Ablolute maximum ratings
- For SO package, Lead-free (Pb-fr ee) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed
245°C for greater than 30 seconds).
5 DC and AC parameters
the measurement conditions when using the quoted parameters. Figure 10. AC testing load circuit Table 7. DC and AC measurement conditions Table 8. Capacitance
- Effective capacitance measured with power supply at 5V; sampled only; not 100% tested.
Table 9. DC characteristics
- Applies to all input pins except RST , which is pulled internally to VCCI.
- Measured without RAM connected.
- ICCO1 is the maximum average load current the device can supply to external memory.
- Voltages are referenced to Ground.
- Measured with load shown in Figure 10 on page 19.
- ICCO2 is the maximum average load current that the dev ice can supply to memory in the battery backup mode.
Figure 11. Power down/up mode AC waveforms Table 10. Crystal electrical characteristics (externally supplied)
- These values are externally supplied. STMicroelectronics recommends the KDS DT-38:
http://www.kdsj.co.jp for further information on this crystal type.
- Load capacitors are integrated within the M41T315Y/V/W . Circuit board layout considerations for the
Table 11. Power down/up trip points DC characteristics
- Measured with load shown in Figure 10 on page 19.
- Input pulse rise and fall times equal 10ns
Package mechanical data M41T315Y, M41T315V, M41T315W
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 12. SO16 - 16-lead plasti c small outline, package outline Table 12. SO16 - 16-lead plastic small outline (150 mils body width), package
Figure 13. SOH28 - 28-lead plastic small outline, package outline Note: Drawing is not to scale. Table 13. SOH28 - 28-lead plastic small outline, package mechanical data
Figure 14. SH - 4-pin SNAPHAT housing for 48mAh battery and crystal, package Table 14. SH - 4-pin SNAPHAT housing for 48mAh battery and crystal, package
Figure 15. SH - 4-pin SNAPHAT housing for 120mAh battery and crystal, package Table 15. SH - 4-pin SNAPHAT housing for 120mAh battery and crystal, package
7 Part numbering
Table 16. Ordering information scheme
- Contact local sales office
- The SOIC package (SOH28) requires the SNAPHAT ® battery package which is ordered separately under the part number
“M4Txx-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in tape & reel form (see Table 17 on page 28).
drain the lithium button-cell battery. ST sales office nearest you. Table 17. SNAPHAT battery table
8 Revision history
Table 18. Document revision history Section 6: Package mechanical data; updated Table 6.