M41T256Y_07 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 30
Technical content
Datasheet sections
- 1 Summary
- 2 Operating modes
- 2.1.1 Bus not busy
- 2.1.2 Start data transfer
- 2.1.3 Stop data transfer
- 2.1.4 Data valid
- 2.1.5 Acknowledge
- 2.2 Read mode
- 2.3 Write mode
- 2.4 Data retention mode
- 2.5 Sleep mode
- 3 Clock operation
- 3.1 Reading the clock
- 3.2 Setting the clock
- 3.3 Stopping and starting the oscillator
- 3.4 Power-on reset
- 3.5 Tamper indication circuit
- 3.6 Tamper event time-stamp
- 3.7 Calibrating the clock
- 3.8 Battery low warning
- 3.9 Preferred power-on/battery attach defaults
- 4 Maximum rating
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Part numbering
Features
■ 5V operating voltage ■ Serial interface supports extended I2C bus addressing (400kHz) ■ Automatic switchover and deselect circuitry ■ Power-fail deselect voltages: –M 4 1 T 2 5 6 Y : VCC = 4.5 V to 5.5V; VPFD = 4.2V < VPFD < 4.5V ■ Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, and year ■ Programmable software clock calibration ■ 32,752 bytes of general purpose RAM ■ Microprocessor power-on reset ■ Holds microprocessor in reset until supply voltage reaches stable operating level ■ Automatic address-incrementing ■ Tamper indication circuit with time-stamp ■ Sleep mode function ■ Available in ST’s 44-lead SNAPHAT® SOIC - mates with ST’s removable/replaceable SNAPHAT ® battery/crystal top (ordered separately) ■ RoHS compliant – Lead-free second level interconnect SOH44 (MH) SNAPHAT (SH) crystal/battery
1 Summary
The M41T256Y Serial TIMEKEEPER® SRAM is a low power 256Kbit static CMOS SRAM organized as 32K words by 8 bits. A built-in 32.768kHz oscillator (external crystal controlled) and 8 bytes of the SRAM (see Table 3 on page 18) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T256Y has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a lithium button-cell supply when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, and power-on reset. The eight clock address locations contain the year, month, date, day, hour, minute, second, and tenths/hundredths of seconds in 24- hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The first clock address location (7FF8h) stores the clock software calibration settings as well as the write clock bit. The M41T256Y is supplied in a 44-lead SOIC SNAPHAT ® package (MH - which integrates both crystal and battery in a single SNAPHAT top). The 44-pin, 330mil SOIC provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the completion of the surface-mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion. The 44-pin SOIC and crystal/battery packages are shipped separately in plastic, anti-static tubes or in Tape & Reel form. For the 44-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4Txx- BR12SH” (see Table 14 on page 28). Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium, button-cell battery.
Figure 1. Logic diagram
- For 44-pin SNAPHAT (MT) package only.
Table 1. Signal names
2 Operating modes
The M41T256Y clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 256K bytes contained in the device can then be accessed sequentially in the following order: 0-7FEF = General purpose RAM 7FF0-7FF6 = Reserved 7FF7h = Tenths/hundredths register 7FF8h = Control register 7FF9h = Seconds register 7FFAh = Minutes register 7FFBh = Hour register 7FFCh = Tamper/day register 7FFDh = Date register 7FFEh = Month register 7FFFh = Y ear register The M41T256Y clock continually monitors V CC for an out-of tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out-of-tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD plus tREC. For more information on Battery Storage Life refer to Application Note AN1012. 2.1 2-wire bus characteristics The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is high.
- Changes in the data line, while the clock line is high, will be interpreted as control signals. Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
Both data and clock lines remain High.
2.1.2 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
2.1.3 Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
2.1.4 Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called “master.” The devices that are controlled by the master are called “slaves.”
2.1.5 Acknowledge
Each byte of eight bits is followed by one acknowledge clock pulse. This acknowledge clock pulse is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.
Figure 6. Bus timing requirements sequence Table 2. AC characteristics
2.2 Read mode
transmitted and the master receiver will send an acknowledge bit to the slave transmitter.
- Valid for ambient operating temperature: T A = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
- Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL
STOP condition to the slave transmitter (see Figure 8 on page 14). consecutive READ or WRITE cycles are performed. is read is the last one stored in the pointer (see Figure 9 on page 14). Figure 7. Slave address location Note: The most significant bit is sent first.
0100011 MSB
2.3 Write mode
byte A(0) is a “Don’t care”). it has received each address byte. Figure 10. Write mode sequence
2.4 Data retention mode
2.5 Sleep mode
In order to minimize the battery current draw while in storage, the M41T256Y provides the user with a battery “sleep mode,” which disconnects the RAM memory array from the external Lithium battery normally used to provide non-volatile operation in the absence of V CC. This can significantly extend the lifetime of the battery, when non-volatile operation is not needed. Note: The sleep mode will remove power from the RAM array only and not affect the data retention of the TIMEKEEPER Registers (7FF0h through 7FFFh - this includes the Calibration Register). The sleep mode (SLP) Bit located in register 7FF8h (D6), must be set to a '1' by the user while the device is powered by VCC. This will “arm” the sleep mode latch, but not actually disconnect the RAM array from power until the next power-down cycle. This protects the user from immediate data loss in the event he inadvertently sets the SLP Bit. Once V CC falls below VSO (VBAT), the sleep mode circuit will be engaged and the RAM array will be isolated from the battery, resulting in both a lower battery current, and a loss of RAM data. Note: Upon initial battery attach or initial power application without the battery, the state of the SLP Bit will be undetermined. Therefore, the SLP Bit should be initialized to '0' by the user. Additional current reduction can be achieved by setting the STOP (ST) Bit in register 7FF9h (D7), turning off the clock oscillator. This combination will result in the longest possible battery life, but also loss of time and data. When the device is again powered-up, the user should first read the SLP Bit to determine if the device is currently in sleep mode, then reset the bit to '0' in order to disable the sleep mode (this will NOT be automatically taken care of during the power-up). Note: See AN1570, “M41T256Y Sleep Mode Function” for more information on sleep mode and battery lifetimes.
3 Clock operation
Y ear, month, and date are contained in the last three registers of the TIMEKEEPER® register map (see Table 3 on page 18). Bits D0 through D2 of the next register contain the day (day of week). Finally, there are the registers containing the seconds, minutes, and hours, respectively. The first clock register is the control register (this is described in the clock calibration section). The nine clock registers may be read one byte at a time, or in a sequential block. The control register (Address location 7FF8h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the nine clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the read.
3.1 Reading the clock
The nine byte clock register (see Table 3 on page 18) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (7FF9h to 7FFFh). The update will resume either due to a stop condition or when the pointer increments to a RAM address. This prevents reading data in transition. The TIMEKEEPER ® cells in the register map are only data registers and not actual clock counters, so updating the registers can be halted without disturbing the clock itself.
3.2 Setting the clock
Bit D7 of the control register (7FF8h) is the write clock bit. Setting the write clock bit to a '1' will allow the user to write the desired day, date, and time data in 24-hour BCD format. Resetting the write clock bit to a '0' then transfers the values of all time registers (7FF8h- 7FFFh) to the actual clock counters and resets the internal divider (or clock) chain. Note: The tenths/hundred ths of seconds register will automatically be reset to zero when the WRITE clock bit is set. Other register bits such as FT, TEB, and ST may be written without setting the WC Bit. In such cases, the clock data will be undisturbed and will retain their previous values.
3.3 Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The stop bit (ST) is the most significant bit of the seconds register. Setting it to '1' stops the oscillator. Setting it to '0' restarts the oscillator in approximately one second.
Table 3. TIMEKEEPER ® register map Note: 7FF0h through 7FF6h are in valid addresses and when read will return arbitrary data.
3.4 Power-on reset
should be chosen to control rise time.
7 F F 6 h XXXXXXXX R e s e r v e d
7 F F 5 h XXXXXXXX R e s e r v e d
7 F F 4 h XXXXXXXX R e s e r v e d
7 F F 3 h XXXXXXXX R e s e r v e d
7 F F 2 h XXXXXXXX R e s e r v e d
7 F F 1 h XXXXXXXX R e s e r v e d
7 F F 0 h XXXXXXXX R e s e r v e d
3.5 Tamper indication circuit
The M41T256Y provides an independent input pin, the tamper pin (TP) which can be used to monitor a signal which can result in the setting of the tamper bit (TB) if the tamper enable bit (TEB) is set to a '1.' The tamper pin is triggered by being connected to V CC/VBAT through an external switch. This switch is normally open in the application, allowing the pin to be “floating” (internally latched to V SS when TEB is set). When this switch is closed (connecting the pin to VCC/VBAT), the tamper bit will be immediately set. This allows the user to determine if the device has been physically moved or tampered with. The tamper bit is a “read only” bit and is reset only by taking the tamper pin to ground and resetting the tamper enable bit to '0.' This function operates both under normal power, and in battery back-up. If the switch closes during a power-down condition, the bit will still be set correctly. Note: Upon initial battery attach or initial power application without the battery, the state of TEB (and TB) will be undetermined. Therefore TEB must be initialized to a '0.'
3.6 Tamper event time-stamp
If a tamper occurs, not only will the tamper bit be set, but the event will also automatically be time-stamped. This is accomplished by freezing the normal update of the clock registers (7FF7h through 7FFFh) immediately following a tamper event. Thus, when tampering occurs, the user may first read the time registers to determine exactly when the tamper event occurred, then re-enable the clock update to the current time (and reset the Tamper Bit, TB) by resetting the tamper enable bit (TEB). The time update will then resume, and after either a stop condition or incrementing the address pointer to a RAM address and back, the clock can be read to determine the current time. Note: The tamper bit (TB) must always be set to '0' in order to read the current time.
3.7 Calibrating the clock
The M41T256Y is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are tested not exceed ±35 ppm (parts per million) oscillator frequency error at 25oC, which equates to about ±1.53 minutes per month. When the calibration circuit is properly employed, accuracy improves to better than +1/–2 ppm at 25°C. The oscillation rate of crystals changes with temperature (see Figure 11 on page 20). Therefore, the M41T256Y design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 12 on page 20. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the control register (7FF8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
that accesses the calibration byte. frequency test output frequency.
3.8 Battery low warning
below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM. CC is applied to the device. power-up via a checksum or other technique.
3.9 Preferred power-on/battery attach defaults
Table 4. Preferred default values
- X = Undetermined; UC = Unchanged
4 Maximum rating
Program and other relevant quality documents. Table 5. Absolute maximum ratings Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
- For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget
not to exceed 180°C for between 90 to 150 seconds). budget not to exceed 245°C for greater than 30 seconds).
5 DC and AC parameters
in their projects match the measurement conditions when using the quoted parameters. Table 6. DC and AC measurement conditions Figure 13. AC testing input/output waveforms Table 7. Capacitance
- Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
Table 8. DC characteristics Table 9. Crystal electrical characteristics (externally supplied)
- Valid for ambient operating temperature: T A = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
- For RST and FT pin (open drain).
- Load capacitors are integrated within the M41T256Y. Circuit board layout considerations for the 32.768kHz crystal of
minimum trace lengths and isolation from RF generating signals should be taken into account.
Figure 14. Power down/up mode AC waveforms Table 10. Power down/up AC characteristics
- Valid for ambient operating temperature: T A = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
- V PFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after
- V PFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
- At 25°C and V CC = 0V with the oscillator running and using M4T32-BR12SH SNAPHAT battery top.
6 Package mechanical data
conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 15. SOH44 – 44-lead plastic small outline, SNAPHAT, package outline Note: Drawing is not to scale. Table 11. SOH44 – 44-lead plastic small outline, SNAPHAT, package mech. data
Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal outline Note: Drawing is not to scale. Table 12. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, mechanical data
7 Part numbering
Table 13. Ordering information scheme drain the lithium button-cell battery. ST sales office nearest you. Table 14. SNAPHAT ® battery table
- The SOIC package (SOH44) requires the SNAPHAT ® battery package which is ordered separately under the part
number “M4Txx-BR12SH” in plastic tubes (see Table 14).
8 Revision history
Table 15. Document revision history 03-Jul-02 1.3 Modify Crystal Electrical Characteristics table footnotes (Table 9). SNAPHAT available (cover page, Summary, Figure 1, Table 1, Table 13).