M41T11_08 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Description
- 2 Operation
- 2.1.1 Bus not busy
- 2.1.2 Start data transfer
- 2.1.3 Stop data transfer
- 2.1.4 Data valid
- 2.1.5 Acknowledge
- 2.2 Read mode
- 2.3 Write mode
- 2.4 Data retention mode
- 3 Clock operation
- 3.1 Clock calibration
- 3.2 Output driver pin
- 3.3 Preferred initial power-on defaults
- 4 Maximum ratings
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Part numbering
- 8 Revision history
Features
■ Counters for seconds, minutes, hours, day, date, month, years and century ■ 32 KHz crystal oscillator integrating load capacitance (12.5 pF) providing exceptional oscillator stability and high crystal series resistance operation ■ Serial interface supports I2C bus (100 kHz protocol) ■ Ultra-low battery supply current of 0.8 µA (typ. at 3 V) ■ 2.0 to 5.5 V clock operating voltage ■ Automatic switchover and deselect circuitry ■ 56 bytes of general purpose RAM ■ Software clock calibration to compensate crystal deviation due to temperature ■ Automatic leap year compensation ■ Operating temperature of –40 to 85°C ■ Packaging includes a 28-lead SOIC and SNAPHAT ® top (to be ordered separately; 3.3 V to 5.0 V supply voltage only) ■ RoHS compliant – Lead-free second level interconnect SO8 (M) SNAPHAT (SH) battery & crystal SOH28 (MH)
Table 13. SH – 4-pin SNAPHAT housing for 48 mAh ba ttery & crystal, package mechanical data . . 25
1 Description
for the clock/calendar function and are configured in binary coded decimal (BCD) format. address register is incremented automatically after each write or read data byte. sustain the RAM and clock operations can be supplied from a small lithium coin cell. for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. BR12SH” (see Table 16 on page 27). since this will drain the lithium button-cell battery. Figure 1. Logic diagram
Figure 4. Block diagram
2 Operation
The M41T11 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order:
- 1st byte: seconds register
- 2nd byte: minutes register
- 3rd byte: century/hours register
- 4th byte: day register
- 5th byte: date register
- 6th byte: month register
- 7th byte: years register
- 8th byte: control register
- 9th - 64th bytes: RAM The M41T11 clock continually monitors VCC for an out of tolerance condition. Should VCC fall below VSO, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. Upon power-up, the device switches from battery to V CC at VSO and recognizes inputs. 2.1 2-wire bus characteristics This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is high.
- Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined:
2.1.1 Bus not busy
Both data and clock lines remain high.
2.1.2 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
2.1.3 Stop data transfer
2.1.4 Data valid
changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. “master”. The devices that are controlled by the master are called “slaves”.
2.1.5 Acknowledge
reception of each byte that has been clocked out of the slave transmitter. Figure 5. Serial bus data transfer sequence
2.2 Read mode
(see Figure 9). The address pointer is only incremented on reception of an acknowledge bit. STOP condition to the slave transmitter. last one stored in the pointer (see Figure 10 on page 12). Table 2. AC characteristics
- Valid for ambient operating temperature: T A = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
- Transmitter must internally provi de a hold time to bridge the undefined region (300 ns max.) of the falling
Figure 8. Slave address location Figure 9. Read mode sequence Figure 10. Alternate read mode sequence
0100011 MSB
2.3 Write mode
the slave address and again after it has received the word address and each data byte.
2.4 Data retention mode
protecting itself when VCC falls (see Figure 15). Figure 11. Write mode sequence
3 Clock operation
The eight byte clock register (see Table 3) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are contained within the first three registers. Bits D6 and D7 of clock register 2 (hours register) contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2 of register 3 contain the day (day of week). Registers 4, 5 and 6 contain the date (day of month), month and years. The final register is the control register (this is described in the clock calibration section). Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. Note: In order to guarantee oscillato r startup after the initial power-up, set the ST bit to a '1,' then reset this bit to a '0.' This sequence enables a “kick start” circuit which aids the oscillator startup during worst case conditions of voltage and temperature. The seven clock registers may be read one byte at a time, or in a sequential block. The control register (address location 7) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock registers will be delayed by 250 ms to allow the read to be completed before the update occurs. This will prevent a transition of data during the read. Note: This 250 ms delay affects only the clock register update and does not alter the actual clock time.
3.1 Clock calibration
The oscillation rate of any crystal changes with temperature (see Figure 12 on page 17). counts speeds the clock up, subtracting counts slows the clock down. binary 6 is loaded, the first 12 will be affected, and so on. Table 3. Register map
0 ST 10 seconds Seconds Seconds 00-59
1 X 10 minutes Minutes Minutes 00-59
- When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' every 100 years (dependent upon the
3 X X X X X Day Day 01-07
4 X X 10 date Date Date 01-31
7 OUT FT S Calibration Control
adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T11 may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accessed the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the frequency test (FT) bit, the seventh-most significant bit in the control register, is set to a '1', and the oscillator is running at 32,768 Hz, the FT/OUT pin of the device will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10(XX001010) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test output frequency.
3.2 Output driver pin
When the FT Bit is not set, the FT/OUT pin becomes an output driver that reflects the contents of D7 of the control register. In other words, when D6 of location 7 is a zero and D7 of location 7 is a zero and then the FT/OUT pin will be driven low. Note: The FT/OUT pin is open drain which requires an external pull-up resistor.
3.3 Preferred initial power-on defaults
Upon initial application of power to the device, the FT bit will be set to a '0' and the OUT bit will be set to a '1'. All other register bits will initially power-on in a random state.
4 Maximum ratings
Program and other relevant quality documents. Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. Table 4. Absolute maximum ratings
- Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed
245°C for greater than 30 seconds).
5 DC and AC parameters
Figure 14. AC testing input/output waveform Table 5. Operating and AC measurement conditions (1)
- Output Hi-Z is defined as the point where data is no longer driven.
- Supply voltage for SOH28 is 3.3V to 5.5V.
Table 6. Capacitance
- Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
Table 7. DC characteristics
- Valid for ambient operating temperature: T A = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted).
- STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
- After switchover (V SO), VBAT(min) can be 2.0 V for crystal with RS = 40 KΩ.
- For rechargeable back-up, V BAT(max) may be considered VCC.
Table 8. Crystal electrical characteristics
- These values are externally supp lied if using the SO8 package. STMicroelectronics recommends the KDS
http://www.kdsj.co.jp for further information on this crystal type.
- Load capacitors are integrated within the M41T11. Circ uit board layout considerations for the 32.768 kHz
crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
- All SNAPHAT ® battery:crystal tops meet these specifications.
Figure 15. Power down/up mode AC waveforms Table 9. Power down/up AC characteristics
- Valid for ambient operating temperature: T A = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
- V CC fall time should not exceed 5 mV/µs.
Table 10. Power down/up trip points DC characteristics
- Valid for ambient operating temperature: T A = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
- All voltages referenced to V SS.
- Switchover and deselect point.
Package mechanical data M41T11
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 16. SO8 – 8-lead plastic small outline package outline Table 11. SO8 – 8-lead plastic small outline (150 mils body width) pack. mech. data
Figure 17. SOH28 – 28-lead plastic small outline, battery snaphat package outline Table 12. SOH28 – 28-lead plastic small outline, battery snaphat pack. mech. data
Figure 18. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal package Table 13. SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, package
Figure 19. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package Table 14. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package
7 Part numbering
drain the lithium button-cell battery. ST sales office nearest you. Table 15. Ordering information scheme
- SOH28 supply voltage is 3.3 V to 5.5 V.
- The SOIC package (SOH28) requires the SNAPHAT ® battery package which is ordered separately under
Table 16. SNAPHAT battery table
8 Revision history
Table 17. Revision history Table 10); added SNAPHAT battery table (Table 16). 02-May-2008 8 Updated Figure 16, Table 11, 15.