M41T00_08 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Device overview
- 2 Device operation
- 2.1 Wire bus characteristics
- 2.2 Bus not busy
- 2.3 Start data transfer
- 2.4 Stop data transfer
- 2.5 Data valid
- 2.6 Acknowledge
- 2.7 Characteristics
- 2.8 READ mode
- 2.9 WRITE mode
- 2.10 Data retention mode
- 3 M41T00 clock operation
- 3.1 Clock calibration
- 3.2 Output driver pin
- 3.3 Initial power-on defaults
- 4 Maximum ratings
- 5 DC and AC parameters
- 6 Package mechanical data
- 7 Part numbering
- 8 Revision history
Features
■ For new designs use M41T00S ■ Counters for seconds, minutes, hours, day, month, years, and century ■ 32 kHz crystal oscillator integrating load capacitance (12.5 pF) providing exceptional oscillator stability and high crystal series resistance operation ■ Serial interface supports I2C bus (100 kHz protocol) ■ Ultra low battery supply current of 0.8 µA (typ at 3 V) ■ 2.0 to 5.5 V clock operating voltage ■ Automatic switchover and deselect circuitry (for 3 V application select M41T00S datasheet) ■ Software clock calibration to compensate crystal deviation due to temperature ■ Automatic leap year compensation ■ Operating temperature of -40 to 85 °C
Description
The M41T00 is a low power serial real time clock with a built-in 32.768 kHz oscillator (external crystal controlled). Eight bytes of the RAM are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a two-line bidirectional bus. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T00 clock has a built-in power sense circuit which detects power failures and automatically switches to the battery supply during power failures. The energy needed to sustain the RAM and clock operations can be supplied from a small lithium coin cell. Typical data retention time is in excess of 5 years with a 50 mA/h 3 V lithium cell (see Section 2.10: Data retention mode for AC/DC characteristics). The M41T00 is supplied in 8-lead plastic small outline package. SO8(M)
1 Device overview
Figure 1. Logic symbol Figure 2. SOIC connection Table 1. Pin description
Figure 3. Block diagram
2 Device operation
The M41T00 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device can then be accessed sequentially in the following order: st byte: seconds register 2nd byte: minutes register 3rd byte: century/hours register 4th byte: day register 5th byte: date register 6th byte: month register 7th byte: years register 8th byte: control register The M41T00 clock continually monitors VCC for an out of tolerance condition. Should VCC fall below VSO, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. When VCC falls below VSO, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. Upon power-up, the device switches from battery to V CC at VSO and recognizes inputs.
2.1 Wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is High. Changes in the data line while the clock line is High will be interpreted as control signals. Accordingly, the following bus conditions have been defined:
2.2 Bus not busy
Both data and clock lines remain high.
2.3 Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
2.4 Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
2.5 Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition, a device that gives out a message is called “transmitter”, the receiving device that gets the message is called “receiver”. The device that controls the message is called “master”. The devices that are controlled by the master are called “slaves”.
2.6 Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line high to enable the master to generate the STOP condition.
2.7 Characteristics
2.8 READ mode
transmitter. The address pointer is only incremented on reception of an acknowledge bit. STOP condition to the slave transmitter. last one stored in the pointer. Table 2. AC characteristics
- Valid for ambient operating temperature: T A = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
- Transmitter must internally provi de a hold time to bridge the undefined region (300 ns max) of the falling
Figure 7. Slave address location Figure 8. READ mode sequence Figure 9. Alternate READ mode sequence
0100011 MSB
2.9 WRITE mode
Figure 10. WRITE mode sequences
2.10 Data retention mode
WRITE protecting itself when VCC falls (see Figure 11). Figure 11. Power down/up mode AC waveforms Table 3. RTC power down/up ac characteristics
- Valid for ambient operating temperature: T A = -40 to 85°C; VCC = 2.0 to 5.5 V (except where otherwise noted).
- V CC fall time should not exceed 5 mV/µs.
Table 4. RTC power down/up trip points dc characteristics
- Valid for ambient operating temperature: T A = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where otherwise
- All voltages referenced to V SS.
- Switchover and deselect point.
M41T00 clock operation M41T00
3 M41T00 clock operation
The eight byte clock register (see Table 5) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are contained within the first three registers. Bits D6 and D7 of clock register 2 (century/hours register) contain the century enable bit (CEB) and the century bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2 of register 3 contain the day (day of week). Registers 4, 5 and 6 contain the date (day of month), month and years. The final register is the control register (this is described in the clock calibration section). Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. Note: In order to guarantee oscillator start-up after the initial power-up, set the ST bit to a '1,' then reset this bit to a '0.' This sequence enables a “kick start” circuit which aids the oscillator start-up during worst case conditions of voltage and temperature. The seven clock registers may be read one byte at a time, or in a sequential block. The control register (address location 7) may be accessed independently. Provision has been made to ensure that a clock update does not occur while any of the seven clock addresses are being read. If a clock address is being read, an update of the clock registers will be delayed by 250 ms to allow the read to be completed before the update occurs. This will prevent a transition of data during the read. Note: Note: This 250 ms delay affects only the cl ock register update and does not alter the actual clock time.
3.1 Clock calibration
subtracting counts slows the clock down. binary 6 is loaded, the first 12 will be affected, and so on. Table 5. Register map
0 ST 10 seconds Seconds Seconds 00-59
1 X 10 minutes Minutes Minutes 00-59
2 CEB
- When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent
upon the initial value set).When CEB is set to '0', CB will not toggle.
4 X X 10 date Date Date 01-31
7 OUT FT S Calibration Control
designer has to do is provide a simple utility that accessed the calibration byte. direction of oscillator frequency shift at the test temperature. Figure 12. Crystal accuracy across temperature
Figure 13. Clock calibration
3.2 Output driver pin
of address 7 is a zero and then the FT/OUT pin will be driven low. Note: The FT/OUT pin is open drain which requires an external pull-up resistor.
3.3 Initial power-on defaults
will be set to a '1'. All other register bits will initially power on in a random state.
4 Maximum ratings
this specification is not implied. Caution: Negative undershoots below -0.3 V are not allowed on any pin while in the backup mode. Table 6. Absolute maximum ratings
- Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30
5 DC and AC parameters
the measurement conditions when using the quoted parameters. Figure 14. AC testing input/output waveform Table 7. Operating and AC measurement conditions (1)
- Output Hi-Z is defined as the point where data is no longer driven.
Table 8. Capacitance
- Effective capacitance m easured with power supply at 3.3 V; sampled only, not 100% tested
Table 9. DC characteristics
- Valid for ambient operating temperature: T A = –40 to 85 °C; VCC = 2.0 to 5.5 V (except where otherwise noted).
- STMicroelectronics recommends the RAYOVAC BR12 25 or BR1632 (or equivalent)as the battery supply.
- After switchover (V SO), VBAT(min) can be 2.0 V for crystal with RS = 40 KΩ.
- For rechargeable backup, V BAT(max) may be considered VCC.
Table 10. Crystal electrical characteristics
- Externally supplied if using the SO 8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning
- Load capacitors are integrated within the M41T00. Circuit boar d layout considerations for the 32.768 kHz crystal of
minimum trace lengths and isolation from RF generating signals should be taken into account.
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 15. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical data Table 11. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical data
7 Part numbering
Table 12. Ordering information scheme
8 Revision history
Table 13. Revision history width, package mechanical data.